1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
15 include "R600InstrFormats.td"
17 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
18 InstR600 <outs, ins, asm, pattern, NullALU> {
20 let Namespace = "AMDGPU";
23 def MEMxi : Operand<iPTR> {
24 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
25 let PrintMethod = "printMemOperand";
28 def MEMrr : Operand<iPTR> {
29 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
32 // Operands for non-registers
34 class InstFlag<string PM = "printOperand", int Default = 0>
35 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
39 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
40 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
41 let PrintMethod = "printSel";
43 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
44 let PrintMethod = "printBankSwizzle";
47 def LITERAL : InstFlag<"printLiteral">;
49 def WRITE : InstFlag <"printWrite", 1>;
50 def OMOD : InstFlag <"printOMOD">;
51 def REL : InstFlag <"printRel">;
52 def CLAMP : InstFlag <"printClamp">;
53 def NEG : InstFlag <"printNeg">;
54 def ABS : InstFlag <"printAbs">;
55 def UEM : InstFlag <"printUpdateExecMask">;
56 def UP : InstFlag <"printUpdatePred">;
58 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
59 // Once we start using the packetizer in this backend we should have this
61 def LAST : InstFlag<"printLast", 1>;
62 def RSel : Operand<i32> {
63 let PrintMethod = "printRSel";
65 def CT: Operand<i32> {
66 let PrintMethod = "printCT";
69 def FRAMEri : Operand<iPTR> {
70 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
73 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
74 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
75 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
76 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
77 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
78 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
81 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
87 // Class for instructions with only one source register.
88 // If you add new ins to this instruction, make sure they are listed before
89 // $literal, because the backend currently assumes that the last operand is
90 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
91 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
92 // and R600InstrInfo::getOperandIdx().
93 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
94 InstrItinClass itin = AnyALU> :
95 InstR600 <(outs R600_Reg32:$dst),
96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
99 BANK_SWIZZLE:$bank_swizzle),
100 !strconcat(" ", opName,
101 "$clamp $last $dst$write$dst_rel$omod, "
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
103 "$pred_sel $bank_swizzle"),
107 R600ALU_Word1_OP2 <inst> {
113 let update_exec_mask = 0;
115 let HasNativeOperands = 1;
117 let DisableEncoding = "$literal";
119 let Inst{31-0} = Word0;
120 let Inst{63-32} = Word1;
123 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
124 InstrItinClass itin = AnyALU> :
125 R600_1OP <inst, opName,
126 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
129 // If you add our change the operands for R600_2OP instructions, you must
130 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
131 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
132 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
133 InstrItinClass itin = AnyALU> :
134 InstR600 <(outs R600_Reg32:$dst),
135 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
136 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
137 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
138 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
139 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
140 BANK_SWIZZLE:$bank_swizzle),
141 !strconcat(" ", opName,
142 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
143 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
144 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
145 "$pred_sel $bank_swizzle"),
149 R600ALU_Word1_OP2 <inst> {
151 let HasNativeOperands = 1;
153 let DisableEncoding = "$literal";
155 let Inst{31-0} = Word0;
156 let Inst{63-32} = Word1;
159 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
160 InstrItinClass itim = AnyALU> :
161 R600_2OP <inst, opName,
162 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
166 // If you add our change the operands for R600_3OP instructions, you must
167 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
168 // R600InstrInfo::buildDefaultInstruction(), and
169 // R600InstrInfo::getOperandIdx().
170 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
171 InstrItinClass itin = AnyALU> :
172 InstR600 <(outs R600_Reg32:$dst),
173 (ins REL:$dst_rel, CLAMP:$clamp,
174 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
175 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
176 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
177 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
178 BANK_SWIZZLE:$bank_swizzle),
179 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
180 "$src0_neg$src0$src0_rel, "
181 "$src1_neg$src1$src1_rel, "
182 "$src2_neg$src2$src2_rel, "
188 R600ALU_Word1_OP3<inst>{
190 let HasNativeOperands = 1;
191 let DisableEncoding = "$literal";
194 let Inst{31-0} = Word0;
195 let Inst{63-32} = Word1;
198 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
199 InstrItinClass itin = VecALU> :
200 InstR600 <(outs R600_Reg32:$dst),
208 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
210 def TEX_SHADOW : PatLeaf<
212 [{uint32_t TType = (uint32_t)N->getZExtValue();
213 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
217 def TEX_RECT : PatLeaf<
219 [{uint32_t TType = (uint32_t)N->getZExtValue();
224 def TEX_ARRAY : PatLeaf<
226 [{uint32_t TType = (uint32_t)N->getZExtValue();
227 return TType == 9 || TType == 10 || TType == 15 || TType == 16;
231 def TEX_SHADOW_ARRAY : PatLeaf<
233 [{uint32_t TType = (uint32_t)N->getZExtValue();
234 return TType == 11 || TType == 12 || TType == 17;
238 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
239 dag ins, string asm, list<dag> pattern> :
240 InstR600ISA <outs, ins, asm, pattern> {
257 // CF_ALLOC_EXPORT_WORD0_RAT
258 let Inst{3-0} = rat_id;
259 let Inst{9-4} = rat_inst;
260 let Inst{10} = 0; // Reserved
261 let Inst{12-11} = RIM;
262 let Inst{14-13} = TYPE;
263 let Inst{21-15} = RW_GPR;
264 let Inst{22} = RW_REL;
265 let Inst{29-23} = INDEX_GPR;
266 let Inst{31-30} = ELEM_SIZE;
268 // CF_ALLOC_EXPORT_WORD1_BUF
269 let Inst{43-32} = ARRAY_SIZE;
270 let Inst{47-44} = COMP_MASK;
271 let Inst{51-48} = BURST_COUNT;
274 let Inst{61-54} = cf_inst;
276 let Inst{63} = BARRIER;
279 class LoadParamFrag <PatFrag load_type> : PatFrag <
280 (ops node:$ptr), (load_type node:$ptr),
281 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
284 def load_param : LoadParamFrag<load>;
285 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
286 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
288 def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">;
289 def isR700 : Predicate<"Subtarget.getGeneration() == AMDGPUSubtarget::R700">;
290 def isEG : Predicate<
291 "Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
292 "Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
293 "!Subtarget.hasCaymanISA()">;
295 def isCayman : Predicate<"Subtarget.hasCaymanISA()">;
296 def isEGorCayman : Predicate<"Subtarget.getGeneration() == "
297 "AMDGPUSubtarget::EVERGREEN"
298 "|| Subtarget.getGeneration() =="
299 "AMDGPUSubtarget::NORTHERN_ISLANDS">;
301 def isR600toCayman : Predicate<
302 "Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
304 //===----------------------------------------------------------------------===//
306 //===----------------------------------------------------------------------===//
308 def INTERP_PAIR_XY : AMDGPUShaderInst <
309 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
310 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
311 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
314 def INTERP_PAIR_ZW : AMDGPUShaderInst <
315 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
316 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
317 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
320 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
321 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
325 def DOT4 : SDNode<"AMDGPUISD::DOT4",
326 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
327 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
328 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
332 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
334 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
336 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
337 def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
338 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
339 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
340 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
341 (i32 imm:$DST_SEL_W),
342 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
343 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
344 (i32 imm:$COORD_TYPE_W)),
345 (inst R600_Reg128:$SRC_GPR,
346 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
347 imm:$offsetx, imm:$offsety, imm:$offsetz,
348 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
350 imm:$RESOURCE_ID, imm:$SAMPLER_ID,
351 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
355 //===----------------------------------------------------------------------===//
356 // Interpolation Instructions
357 //===----------------------------------------------------------------------===//
359 def INTERP_VEC_LOAD : AMDGPUShaderInst <
360 (outs R600_Reg128:$dst),
362 "INTERP_LOAD $src0 : $dst",
365 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
366 let bank_swizzle = 5;
369 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
370 let bank_swizzle = 5;
373 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
375 //===----------------------------------------------------------------------===//
376 // Export Instructions
377 //===----------------------------------------------------------------------===//
379 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
381 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
382 [SDNPHasChain, SDNPSideEffect]>;
385 field bits<32> Word0;
392 let Word0{12-0} = arraybase;
393 let Word0{14-13} = type;
394 let Word0{21-15} = gpr;
395 let Word0{22} = 0; // RW_REL
396 let Word0{29-23} = 0; // INDEX_GPR
397 let Word0{31-30} = elem_size;
400 class ExportSwzWord1 {
401 field bits<32> Word1;
410 let Word1{2-0} = sw_x;
411 let Word1{5-3} = sw_y;
412 let Word1{8-6} = sw_z;
413 let Word1{11-9} = sw_w;
416 class ExportBufWord1 {
417 field bits<32> Word1;
424 let Word1{11-0} = arraySize;
425 let Word1{15-12} = compMask;
428 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
429 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
431 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
432 0, 61, 0, 7, 7, 7, cf_inst, 0)
435 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
437 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
438 0, 61, 7, 0, 7, 7, cf_inst, 0)
441 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
443 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
446 def : Pat<(int_R600_store_dummy 1),
448 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
451 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
452 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
453 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
454 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
459 multiclass SteamOutputExportPattern<Instruction ExportInst,
460 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
462 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
463 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
464 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
465 4095, imm:$mask, buf0inst, 0)>;
467 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
468 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
469 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
470 4095, imm:$mask, buf1inst, 0)>;
472 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
473 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
474 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
475 4095, imm:$mask, buf2inst, 0)>;
477 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
478 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
479 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
480 4095, imm:$mask, buf3inst, 0)>;
483 // Export Instructions should not be duplicated by TailDuplication pass
484 // (which assumes that duplicable instruction are affected by exec mask)
485 let usesCustomInserter = 1, isNotDuplicable = 1 in {
487 class ExportSwzInst : InstR600ISA<(
489 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
490 i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
492 !strconcat("EXPORT", " $gpr"),
493 []>, ExportWord0, ExportSwzWord1 {
495 let Inst{31-0} = Word0;
496 let Inst{63-32} = Word1;
499 } // End usesCustomInserter = 1
501 class ExportBufInst : InstR600ISA<(
503 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
504 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
505 !strconcat("EXPORT", " $gpr"),
506 []>, ExportWord0, ExportBufWord1 {
508 let Inst{31-0} = Word0;
509 let Inst{63-32} = Word1;
512 //===----------------------------------------------------------------------===//
513 // Control Flow Instructions
514 //===----------------------------------------------------------------------===//
517 def KCACHE : InstFlag<"printKCache">;
519 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
520 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
521 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
522 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
524 !strconcat(OpName, " $COUNT, @$ADDR, "
525 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
526 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
531 let WHOLE_QUAD_MODE = 0;
534 let Inst{31-0} = Word0;
535 let Inst{63-32} = Word1;
538 class CF_WORD0_R600 {
539 field bits<32> Word0;
546 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
547 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
553 let VALID_PIXEL_MODE = 0;
557 let END_OF_PROGRAM = 0;
558 let WHOLE_QUAD_MODE = 0;
560 let Inst{31-0} = Word0;
561 let Inst{63-32} = Word1;
564 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
565 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
570 let JUMPTABLE_SEL = 0;
572 let VALID_PIXEL_MODE = 0;
574 let END_OF_PROGRAM = 0;
576 let Inst{31-0} = Word0;
577 let Inst{63-32} = Word1;
580 def CF_ALU : ALU_CLAUSE<8, "ALU">;
581 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
583 def FETCH_CLAUSE : AMDGPUInst <(outs),
584 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
590 def ALU_CLAUSE : AMDGPUInst <(outs),
591 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
597 def LITERALS : AMDGPUInst <(outs),
598 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
603 let Inst{31-0} = literal1;
604 let Inst{63-32} = literal2;
607 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
611 let Predicates = [isR600toCayman] in {
613 //===----------------------------------------------------------------------===//
614 // Common Instructions R600, R700, Evergreen, Cayman
615 //===----------------------------------------------------------------------===//
617 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
618 // Non-IEEE MUL: 0 * anything = 0
619 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
620 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
621 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
622 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
624 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
625 // so some of the instruction names don't match the asm string.
626 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
627 def SETE : R600_2OP <
629 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_EQ))]
634 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GT))]
639 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GE))]
644 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_NE))]
647 def SETE_DX10 : R600_2OP <
649 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_EQ))]
652 def SETGT_DX10 : R600_2OP <
654 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GT))]
657 def SETGE_DX10 : R600_2OP <
659 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GE))]
662 def SETNE_DX10 : R600_2OP <
664 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_NE))]
667 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
668 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
669 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
670 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
671 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
673 def MOV : R600_1OP <0x19, "MOV", []>;
675 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
677 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
678 (outs R600_Reg32:$dst),
684 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
686 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
689 (MOV_IMM_I32 imm:$val)
692 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
695 (MOV_IMM_F32 fpimm:$val)
698 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
699 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
700 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
701 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
703 let hasSideEffects = 1 in {
705 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
707 } // end hasSideEffects
709 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
710 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
711 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
712 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
713 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
714 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
715 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
716 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
717 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
718 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
720 def SETE_INT : R600_2OP <
722 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
725 def SETGT_INT : R600_2OP <
727 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
730 def SETGE_INT : R600_2OP <
732 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
735 def SETNE_INT : R600_2OP <
737 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
740 def SETGT_UINT : R600_2OP <
742 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
745 def SETGE_UINT : R600_2OP <
747 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
750 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
751 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
752 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
753 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
755 def CNDE_INT : R600_3OP <
757 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
760 def CNDGE_INT : R600_3OP <
762 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GE))]
765 def CNDGT_INT : R600_3OP <
767 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GT))]
770 //===----------------------------------------------------------------------===//
771 // Texture instructions
772 //===----------------------------------------------------------------------===//
774 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
776 class R600_TEX <bits<11> inst, string opName> :
777 InstR600 <(outs R600_Reg128:$DST_GPR),
778 (ins R600_Reg128:$SRC_GPR,
779 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,
780 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,
781 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
782 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
783 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
786 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
787 "$SRC_GPR.$srcx$srcy$srcz$srcw "
788 "RID:$RESOURCE_ID SID:$SAMPLER_ID "
789 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
791 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
792 let Inst{31-0} = Word0;
793 let Inst{63-32} = Word1;
795 let TEX_INST = inst{4-0};
801 let FETCH_WHOLE_QUAD = 0;
803 let SAMPLER_INDEX_MODE = 0;
804 let RESOURCE_INDEX_MODE = 0;
809 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
813 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;
814 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;
815 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;
816 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;
817 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;
818 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;
819 def TEX_LD : R600_TEX <0x03, "TEX_LD">;
820 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;
821 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;
822 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;
823 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;
824 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
825 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
826 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
828 defm : TexPattern<0, TEX_SAMPLE>;
829 defm : TexPattern<1, TEX_SAMPLE_C>;
830 defm : TexPattern<2, TEX_SAMPLE_L>;
831 defm : TexPattern<3, TEX_SAMPLE_C_L>;
832 defm : TexPattern<4, TEX_SAMPLE_LB>;
833 defm : TexPattern<5, TEX_SAMPLE_C_LB>;
834 defm : TexPattern<6, TEX_LD, v4i32>;
835 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
836 defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
837 defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
839 //===----------------------------------------------------------------------===//
840 // Helper classes for common instructions
841 //===----------------------------------------------------------------------===//
843 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
848 class MULADD_Common <bits<5> inst> : R600_3OP <
853 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
855 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
858 class CNDE_Common <bits<5> inst> : R600_3OP <
860 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_EQ))]
863 class CNDGT_Common <bits<5> inst> : R600_3OP <
865 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GT))]
868 class CNDGE_Common <bits<5> inst> : R600_3OP <
870 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GE))]
874 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
875 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins
877 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,
878 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,
879 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,
880 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,
881 R600_Pred:$pred_sel_X,
883 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,
884 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,
885 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,
886 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,
887 R600_Pred:$pred_sel_Y,
889 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,
890 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,
891 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,
892 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,
893 R600_Pred:$pred_sel_Z,
895 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,
896 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,
897 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,
898 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,
899 R600_Pred:$pred_sel_W,
900 LITERAL:$literal0, LITERAL:$literal1),
906 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4
907 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,
908 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,
909 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,
910 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;
913 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;
916 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
917 multiclass CUBE_Common <bits<11> inst> {
919 def _pseudo : InstR600 <
920 (outs R600_Reg128:$dst),
921 (ins R600_Reg128:$src),
923 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src))],
929 def _real : R600_2OP <inst, "CUBE", []>;
931 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
933 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
934 inst, "EXP_IEEE", fexp2
937 let Itinerary = TransALU;
940 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
941 inst, "FLT_TO_INT", fp_to_sint
944 let Itinerary = TransALU;
947 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
948 inst, "INT_TO_FLT", sint_to_fp
951 let Itinerary = TransALU;
954 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
955 inst, "FLT_TO_UINT", fp_to_uint
958 let Itinerary = TransALU;
961 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
962 inst, "UINT_TO_FLT", uint_to_fp
965 let Itinerary = TransALU;
968 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
969 inst, "LOG_CLAMPED", []
972 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
973 inst, "LOG_IEEE", flog2
976 let Itinerary = TransALU;
979 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
980 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
981 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
982 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
983 inst, "MULHI_INT", mulhs
986 let Itinerary = TransALU;
988 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
992 let Itinerary = TransALU;
994 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
995 inst, "MULLO_INT", mul
998 let Itinerary = TransALU;
1000 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1002 let Itinerary = TransALU;
1005 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1006 inst, "RECIP_CLAMPED", []
1009 let Itinerary = TransALU;
1012 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1013 inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1016 let Itinerary = TransALU;
1019 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1020 inst, "RECIP_UINT", AMDGPUurecip
1023 let Itinerary = TransALU;
1026 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1027 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1030 let Itinerary = TransALU;
1033 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1034 inst, "RECIPSQRT_IEEE", []
1037 let Itinerary = TransALU;
1040 class SIN_Common <bits<11> inst> : R600_1OP <
1044 let Itinerary = TransALU;
1047 class COS_Common <bits<11> inst> : R600_1OP <
1051 let Itinerary = TransALU;
1054 //===----------------------------------------------------------------------===//
1055 // Helper patterns for complex intrinsics
1056 //===----------------------------------------------------------------------===//
1058 multiclass DIV_Common <InstR600 recip_ieee> {
1060 (int_AMDGPU_div f32:$src0, f32:$src1),
1061 (MUL_IEEE $src0, (recip_ieee $src1))
1065 (fdiv f32:$src0, f32:$src1),
1066 (MUL_IEEE $src0, (recip_ieee $src1))
1070 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
1072 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
1073 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
1076 //===----------------------------------------------------------------------===//
1077 // R600 / R700 Instructions
1078 //===----------------------------------------------------------------------===//
1080 let Predicates = [isR600] in {
1082 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1083 def MULADD_r600 : MULADD_Common<0x10>;
1084 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1085 def CNDE_r600 : CNDE_Common<0x18>;
1086 def CNDGT_r600 : CNDGT_Common<0x19>;
1087 def CNDGE_r600 : CNDGE_Common<0x1A>;
1088 def DOT4_r600 : DOT4_Common<0x50>;
1089 defm CUBE_r600 : CUBE_Common<0x52>;
1090 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1091 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1092 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1093 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1094 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1095 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1096 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1097 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1098 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1099 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1100 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1101 def SIN_r600 : SIN_Common<0x6E>;
1102 def COS_r600 : COS_Common<0x6F>;
1103 def ASHR_r600 : ASHR_Common<0x70>;
1104 def LSHR_r600 : LSHR_Common<0x71>;
1105 def LSHL_r600 : LSHL_Common<0x72>;
1106 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1107 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1108 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1109 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1110 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1112 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1113 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1114 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1116 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1118 def R600_ExportSwz : ExportSwzInst {
1119 let Word1{20-17} = 0; // BURST_COUNT
1120 let Word1{21} = eop;
1121 let Word1{22} = 1; // VALID_PIXEL_MODE
1122 let Word1{30-23} = inst;
1123 let Word1{31} = 1; // BARRIER
1125 defm : ExportPattern<R600_ExportSwz, 39>;
1127 def R600_ExportBuf : ExportBufInst {
1128 let Word1{20-17} = 0; // BURST_COUNT
1129 let Word1{21} = eop;
1130 let Word1{22} = 1; // VALID_PIXEL_MODE
1131 let Word1{30-23} = inst;
1132 let Word1{31} = 1; // BARRIER
1134 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1136 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1137 "TEX $COUNT @$ADDR"> {
1140 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1141 "VTX $COUNT @$ADDR"> {
1144 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1145 "LOOP_START_DX10 @$ADDR"> {
1149 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1153 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1154 "LOOP_BREAK @$ADDR"> {
1158 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1159 "CONTINUE @$ADDR"> {
1163 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1164 "JUMP @$ADDR POP:$POP_COUNT"> {
1167 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1168 "ELSE @$ADDR POP:$POP_COUNT"> {
1171 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1176 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1177 "POP @$ADDR POP:$POP_COUNT"> {
1180 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1184 let END_OF_PROGRAM = 1;
1189 // Helper pattern for normalizing inputs to triginomic instructions for R700+
1191 class COS_PAT <InstR600 trig> : Pat<
1193 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), $src))
1196 class SIN_PAT <InstR600 trig> : Pat<
1198 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), $src))
1201 //===----------------------------------------------------------------------===//
1202 // R700 Only instructions
1203 //===----------------------------------------------------------------------===//
1205 let Predicates = [isR700] in {
1206 def SIN_r700 : SIN_Common<0x6E>;
1207 def COS_r700 : COS_Common<0x6F>;
1209 // R700 normalizes inputs to SIN/COS the same as EG
1210 def : SIN_PAT <SIN_r700>;
1211 def : COS_PAT <COS_r700>;
1214 //===----------------------------------------------------------------------===//
1215 // Evergreen Only instructions
1216 //===----------------------------------------------------------------------===//
1218 let Predicates = [isEG] in {
1220 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1221 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1223 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1224 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1225 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1226 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1227 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1228 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1229 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1230 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1231 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1232 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1233 def SIN_eg : SIN_Common<0x8D>;
1234 def COS_eg : COS_Common<0x8E>;
1236 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
1237 def : SIN_PAT <SIN_eg>;
1238 def : COS_PAT <COS_eg>;
1239 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
1240 } // End Predicates = [isEG]
1242 //===----------------------------------------------------------------------===//
1243 // Evergreen / Cayman Instructions
1244 //===----------------------------------------------------------------------===//
1246 let Predicates = [isEGorCayman] in {
1248 // BFE_UINT - bit_extract, an optimization for mask and shift
1253 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1258 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1259 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1260 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1261 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1262 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1263 [(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
1267 def : BFEPattern <BFE_UINT_eg>;
1269 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>;
1270 defm : BFIPatterns <BFI_INT_eg>;
1272 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
1273 def : ROTRPattern <BIT_ALIGN_INT_eg>;
1275 def MULADD_eg : MULADD_Common<0x14>;
1276 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1277 def ASHR_eg : ASHR_Common<0x15>;
1278 def LSHR_eg : LSHR_Common<0x16>;
1279 def LSHL_eg : LSHL_Common<0x17>;
1280 def CNDE_eg : CNDE_Common<0x19>;
1281 def CNDGT_eg : CNDGT_Common<0x1A>;
1282 def CNDGE_eg : CNDGE_Common<0x1B>;
1283 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1284 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1285 def DOT4_eg : DOT4_Common<0xBE>;
1286 defm CUBE_eg : CUBE_Common<0xC0>;
1288 let hasSideEffects = 1 in {
1289 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1292 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1294 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1298 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1300 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1304 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1306 // TRUNC is used for the FLT_TO_INT instructions to work around a
1307 // perceived problem where the rounding modes are applied differently
1308 // depending on the instruction and the slot they are in.
1310 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1311 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1313 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1314 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1315 // We should look into handling these cases separately.
1316 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
1318 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
1321 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
1323 def EG_ExportSwz : ExportSwzInst {
1324 let Word1{19-16} = 0; // BURST_COUNT
1325 let Word1{20} = 1; // VALID_PIXEL_MODE
1326 let Word1{21} = eop;
1327 let Word1{29-22} = inst;
1328 let Word1{30} = 0; // MARK
1329 let Word1{31} = 1; // BARRIER
1331 defm : ExportPattern<EG_ExportSwz, 83>;
1333 def EG_ExportBuf : ExportBufInst {
1334 let Word1{19-16} = 0; // BURST_COUNT
1335 let Word1{20} = 1; // VALID_PIXEL_MODE
1336 let Word1{21} = eop;
1337 let Word1{29-22} = inst;
1338 let Word1{30} = 0; // MARK
1339 let Word1{31} = 1; // BARRIER
1341 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1343 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1344 "TEX $COUNT @$ADDR"> {
1347 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1348 "VTX $COUNT @$ADDR"> {
1351 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1352 "LOOP_START_DX10 @$ADDR"> {
1356 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1360 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1361 "LOOP_BREAK @$ADDR"> {
1365 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1366 "CONTINUE @$ADDR"> {
1370 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1371 "JUMP @$ADDR POP:$POP_COUNT"> {
1374 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1375 "ELSE @$ADDR POP:$POP_COUNT"> {
1378 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1383 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1384 "POP @$ADDR POP:$POP_COUNT"> {
1387 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1391 let END_OF_PROGRAM = 1;
1394 //===----------------------------------------------------------------------===//
1395 // Memory read/write instructions
1396 //===----------------------------------------------------------------------===//
1397 let usesCustomInserter = 1 in {
1399 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
1401 : EG_CF_RAT <0x57, 0x2, 0, (outs), ins, name, pattern> {
1403 // XXX: Have a separate instruction for non-indexed writes.
1409 let COMP_MASK = comp_mask;
1410 let BURST_COUNT = 0;
1416 } // End usesCustomInserter = 1
1419 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1420 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1421 0x1, "RAT_WRITE_CACHELESS_32_eg $rw_gpr, $index_gpr, $eop",
1422 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1426 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1427 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1428 0xf, "RAT_WRITE_CACHELESS_128 $rw_gpr.XYZW, $index_gpr, $eop",
1429 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
1432 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1433 : InstR600ISA <outs, (ins MEMxi:$ptr), name, pattern>,
1434 VTX_WORD1_GPR, VTX_WORD0 {
1439 let FETCH_WHOLE_QUAD = 0;
1440 let BUFFER_ID = buffer_id;
1442 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1443 // to store vertex addresses in any channel, not just X.
1446 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1447 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1448 // however, based on my testing if USE_CONST_FIELDS is set, then all
1449 // these fields need to be set to 0.
1450 let USE_CONST_FIELDS = 0;
1451 let NUM_FORMAT_ALL = 1;
1452 let FORMAT_COMP_ALL = 0;
1453 let SRF_MODE_ALL = 0;
1455 let Inst{31-0} = Word0;
1456 let Inst{63-32} = Word1;
1457 // LLVM can only encode 64-bit instructions, so these fields are manually
1458 // encoded in R600CodeEmitter
1461 // bits<2> ENDIAN_SWAP = 0;
1462 // bits<1> CONST_BUF_NO_STRIDE = 0;
1463 // bits<1> MEGA_FETCH = 0;
1464 // bits<1> ALT_CONST = 0;
1465 // bits<2> BUFFER_INDEX_MODE = 0;
1469 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1470 // is done in R600CodeEmitter
1472 // Inst{79-64} = OFFSET;
1473 // Inst{81-80} = ENDIAN_SWAP;
1474 // Inst{82} = CONST_BUF_NO_STRIDE;
1475 // Inst{83} = MEGA_FETCH;
1476 // Inst{84} = ALT_CONST;
1477 // Inst{86-85} = BUFFER_INDEX_MODE;
1478 // Inst{95-86} = 0; Reserved
1480 // VTX_WORD3 (Padding)
1482 // Inst{127-96} = 0;
1487 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1488 : VTX_READ_eg <"VTX_READ_8 $dst, $ptr", buffer_id, (outs R600_TReg32_X:$dst),
1491 let MEGA_FETCH_COUNT = 1;
1493 let DST_SEL_Y = 7; // Masked
1494 let DST_SEL_Z = 7; // Masked
1495 let DST_SEL_W = 7; // Masked
1496 let DATA_FORMAT = 1; // FMT_8
1499 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1500 : VTX_READ_eg <"VTX_READ_16 $dst, $ptr", buffer_id, (outs R600_TReg32_X:$dst),
1502 let MEGA_FETCH_COUNT = 2;
1504 let DST_SEL_Y = 7; // Masked
1505 let DST_SEL_Z = 7; // Masked
1506 let DST_SEL_W = 7; // Masked
1507 let DATA_FORMAT = 5; // FMT_16
1511 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1512 : VTX_READ_eg <"VTX_READ_32 $dst, $ptr", buffer_id, (outs R600_TReg32_X:$dst),
1515 let MEGA_FETCH_COUNT = 4;
1517 let DST_SEL_Y = 7; // Masked
1518 let DST_SEL_Z = 7; // Masked
1519 let DST_SEL_W = 7; // Masked
1520 let DATA_FORMAT = 0xD; // COLOR_32
1522 // This is not really necessary, but there were some GPU hangs that appeared
1523 // to be caused by ALU instructions in the next instruction group that wrote
1524 // to the $ptr registers of the VTX_READ.
1526 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1527 // %T2_X<def> = MOV %ZERO
1528 //Adding this constraint prevents this from happening.
1529 let Constraints = "$ptr.ptr = $dst";
1532 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1533 : VTX_READ_eg <"VTX_READ_128 $dst.XYZW, $ptr", buffer_id, (outs R600_Reg128:$dst),
1536 let MEGA_FETCH_COUNT = 16;
1541 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1543 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1544 // that holds its buffer address to avoid potential hangs. We can't use
1545 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1546 // registers are different sizes.
1549 //===----------------------------------------------------------------------===//
1550 // VTX Read from parameter memory space
1551 //===----------------------------------------------------------------------===//
1553 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1554 [(set i32:$dst, (load_param_zexti8 ADDRVTX_READ:$ptr))]
1557 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1558 [(set i32:$dst, (load_param_zexti16 ADDRVTX_READ:$ptr))]
1561 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1562 [(set i32:$dst, (load_param ADDRVTX_READ:$ptr))]
1565 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1566 [(set v4i32:$dst, (load_param ADDRVTX_READ:$ptr))]
1569 //===----------------------------------------------------------------------===//
1570 // VTX Read from global memory space
1571 //===----------------------------------------------------------------------===//
1574 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1575 [(set i32:$dst, (zextloadi8_global ADDRVTX_READ:$ptr))]
1579 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1580 [(set i32:$dst, (global_load ADDRVTX_READ:$ptr))]
1584 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1585 [(set v4i32:$dst, (global_load ADDRVTX_READ:$ptr))]
1588 //===----------------------------------------------------------------------===//
1590 // XXX: We are currently storing all constants in the global address space.
1591 //===----------------------------------------------------------------------===//
1593 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1594 [(set i32:$dst, (constant_load ADDRVTX_READ:$ptr))]
1599 //===----------------------------------------------------------------------===//
1600 // Regist loads and stores - for indirect addressing
1601 //===----------------------------------------------------------------------===//
1603 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1605 let Predicates = [isCayman] in {
1607 let isVector = 1 in {
1609 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1611 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1612 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1613 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1614 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1615 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1616 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1617 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1618 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1619 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1620 def SIN_cm : SIN_Common<0x8D>;
1621 def COS_cm : COS_Common<0x8E>;
1622 } // End isVector = 1
1624 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
1625 def : SIN_PAT <SIN_cm>;
1626 def : COS_PAT <COS_cm>;
1628 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1630 // RECIP_UINT emulation for Cayman
1631 // The multiplication scales from [0,1] to the unsigned integer range
1633 (AMDGPUurecip i32:$src0),
1634 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
1635 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1638 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1644 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
1648 //===----------------------------------------------------------------------===//
1649 // Branch Instructions
1650 //===----------------------------------------------------------------------===//
1653 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1654 "IF_PREDICATE_SET $src", []>;
1656 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
1657 "PREDICATED_BREAK $src", []>;
1659 //===----------------------------------------------------------------------===//
1660 // Pseudo instructions
1661 //===----------------------------------------------------------------------===//
1663 let isPseudo = 1 in {
1665 def PRED_X : InstR600 <
1666 (outs R600_Predicate_Bit:$dst),
1667 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1669 let FlagOperandIdx = 3;
1672 let isTerminator = 1, isBranch = 1 in {
1673 def JUMP_COND : InstR600 <
1675 (ins brtarget:$target, R600_Predicate_Bit:$p),
1676 "JUMP $target ($p)",
1680 def JUMP : InstR600 <
1682 (ins brtarget:$target),
1687 let isPredicable = 1;
1691 } // End isTerminator = 1, isBranch = 1
1693 let usesCustomInserter = 1 in {
1695 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1697 def MASK_WRITE : AMDGPUShaderInst <
1699 (ins R600_Reg32:$src),
1704 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1708 (outs R600_Reg128:$dst),
1709 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1710 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1711 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1712 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1713 imm:$resourceId, imm:$samplerId, imm:$textureTarget))],
1718 def TXD_SHADOW: InstR600 <
1719 (outs R600_Reg128:$dst),
1720 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1721 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1722 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1723 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1724 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))],
1729 } // End isPseudo = 1
1730 } // End usesCustomInserter = 1
1732 def CLAMP_R600 : CLAMP <R600_Reg32>;
1733 def FABS_R600 : FABS<R600_Reg32>;
1734 def FNEG_R600 : FNEG<R600_Reg32>;
1736 //===---------------------------------------------------------------------===//
1737 // Return instruction
1738 //===---------------------------------------------------------------------===//
1739 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
1740 usesCustomInserter = 1 in {
1741 def RETURN : ILFormat<(outs), (ins variable_ops),
1742 "RETURN", [(IL_retflag)]>;
1746 //===----------------------------------------------------------------------===//
1747 // Constant Buffer Addressing Support
1748 //===----------------------------------------------------------------------===//
1750 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1751 def CONST_COPY : Instruction {
1752 let OutOperandList = (outs R600_Reg32:$dst);
1753 let InOperandList = (ins i32imm:$src);
1755 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
1756 let AsmString = "CONST_COPY";
1757 let neverHasSideEffects = 1;
1758 let isAsCheapAsAMove = 1;
1759 let Itinerary = NullALU;
1761 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1763 def TEX_VTX_CONSTBUF :
1764 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
1765 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
1766 VTX_WORD1_GPR, VTX_WORD0 {
1770 let FETCH_WHOLE_QUAD = 0;
1774 let USE_CONST_FIELDS = 0;
1775 let NUM_FORMAT_ALL = 2;
1776 let FORMAT_COMP_ALL = 1;
1777 let SRF_MODE_ALL = 1;
1778 let MEGA_FETCH_COUNT = 16;
1783 let DATA_FORMAT = 35;
1785 let Inst{31-0} = Word0;
1786 let Inst{63-32} = Word1;
1788 // LLVM can only encode 64-bit instructions, so these fields are manually
1789 // encoded in R600CodeEmitter
1792 // bits<2> ENDIAN_SWAP = 0;
1793 // bits<1> CONST_BUF_NO_STRIDE = 0;
1794 // bits<1> MEGA_FETCH = 0;
1795 // bits<1> ALT_CONST = 0;
1796 // bits<2> BUFFER_INDEX_MODE = 0;
1800 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1801 // is done in R600CodeEmitter
1803 // Inst{79-64} = OFFSET;
1804 // Inst{81-80} = ENDIAN_SWAP;
1805 // Inst{82} = CONST_BUF_NO_STRIDE;
1806 // Inst{83} = MEGA_FETCH;
1807 // Inst{84} = ALT_CONST;
1808 // Inst{86-85} = BUFFER_INDEX_MODE;
1809 // Inst{95-86} = 0; Reserved
1811 // VTX_WORD3 (Padding)
1813 // Inst{127-96} = 0;
1818 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
1819 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
1820 VTX_WORD1_GPR, VTX_WORD0 {
1824 let FETCH_WHOLE_QUAD = 0;
1828 let USE_CONST_FIELDS = 1;
1829 let NUM_FORMAT_ALL = 0;
1830 let FORMAT_COMP_ALL = 0;
1831 let SRF_MODE_ALL = 1;
1832 let MEGA_FETCH_COUNT = 16;
1837 let DATA_FORMAT = 0;
1839 let Inst{31-0} = Word0;
1840 let Inst{63-32} = Word1;
1842 // LLVM can only encode 64-bit instructions, so these fields are manually
1843 // encoded in R600CodeEmitter
1846 // bits<2> ENDIAN_SWAP = 0;
1847 // bits<1> CONST_BUF_NO_STRIDE = 0;
1848 // bits<1> MEGA_FETCH = 0;
1849 // bits<1> ALT_CONST = 0;
1850 // bits<2> BUFFER_INDEX_MODE = 0;
1854 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1855 // is done in R600CodeEmitter
1857 // Inst{79-64} = OFFSET;
1858 // Inst{81-80} = ENDIAN_SWAP;
1859 // Inst{82} = CONST_BUF_NO_STRIDE;
1860 // Inst{83} = MEGA_FETCH;
1861 // Inst{84} = ALT_CONST;
1862 // Inst{86-85} = BUFFER_INDEX_MODE;
1863 // Inst{95-86} = 0; Reserved
1865 // VTX_WORD3 (Padding)
1867 // Inst{127-96} = 0;
1873 //===--------------------------------------------------------------------===//
1874 // Instructions support
1875 //===--------------------------------------------------------------------===//
1876 //===---------------------------------------------------------------------===//
1877 // Custom Inserter for Branches and returns, this eventually will be a
1879 //===---------------------------------------------------------------------===//
1880 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
1881 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
1882 "; Pseudo unconditional branch instruction",
1884 defm BRANCH_COND : BranchConditional<IL_brcond>;
1887 //===---------------------------------------------------------------------===//
1888 // Flow and Program control Instructions
1889 //===---------------------------------------------------------------------===//
1890 let isTerminator=1 in {
1891 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
1892 !strconcat("SWITCH", " $src"), []>;
1893 def CASE : ILFormat< (outs), (ins GPRI32:$src),
1894 !strconcat("CASE", " $src"), []>;
1895 def BREAK : ILFormat< (outs), (ins),
1897 def CONTINUE : ILFormat< (outs), (ins),
1899 def DEFAULT : ILFormat< (outs), (ins),
1901 def ELSE : ILFormat< (outs), (ins),
1903 def ENDSWITCH : ILFormat< (outs), (ins),
1905 def ENDMAIN : ILFormat< (outs), (ins),
1907 def END : ILFormat< (outs), (ins),
1909 def ENDFUNC : ILFormat< (outs), (ins),
1911 def ENDIF : ILFormat< (outs), (ins),
1913 def WHILELOOP : ILFormat< (outs), (ins),
1915 def ENDLOOP : ILFormat< (outs), (ins),
1917 def FUNC : ILFormat< (outs), (ins),
1919 def RETDYN : ILFormat< (outs), (ins),
1921 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1922 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
1923 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1924 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
1925 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1926 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
1927 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1928 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
1929 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1930 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
1931 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1932 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
1933 defm IFC : BranchInstr2<"IFC">;
1934 defm BREAKC : BranchInstr2<"BREAKC">;
1935 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
1938 //===----------------------------------------------------------------------===//
1940 //===----------------------------------------------------------------------===//
1942 // CND*_INT Pattterns for f32 True / False values
1944 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
1945 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
1946 (cnd $src0, $src1, $src2)
1949 def : CND_INT_f32 <CNDE_INT, SETEQ>;
1950 def : CND_INT_f32 <CNDGT_INT, SETGT>;
1951 def : CND_INT_f32 <CNDGE_INT, SETGE>;
1953 //CNDGE_INT extra pattern
1955 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_GT),
1956 (CNDGE_INT $src0, $src1, $src2)
1962 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1966 (int_AMDGPU_kill f32:$src0),
1967 (MASK_WRITE (KILLGT (f32 ZERO), $src0))
1972 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LT),
1978 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LE),
1982 // SETGT_DX10 reverse args
1984 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LT),
1985 (SETGT_DX10 $src1, $src0)
1988 // SETGE_DX10 reverse args
1990 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LE),
1991 (SETGE_DX10 $src1, $src0)
1994 // SETGT_INT reverse args
1996 (selectcc i32:$src0, i32:$src1, -1, 0, SETLT),
1997 (SETGT_INT $src1, $src0)
2000 // SETGE_INT reverse args
2002 (selectcc i32:$src0, i32:$src1, -1, 0, SETLE),
2003 (SETGE_INT $src1, $src0)
2006 // SETGT_UINT reverse args
2008 (selectcc i32:$src0, i32:$src1, -1, 0, SETULT),
2009 (SETGT_UINT $src1, $src0)
2012 // SETGE_UINT reverse args
2014 (selectcc i32:$src0, i32:$src1, -1, 0, SETULE),
2015 (SETGE_UINT $src1, $src0)
2018 // The next two patterns are special cases for handling 'true if ordered' and
2019 // 'true if unordered' conditionals. The assumption here is that the behavior of
2020 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2022 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2023 // We assume that SETE returns false when one of the operands is NAN and
2024 // SNE returns true when on of the operands is NAN
2026 //SETE - 'true if ordered'
2028 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETO),
2032 //SETE_DX10 - 'true if ordered'
2034 (selectcc f32:$src0, f32:$src1, -1, 0, SETO),
2035 (SETE_DX10 $src0, $src1)
2038 //SNE - 'true if unordered'
2040 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETUO),
2044 //SETNE_DX10 - 'true if ordered'
2046 (selectcc f32:$src0, f32:$src1, -1, 0, SETUO),
2047 (SETNE_DX10 $src0, $src1)
2050 def : Extract_Element <f32, v4f32, 0, sub0>;
2051 def : Extract_Element <f32, v4f32, 1, sub1>;
2052 def : Extract_Element <f32, v4f32, 2, sub2>;
2053 def : Extract_Element <f32, v4f32, 3, sub3>;
2055 def : Insert_Element <f32, v4f32, 0, sub0>;
2056 def : Insert_Element <f32, v4f32, 1, sub1>;
2057 def : Insert_Element <f32, v4f32, 2, sub2>;
2058 def : Insert_Element <f32, v4f32, 3, sub3>;
2060 def : Extract_Element <i32, v4i32, 0, sub0>;
2061 def : Extract_Element <i32, v4i32, 1, sub1>;
2062 def : Extract_Element <i32, v4i32, 2, sub2>;
2063 def : Extract_Element <i32, v4i32, 3, sub3>;
2065 def : Insert_Element <i32, v4i32, 0, sub0>;
2066 def : Insert_Element <i32, v4i32, 1, sub1>;
2067 def : Insert_Element <i32, v4i32, 2, sub2>;
2068 def : Insert_Element <i32, v4i32, 3, sub3>;
2070 def : Vector4_Build <v4f32, f32>;
2071 def : Vector4_Build <v4i32, i32>;
2073 // bitconvert patterns
2075 def : BitConvert <i32, f32, R600_Reg32>;
2076 def : BitConvert <f32, i32, R600_Reg32>;
2077 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2078 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2080 // DWORDADDR pattern
2081 def : DwordAddrPat <i32, R600_Reg32>;
2083 } // End isR600toCayman Predicate