1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
16 class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
24 bits<2> FlagOperandIdx = 0;
27 bit HasNativeOperands = 0;
29 bits<11> op_code = inst;
31 let Namespace = "AMDGPU";
32 let OutOperandList = outs;
33 let InOperandList = ins;
35 let Pattern = pattern;
38 let TSFlags{4} = Trig;
41 // Vector instructions are instructions that must fill all slots in an
43 let TSFlags{6} = isVector;
44 let TSFlags{8-7} = FlagOperandIdx;
45 let TSFlags{9} = HasNativeOperands;
46 let TSFlags{10} = Op1;
47 let TSFlags{11} = Op2;
50 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
51 AMDGPUInst <outs, ins, asm, pattern> {
54 let Namespace = "AMDGPU";
57 def MEMxi : Operand<iPTR> {
58 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
59 let PrintMethod = "printMemOperand";
62 def MEMrr : Operand<iPTR> {
63 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
66 // Operands for non-registers
68 class InstFlag<string PM = "printOperand", int Default = 0>
69 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
73 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
74 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
75 let PrintMethod = "printSel";
78 def LITERAL : InstFlag<"printLiteral">;
80 def WRITE : InstFlag <"printWrite", 1>;
81 def OMOD : InstFlag <"printOMOD">;
82 def REL : InstFlag <"printRel">;
83 def CLAMP : InstFlag <"printClamp">;
84 def NEG : InstFlag <"printNeg">;
85 def ABS : InstFlag <"printAbs">;
86 def UEM : InstFlag <"printUpdateExecMask">;
87 def UP : InstFlag <"printUpdatePred">;
89 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
90 // Once we start using the packetizer in this backend we should have this
92 def LAST : InstFlag<"printLast", 1>;
94 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
95 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
96 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
97 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
98 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
100 class R600ALU_Word0 {
101 field bits<32> Word0;
109 bits<3> index_mode = 0;
113 bits<9> src0_sel = src0{8-0};
114 bits<2> src0_chan = src0{10-9};
115 bits<9> src1_sel = src1{8-0};
116 bits<2> src1_chan = src1{10-9};
118 let Word0{8-0} = src0_sel;
119 let Word0{9} = src0_rel;
120 let Word0{11-10} = src0_chan;
121 let Word0{12} = src0_neg;
122 let Word0{21-13} = src1_sel;
123 let Word0{22} = src1_rel;
124 let Word0{24-23} = src1_chan;
125 let Word0{25} = src1_neg;
126 let Word0{28-26} = index_mode;
127 let Word0{30-29} = pred_sel;
128 let Word0{31} = last;
131 class R600ALU_Word1 {
132 field bits<32> Word1;
135 bits<3> bank_swizzle = 0;
139 bits<7> dst_sel = dst{6-0};
140 bits<2> dst_chan = dst{10-9};
142 let Word1{20-18} = bank_swizzle;
143 let Word1{27-21} = dst_sel;
144 let Word1{28} = dst_rel;
145 let Word1{30-29} = dst_chan;
146 let Word1{31} = clamp;
149 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
153 bits<1> update_exec_mask;
158 let Word1{0} = src0_abs;
159 let Word1{1} = src1_abs;
160 let Word1{2} = update_exec_mask;
161 let Word1{3} = update_pred;
162 let Word1{4} = write;
163 let Word1{6-5} = omod;
164 let Word1{17-7} = alu_inst;
167 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
173 bits<9> src2_sel = src2{8-0};
174 bits<2> src2_chan = src2{10-9};
176 let Word1{8-0} = src2_sel;
177 let Word1{9} = src2_rel;
178 let Word1{11-10} = src2_chan;
179 let Word1{12} = src2_neg;
180 let Word1{17-13} = alu_inst;
184 field bits<32> Word0;
188 bits<1> FETCH_WHOLE_QUAD;
192 bits<6> MEGA_FETCH_COUNT;
194 let Word0{4-0} = VC_INST;
195 let Word0{6-5} = FETCH_TYPE;
196 let Word0{7} = FETCH_WHOLE_QUAD;
197 let Word0{15-8} = BUFFER_ID;
198 let Word0{22-16} = SRC_GPR;
199 let Word0{23} = SRC_REL;
200 let Word0{25-24} = SRC_SEL_X;
201 let Word0{31-26} = MEGA_FETCH_COUNT;
204 class VTX_WORD1_GPR {
205 field bits<32> Word1;
212 bits<1> USE_CONST_FIELDS;
214 bits<2> NUM_FORMAT_ALL;
215 bits<1> FORMAT_COMP_ALL;
216 bits<1> SRF_MODE_ALL;
218 let Word1{6-0} = DST_GPR;
219 let Word1{7} = DST_REL;
220 let Word1{8} = 0; // Reserved
221 let Word1{11-9} = DST_SEL_X;
222 let Word1{14-12} = DST_SEL_Y;
223 let Word1{17-15} = DST_SEL_Z;
224 let Word1{20-18} = DST_SEL_W;
225 let Word1{21} = USE_CONST_FIELDS;
226 let Word1{27-22} = DATA_FORMAT;
227 let Word1{29-28} = NUM_FORMAT_ALL;
228 let Word1{30} = FORMAT_COMP_ALL;
229 let Word1{31} = SRF_MODE_ALL;
233 XXX: R600 subtarget uses a slightly different encoding than the other
234 subtargets. We currently handle this in R600MCCodeEmitter, but we may
235 want to use these instruction classes in the future.
237 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
242 let Inst{37} = fog_merge;
243 let Inst{39-38} = omod;
244 let Inst{49-40} = alu_inst;
247 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
251 let Inst{38-37} = omod;
252 let Inst{49-39} = alu_inst;
256 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
260 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
262 // Class for instructions with only one source register.
263 // If you add new ins to this instruction, make sure they are listed before
264 // $literal, because the backend currently assumes that the last operand is
265 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
266 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
267 // and R600InstrInfo::getOperandIdx().
268 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
269 InstrItinClass itin = AnyALU> :
271 (outs R600_Reg32:$dst),
272 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
273 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
274 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
276 "$clamp $dst$write$dst_rel$omod, "
277 "$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
278 "$literal $pred_sel$last"),
282 R600ALU_Word1_OP2 <inst> {
288 let update_exec_mask = 0;
290 let HasNativeOperands = 1;
292 let DisableEncoding = "$literal";
294 let Inst{31-0} = Word0;
295 let Inst{63-32} = Word1;
298 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
299 InstrItinClass itin = AnyALU> :
300 R600_1OP <inst, opName,
301 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
304 // If you add our change the operands for R600_2OP instructions, you must
305 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
306 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
307 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
308 InstrItinClass itin = AnyALU> :
310 (outs R600_Reg32:$dst),
311 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
312 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
313 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
314 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
315 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
317 "$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
318 "$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
319 "$src1_neg$src1_abs$src1$src1_sel$src1_abs$src1_rel, "
320 "$literal $pred_sel$last"),
324 R600ALU_Word1_OP2 <inst> {
326 let HasNativeOperands = 1;
328 let DisableEncoding = "$literal";
330 let Inst{31-0} = Word0;
331 let Inst{63-32} = Word1;
334 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
335 InstrItinClass itim = AnyALU> :
336 R600_2OP <inst, opName,
337 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
341 // If you add our change the operands for R600_3OP instructions, you must
342 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
343 // R600InstrInfo::buildDefaultInstruction(), and
344 // R600InstrInfo::getOperandIdx().
345 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
346 InstrItinClass itin = AnyALU> :
348 (outs R600_Reg32:$dst),
349 (ins REL:$dst_rel, CLAMP:$clamp,
350 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
351 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
352 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
353 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
354 !strconcat(opName, "$clamp $dst$dst_rel, "
355 "$src0_neg$src0$src0_sel$src0_rel, "
356 "$src1_neg$src1$src1_sel$src1_rel, "
357 "$src2_neg$src2$src2_sel$src2_rel, "
358 "$literal $pred_sel$last"),
362 R600ALU_Word1_OP3<inst>{
364 let HasNativeOperands = 1;
365 let DisableEncoding = "$literal";
368 let Inst{31-0} = Word0;
369 let Inst{63-32} = Word1;
372 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
373 InstrItinClass itin = VecALU> :
375 (outs R600_Reg32:$dst),
381 class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
382 InstrItinClass itin = AnyALU> :
384 (outs R600_Reg128:$dst),
385 (ins R600_Reg128:$src0, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
386 !strconcat(opName, "$dst, $src0, $resourceId, $samplerId, $textureTarget"),
389 let Inst {10-0} = inst;
392 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
394 def TEX_SHADOW : PatLeaf<
396 [{uint32_t TType = (uint32_t)N->getZExtValue();
397 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
401 def TEX_RECT : PatLeaf<
403 [{uint32_t TType = (uint32_t)N->getZExtValue();
408 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
409 dag ins, string asm, list<dag> pattern> :
410 InstR600ISA <outs, ins, asm, pattern> {
427 // CF_ALLOC_EXPORT_WORD0_RAT
428 let Inst{3-0} = rat_id;
429 let Inst{9-4} = rat_inst;
430 let Inst{10} = 0; // Reserved
431 let Inst{12-11} = RIM;
432 let Inst{14-13} = TYPE;
433 let Inst{21-15} = RW_GPR;
434 let Inst{22} = RW_REL;
435 let Inst{29-23} = INDEX_GPR;
436 let Inst{31-30} = ELEM_SIZE;
438 // CF_ALLOC_EXPORT_WORD1_BUF
439 let Inst{43-32} = ARRAY_SIZE;
440 let Inst{47-44} = COMP_MASK;
441 let Inst{51-48} = BURST_COUNT;
444 let Inst{61-54} = cf_inst;
446 let Inst{63} = BARRIER;
449 class LoadParamFrag <PatFrag load_type> : PatFrag <
450 (ops node:$ptr), (load_type node:$ptr),
451 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
454 def load_param : LoadParamFrag<load>;
455 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
456 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
458 def isR600 : Predicate<"Subtarget.device()"
459 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
460 def isR700 : Predicate<"Subtarget.device()"
461 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
462 "Subtarget.device()->getDeviceFlag()"
463 ">= OCL_DEVICE_RV710">;
464 def isEG : Predicate<
465 "Subtarget.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
466 "Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX && "
467 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
469 def isCayman : Predicate<"Subtarget.device()"
470 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
471 def isEGorCayman : Predicate<"Subtarget.device()"
472 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
473 "|| Subtarget.device()->getGeneration() =="
474 "AMDGPUDeviceInfo::HD6XXX">;
476 def isR600toCayman : Predicate<
477 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
479 //===----------------------------------------------------------------------===//
481 //===----------------------------------------------------------------------===//
483 def INTERP: SDNode<"AMDGPUISD::INTERP",
484 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>
487 def INTERP_P0: SDNode<"AMDGPUISD::INTERP_P0",
488 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisInt<1>]>
491 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
492 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
496 //===----------------------------------------------------------------------===//
497 // Interpolation Instructions
498 //===----------------------------------------------------------------------===//
500 let usesCustomInserter = 1 in {
501 def input_perspective : AMDGPUShaderInst <
502 (outs R600_Reg128:$dst),
503 (ins i32imm:$src0, i32imm:$src1),
504 "input_perspective $src0 $src1 : dst",
505 [(set R600_Reg128:$dst, (INTERP (i32 imm:$src0), (i32 imm:$src1)))]>;
506 } // End usesCustomInserter = 1
508 def input_constant : AMDGPUShaderInst <
509 (outs R600_Reg128:$dst),
511 "input_perspective $src : dst",
512 [(set R600_Reg128:$dst, (INTERP_P0 (i32 imm:$src)))]>;
516 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
517 let bank_swizzle = 5;
520 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
521 let bank_swizzle = 5;
524 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
526 //===----------------------------------------------------------------------===//
527 // Export Instructions
528 //===----------------------------------------------------------------------===//
530 def ExportType : SDTypeProfile<0, 5, [SDTCisFP<0>, SDTCisInt<1>]>;
532 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
533 [SDNPHasChain, SDNPSideEffect]>;
536 field bits<32> Word0;
543 let Word0{12-0} = arraybase;
544 let Word0{14-13} = type;
545 let Word0{21-15} = gpr;
546 let Word0{22} = 0; // RW_REL
547 let Word0{29-23} = 0; // INDEX_GPR
548 let Word0{31-30} = elem_size;
551 class ExportSwzWord1 {
552 field bits<32> Word1;
561 let Word1{2-0} = sw_x;
562 let Word1{5-3} = sw_y;
563 let Word1{8-6} = sw_z;
564 let Word1{11-9} = sw_w;
567 class ExportBufWord1 {
568 field bits<32> Word1;
575 let Word1{11-0} = arraySize;
576 let Word1{15-12} = compMask;
579 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
580 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
582 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sel_x),
583 0, 61, 0, 7, 7, 7, cf_inst, 0)
586 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
588 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sel_x),
589 0, 61, 7, 0, 7, 7, cf_inst, 0)
592 def : Pat<(int_R600_store_pixel_dummy),
594 (v4f32 (IMPLICIT_DEF)), 0, 0, 7, 7, 7, 7, cf_inst, 0)
597 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 0),
598 (i32 imm:$type), (i32 imm:$arraybase), (i32 imm)),
599 (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
600 0, 1, 2, 3, cf_inst, 0)
604 multiclass SteamOutputExportPattern<Instruction ExportInst,
605 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
607 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 1),
608 (i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
609 (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
610 4095, imm:$mask, buf0inst, 0)>;
612 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 2),
613 (i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
614 (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
615 4095, imm:$mask, buf1inst, 0)>;
617 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 3),
618 (i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
619 (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
620 4095, imm:$mask, buf2inst, 0)>;
622 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 4),
623 (i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
624 (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
625 4095, imm:$mask, buf3inst, 0)>;
628 let isTerminator = 1, usesCustomInserter = 1 in {
630 class ExportSwzInst : InstR600ISA<(
632 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
633 i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
635 !strconcat("EXPORT", " $gpr"),
636 []>, ExportWord0, ExportSwzWord1 {
638 let Inst{31-0} = Word0;
639 let Inst{63-32} = Word1;
642 } // End isTerminator = 1, usesCustomInserter = 1
644 class ExportBufInst : InstR600ISA<(
646 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
647 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
648 !strconcat("EXPORT", " $gpr"),
649 []>, ExportWord0, ExportBufWord1 {
651 let Inst{31-0} = Word0;
652 let Inst{63-32} = Word1;
655 let Predicates = [isR600toCayman] in {
657 //===----------------------------------------------------------------------===//
658 // Common Instructions R600, R700, Evergreen, Cayman
659 //===----------------------------------------------------------------------===//
661 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
662 // Non-IEEE MUL: 0 * anything = 0
663 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
664 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
665 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
666 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
668 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
669 // so some of the instruction names don't match the asm string.
670 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
671 def SETE : R600_2OP <
673 [(set R600_Reg32:$dst,
674 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
680 [(set R600_Reg32:$dst,
681 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
687 [(set R600_Reg32:$dst,
688 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
694 [(set R600_Reg32:$dst,
695 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
699 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
700 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
701 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
702 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
703 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
705 def MOV : R600_1OP <0x19, "MOV", []>;
707 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
709 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
710 (outs R600_Reg32:$dst),
716 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
718 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
721 (MOV_IMM_I32 imm:$val)
724 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
727 (MOV_IMM_F32 fpimm:$val)
730 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
731 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
732 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
733 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
735 let hasSideEffects = 1 in {
737 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
739 } // end hasSideEffects
741 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
742 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
743 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
744 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
745 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
746 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
747 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
748 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
749 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
750 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
752 def SETE_INT : R600_2OP <
754 [(set (i32 R600_Reg32:$dst),
755 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
758 def SETGT_INT : R600_2OP <
760 [(set (i32 R600_Reg32:$dst),
761 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
764 def SETGE_INT : R600_2OP <
766 [(set (i32 R600_Reg32:$dst),
767 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
770 def SETNE_INT : R600_2OP <
772 [(set (i32 R600_Reg32:$dst),
773 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
776 def SETGT_UINT : R600_2OP <
778 [(set (i32 R600_Reg32:$dst),
779 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
782 def SETGE_UINT : R600_2OP <
784 [(set (i32 R600_Reg32:$dst),
785 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
788 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
789 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
790 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
791 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
793 def CNDE_INT : R600_3OP <
795 [(set (i32 R600_Reg32:$dst),
796 (selectcc (i32 R600_Reg32:$src0), 0,
797 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
801 def CNDGE_INT : R600_3OP <
803 [(set (i32 R600_Reg32:$dst),
804 (selectcc (i32 R600_Reg32:$src0), 0,
805 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
809 def CNDGT_INT : R600_3OP <
811 [(set (i32 R600_Reg32:$dst),
812 (selectcc (i32 R600_Reg32:$src0), 0,
813 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
817 //===----------------------------------------------------------------------===//
818 // Texture instructions
819 //===----------------------------------------------------------------------===//
821 def TEX_LD : R600_TEX <
823 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
825 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $resourceId, $samplerId, $textureTarget";
826 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget);
829 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
830 0x04, "TEX_GET_TEXTURE_RESINFO",
831 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
834 def TEX_GET_GRADIENTS_H : R600_TEX <
835 0x07, "TEX_GET_GRADIENTS_H",
836 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
839 def TEX_GET_GRADIENTS_V : R600_TEX <
840 0x08, "TEX_GET_GRADIENTS_V",
841 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
844 def TEX_SET_GRADIENTS_H : R600_TEX <
845 0x0B, "TEX_SET_GRADIENTS_H",
849 def TEX_SET_GRADIENTS_V : R600_TEX <
850 0x0C, "TEX_SET_GRADIENTS_V",
854 def TEX_SAMPLE : R600_TEX <
856 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
859 def TEX_SAMPLE_C : R600_TEX <
860 0x18, "TEX_SAMPLE_C",
861 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
864 def TEX_SAMPLE_L : R600_TEX <
865 0x11, "TEX_SAMPLE_L",
866 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
869 def TEX_SAMPLE_C_L : R600_TEX <
870 0x19, "TEX_SAMPLE_C_L",
871 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
874 def TEX_SAMPLE_LB : R600_TEX <
875 0x12, "TEX_SAMPLE_LB",
876 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0,imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
879 def TEX_SAMPLE_C_LB : R600_TEX <
880 0x1A, "TEX_SAMPLE_C_LB",
881 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
884 def TEX_SAMPLE_G : R600_TEX <
885 0x14, "TEX_SAMPLE_G",
889 def TEX_SAMPLE_C_G : R600_TEX <
890 0x1C, "TEX_SAMPLE_C_G",
894 //===----------------------------------------------------------------------===//
895 // Helper classes for common instructions
896 //===----------------------------------------------------------------------===//
898 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
903 class MULADD_Common <bits<5> inst> : R600_3OP <
905 [(set (f32 R600_Reg32:$dst),
906 (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
909 class CNDE_Common <bits<5> inst> : R600_3OP <
911 [(set R600_Reg32:$dst,
912 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
913 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
917 class CNDGT_Common <bits<5> inst> : R600_3OP <
919 [(set R600_Reg32:$dst,
920 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
921 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
925 class CNDGE_Common <bits<5> inst> : R600_3OP <
927 [(set R600_Reg32:$dst,
928 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
929 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
933 multiclass DOT4_Common <bits<11> inst> {
935 def _pseudo : R600_REDUCTION <inst,
936 (ins R600_Reg128:$src0, R600_Reg128:$src1),
937 "DOT4 $dst $src0, $src1",
938 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
941 def _real : R600_2OP <inst, "DOT4", []>;
944 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
945 multiclass CUBE_Common <bits<11> inst> {
947 def _pseudo : InstR600 <
949 (outs R600_Reg128:$dst),
950 (ins R600_Reg128:$src),
952 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
958 def _real : R600_2OP <inst, "CUBE", []>;
960 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
962 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
963 inst, "EXP_IEEE", fexp2
966 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
967 inst, "FLT_TO_INT", fp_to_sint
970 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
971 inst, "INT_TO_FLT", sint_to_fp
974 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
975 inst, "FLT_TO_UINT", fp_to_uint
978 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
979 inst, "UINT_TO_FLT", uint_to_fp
982 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
983 inst, "LOG_CLAMPED", []
986 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
987 inst, "LOG_IEEE", flog2
990 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
991 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
992 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
993 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
994 inst, "MULHI_INT", mulhs
996 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
999 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1000 inst, "MULLO_INT", mul
1002 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []>;
1004 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1005 inst, "RECIP_CLAMPED", []
1008 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1009 inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))]
1012 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1013 inst, "RECIP_UINT", AMDGPUurecip
1016 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1017 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1020 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1021 inst, "RECIPSQRT_IEEE", []
1024 class SIN_Common <bits<11> inst> : R600_1OP <
1029 class COS_Common <bits<11> inst> : R600_1OP <
1034 //===----------------------------------------------------------------------===//
1035 // Helper patterns for complex intrinsics
1036 //===----------------------------------------------------------------------===//
1038 multiclass DIV_Common <InstR600 recip_ieee> {
1040 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
1041 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1045 (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
1046 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1050 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
1051 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
1052 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
1055 //===----------------------------------------------------------------------===//
1056 // R600 / R700 Instructions
1057 //===----------------------------------------------------------------------===//
1059 let Predicates = [isR600] in {
1061 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1062 def MULADD_r600 : MULADD_Common<0x10>;
1063 def CNDE_r600 : CNDE_Common<0x18>;
1064 def CNDGT_r600 : CNDGT_Common<0x19>;
1065 def CNDGE_r600 : CNDGE_Common<0x1A>;
1066 defm DOT4_r600 : DOT4_Common<0x50>;
1067 defm CUBE_r600 : CUBE_Common<0x52>;
1068 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1069 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1070 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1071 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1072 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1073 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1074 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1075 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1076 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1077 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1078 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1079 def SIN_r600 : SIN_Common<0x6E>;
1080 def COS_r600 : COS_Common<0x6F>;
1081 def ASHR_r600 : ASHR_Common<0x70>;
1082 def LSHR_r600 : LSHR_Common<0x71>;
1083 def LSHL_r600 : LSHL_Common<0x72>;
1084 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1085 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1086 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1087 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1088 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1090 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1091 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1093 def : Pat<(fsqrt R600_Reg32:$src),
1094 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_r600 R600_Reg32:$src))>;
1096 def R600_ExportSwz : ExportSwzInst {
1097 let Word1{20-17} = 1; // BURST_COUNT
1098 let Word1{21} = eop;
1099 let Word1{22} = 1; // VALID_PIXEL_MODE
1100 let Word1{30-23} = inst;
1101 let Word1{31} = 1; // BARRIER
1103 defm : ExportPattern<R600_ExportSwz, 39>;
1105 def R600_ExportBuf : ExportBufInst {
1106 let Word1{20-17} = 1; // BURST_COUNT
1107 let Word1{21} = eop;
1108 let Word1{22} = 1; // VALID_PIXEL_MODE
1109 let Word1{30-23} = inst;
1110 let Word1{31} = 1; // BARRIER
1112 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1115 // Helper pattern for normalizing inputs to triginomic instructions for R700+
1117 class COS_PAT <InstR600 trig> : Pat<
1118 (fcos R600_Reg32:$src),
1119 (trig (MUL (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1122 class SIN_PAT <InstR600 trig> : Pat<
1123 (fsin R600_Reg32:$src),
1124 (trig (MUL (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1127 //===----------------------------------------------------------------------===//
1128 // R700 Only instructions
1129 //===----------------------------------------------------------------------===//
1131 let Predicates = [isR700] in {
1132 def SIN_r700 : SIN_Common<0x6E>;
1133 def COS_r700 : COS_Common<0x6F>;
1135 // R700 normalizes inputs to SIN/COS the same as EG
1136 def : SIN_PAT <SIN_r700>;
1137 def : COS_PAT <COS_r700>;
1140 //===----------------------------------------------------------------------===//
1141 // Evergreen Only instructions
1142 //===----------------------------------------------------------------------===//
1144 let Predicates = [isEG] in {
1146 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1147 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1149 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1150 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1151 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1152 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1153 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1154 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1155 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1156 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1157 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1158 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1159 def SIN_eg : SIN_Common<0x8D>;
1160 def COS_eg : COS_Common<0x8E>;
1162 def : SIN_PAT <SIN_eg>;
1163 def : COS_PAT <COS_eg>;
1164 def : Pat<(fsqrt R600_Reg32:$src),
1165 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_eg R600_Reg32:$src))>;
1166 } // End Predicates = [isEG]
1168 //===----------------------------------------------------------------------===//
1169 // Evergreen / Cayman Instructions
1170 //===----------------------------------------------------------------------===//
1172 let Predicates = [isEGorCayman] in {
1174 // BFE_UINT - bit_extract, an optimization for mask and shift
1179 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1184 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1185 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1186 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1187 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1188 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1189 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
1191 R600_Reg32:$src2))],
1195 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
1196 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
1197 R600_Reg32:$src2))],
1201 def MULADD_eg : MULADD_Common<0x14>;
1202 def ASHR_eg : ASHR_Common<0x15>;
1203 def LSHR_eg : LSHR_Common<0x16>;
1204 def LSHL_eg : LSHL_Common<0x17>;
1205 def CNDE_eg : CNDE_Common<0x19>;
1206 def CNDGT_eg : CNDGT_Common<0x1A>;
1207 def CNDGE_eg : CNDGE_Common<0x1B>;
1208 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1209 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1210 defm DOT4_eg : DOT4_Common<0xBE>;
1211 defm CUBE_eg : CUBE_Common<0xC0>;
1213 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1215 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1219 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1221 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1225 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1227 // TRUNC is used for the FLT_TO_INT instructions to work around a
1228 // perceived problem where the rounding modes are applied differently
1229 // depending on the instruction and the slot they are in.
1231 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1232 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1234 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1235 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1236 // We should look into handling these cases separately.
1237 def : Pat<(fp_to_sint R600_Reg32:$src0),
1238 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src0))>;
1240 def : Pat<(fp_to_uint R600_Reg32:$src0),
1241 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src0))>;
1243 def EG_ExportSwz : ExportSwzInst {
1244 let Word1{19-16} = 1; // BURST_COUNT
1245 let Word1{20} = 1; // VALID_PIXEL_MODE
1246 let Word1{21} = eop;
1247 let Word1{29-22} = inst;
1248 let Word1{30} = 0; // MARK
1249 let Word1{31} = 1; // BARRIER
1251 defm : ExportPattern<EG_ExportSwz, 83>;
1253 def EG_ExportBuf : ExportBufInst {
1254 let Word1{19-16} = 1; // BURST_COUNT
1255 let Word1{20} = 1; // VALID_PIXEL_MODE
1256 let Word1{21} = eop;
1257 let Word1{29-22} = inst;
1258 let Word1{30} = 0; // MARK
1259 let Word1{31} = 1; // BARRIER
1261 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1263 //===----------------------------------------------------------------------===//
1264 // Memory read/write instructions
1265 //===----------------------------------------------------------------------===//
1266 let usesCustomInserter = 1 in {
1268 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
1270 : EG_CF_RAT <0x57, 0x2, 0, (outs), ins,
1271 !strconcat(name, " $rw_gpr, $index_gpr, $eop"), pattern> {
1273 // XXX: Have a separate instruction for non-indexed writes.
1279 let COMP_MASK = comp_mask;
1280 let BURST_COUNT = 0;
1286 } // End usesCustomInserter = 1
1289 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1290 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1291 0x1, "RAT_WRITE_CACHELESS_32_eg",
1292 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]
1296 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1297 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1298 0xf, "RAT_WRITE_CACHELESS_128",
1299 [(global_store (v4i32 R600_Reg128:$rw_gpr), R600_TReg32_X:$index_gpr)]
1302 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1303 : InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
1304 VTX_WORD1_GPR, VTX_WORD0 {
1309 let FETCH_WHOLE_QUAD = 0;
1310 let BUFFER_ID = buffer_id;
1312 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1313 // to store vertex addresses in any channel, not just X.
1316 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1317 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1318 // however, based on my testing if USE_CONST_FIELDS is set, then all
1319 // these fields need to be set to 0.
1320 let USE_CONST_FIELDS = 0;
1321 let NUM_FORMAT_ALL = 1;
1322 let FORMAT_COMP_ALL = 0;
1323 let SRF_MODE_ALL = 0;
1325 let Inst{31-0} = Word0;
1326 let Inst{63-32} = Word1;
1327 // LLVM can only encode 64-bit instructions, so these fields are manually
1328 // encoded in R600CodeEmitter
1331 // bits<2> ENDIAN_SWAP = 0;
1332 // bits<1> CONST_BUF_NO_STRIDE = 0;
1333 // bits<1> MEGA_FETCH = 0;
1334 // bits<1> ALT_CONST = 0;
1335 // bits<2> BUFFER_INDEX_MODE = 0;
1339 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1340 // is done in R600CodeEmitter
1342 // Inst{79-64} = OFFSET;
1343 // Inst{81-80} = ENDIAN_SWAP;
1344 // Inst{82} = CONST_BUF_NO_STRIDE;
1345 // Inst{83} = MEGA_FETCH;
1346 // Inst{84} = ALT_CONST;
1347 // Inst{86-85} = BUFFER_INDEX_MODE;
1348 // Inst{95-86} = 0; Reserved
1350 // VTX_WORD3 (Padding)
1352 // Inst{127-96} = 0;
1355 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1356 : VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
1359 let MEGA_FETCH_COUNT = 1;
1361 let DST_SEL_Y = 7; // Masked
1362 let DST_SEL_Z = 7; // Masked
1363 let DST_SEL_W = 7; // Masked
1364 let DATA_FORMAT = 1; // FMT_8
1367 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1368 : VTX_READ_eg <"VTX_READ_16", buffer_id, (outs R600_TReg32_X:$dst),
1370 let MEGA_FETCH_COUNT = 2;
1372 let DST_SEL_Y = 7; // Masked
1373 let DST_SEL_Z = 7; // Masked
1374 let DST_SEL_W = 7; // Masked
1375 let DATA_FORMAT = 5; // FMT_16
1379 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1380 : VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
1383 let MEGA_FETCH_COUNT = 4;
1385 let DST_SEL_Y = 7; // Masked
1386 let DST_SEL_Z = 7; // Masked
1387 let DST_SEL_W = 7; // Masked
1388 let DATA_FORMAT = 0xD; // COLOR_32
1390 // This is not really necessary, but there were some GPU hangs that appeared
1391 // to be caused by ALU instructions in the next instruction group that wrote
1392 // to the $ptr registers of the VTX_READ.
1394 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1395 // %T2_X<def> = MOV %ZERO
1396 //Adding this constraint prevents this from happening.
1397 let Constraints = "$ptr.ptr = $dst";
1400 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1401 : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
1404 let MEGA_FETCH_COUNT = 16;
1409 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1411 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1412 // that holds its buffer address to avoid potential hangs. We can't use
1413 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1414 // registers are different sizes.
1417 //===----------------------------------------------------------------------===//
1418 // VTX Read from parameter memory space
1419 //===----------------------------------------------------------------------===//
1421 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1422 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti8 ADDRVTX_READ:$ptr))]
1425 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1426 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti16 ADDRVTX_READ:$ptr))]
1429 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1430 [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1433 //===----------------------------------------------------------------------===//
1434 // VTX Read from global memory space
1435 //===----------------------------------------------------------------------===//
1438 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1439 [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
1443 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1444 [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1448 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1449 [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1452 //===----------------------------------------------------------------------===//
1454 // XXX: We are currently storing all constants in the global address space.
1455 //===----------------------------------------------------------------------===//
1457 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1458 [(set (i32 R600_TReg32_X:$dst), (constant_load ADDRVTX_READ:$ptr))]
1463 let Predicates = [isCayman] in {
1465 let isVector = 1 in {
1467 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1469 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1470 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1471 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1472 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1473 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1474 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1475 def LOG_IEEE_ : LOG_IEEE_Common<0x83>;
1476 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1477 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1478 def SIN_cm : SIN_Common<0x8D>;
1479 def COS_cm : COS_Common<0x8E>;
1480 } // End isVector = 1
1482 def : SIN_PAT <SIN_cm>;
1483 def : COS_PAT <COS_cm>;
1485 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1487 // RECIP_UINT emulation for Cayman
1489 (AMDGPUurecip R600_Reg32:$src0),
1490 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1491 (MOV_IMM_I32 0x4f800000)))
1495 def : Pat<(fsqrt R600_Reg32:$src),
1496 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm R600_Reg32:$src))>;
1500 //===----------------------------------------------------------------------===//
1501 // Branch Instructions
1502 //===----------------------------------------------------------------------===//
1505 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1506 "IF_PREDICATE_SET $src", []>;
1508 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
1509 "PREDICATED_BREAK $src", []>;
1511 //===----------------------------------------------------------------------===//
1512 // Pseudo instructions
1513 //===----------------------------------------------------------------------===//
1515 let isPseudo = 1 in {
1517 def PRED_X : InstR600 <
1518 0, (outs R600_Predicate_Bit:$dst),
1519 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1521 let FlagOperandIdx = 3;
1524 let isTerminator = 1, isBranch = 1, isBarrier = 1 in {
1526 def JUMP : InstR600 <0x10,
1528 (ins brtarget:$target, R600_Pred:$p),
1529 "JUMP $target ($p)",
1533 } // End isTerminator = 1, isBranch = 1, isBarrier = 1
1535 let usesCustomInserter = 1 in {
1537 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1539 def MASK_WRITE : AMDGPUShaderInst <
1541 (ins R600_Reg32:$src),
1546 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1549 def RESERVE_REG : AMDGPUShaderInst <
1553 [(int_AMDGPU_reserve_reg imm:$src)]
1555 def TXD: AMDGPUShaderInst <
1556 (outs R600_Reg128:$dst),
1557 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1558 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1559 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
1562 def TXD_SHADOW: AMDGPUShaderInst <
1563 (outs R600_Reg128:$dst),
1564 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1565 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1566 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
1569 } // End isPseudo = 1
1570 } // End usesCustomInserter = 1
1572 def CLAMP_R600 : CLAMP <R600_Reg32>;
1573 def FABS_R600 : FABS<R600_Reg32>;
1574 def FNEG_R600 : FNEG<R600_Reg32>;
1576 //===---------------------------------------------------------------------===//
1577 // Return instruction
1578 //===---------------------------------------------------------------------===//
1579 let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
1580 def RETURN : ILFormat<(outs), (ins variable_ops),
1581 "RETURN", [(IL_retflag)]>;
1585 //===----------------------------------------------------------------------===//
1586 // Constant Buffer Addressing Support
1587 //===----------------------------------------------------------------------===//
1589 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1590 def CONST_COPY : Instruction {
1591 let OutOperandList = (outs R600_Reg32:$dst);
1592 let InOperandList = (ins i32imm:$src);
1593 let Pattern = [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
1594 let AsmString = "CONST_COPY";
1595 let neverHasSideEffects = 1;
1596 let isAsCheapAsAMove = 1;
1597 let Itinerary = NullALU;
1599 } // end isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1601 def TEX_VTX_CONSTBUF :
1602 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr), "VTX_READ_eg $dst, $ptr",
1603 [(set R600_Reg128:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr))]>,
1604 VTX_WORD1_GPR, VTX_WORD0 {
1608 let FETCH_WHOLE_QUAD = 0;
1613 let USE_CONST_FIELDS = 0;
1614 let NUM_FORMAT_ALL = 2;
1615 let FORMAT_COMP_ALL = 1;
1616 let SRF_MODE_ALL = 1;
1617 let MEGA_FETCH_COUNT = 16;
1622 let DATA_FORMAT = 35;
1624 let Inst{31-0} = Word0;
1625 let Inst{63-32} = Word1;
1627 // LLVM can only encode 64-bit instructions, so these fields are manually
1628 // encoded in R600CodeEmitter
1631 // bits<2> ENDIAN_SWAP = 0;
1632 // bits<1> CONST_BUF_NO_STRIDE = 0;
1633 // bits<1> MEGA_FETCH = 0;
1634 // bits<1> ALT_CONST = 0;
1635 // bits<2> BUFFER_INDEX_MODE = 0;
1639 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1640 // is done in R600CodeEmitter
1642 // Inst{79-64} = OFFSET;
1643 // Inst{81-80} = ENDIAN_SWAP;
1644 // Inst{82} = CONST_BUF_NO_STRIDE;
1645 // Inst{83} = MEGA_FETCH;
1646 // Inst{84} = ALT_CONST;
1647 // Inst{86-85} = BUFFER_INDEX_MODE;
1648 // Inst{95-86} = 0; Reserved
1650 // VTX_WORD3 (Padding)
1652 // Inst{127-96} = 0;
1656 //===--------------------------------------------------------------------===//
1657 // Instructions support
1658 //===--------------------------------------------------------------------===//
1659 //===---------------------------------------------------------------------===//
1660 // Custom Inserter for Branches and returns, this eventually will be a
1662 //===---------------------------------------------------------------------===//
1663 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
1664 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
1665 "; Pseudo unconditional branch instruction",
1667 defm BRANCH_COND : BranchConditional<IL_brcond>;
1670 //===---------------------------------------------------------------------===//
1671 // Flow and Program control Instructions
1672 //===---------------------------------------------------------------------===//
1673 let isTerminator=1 in {
1674 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
1675 !strconcat("SWITCH", " $src"), []>;
1676 def CASE : ILFormat< (outs), (ins GPRI32:$src),
1677 !strconcat("CASE", " $src"), []>;
1678 def BREAK : ILFormat< (outs), (ins),
1680 def CONTINUE : ILFormat< (outs), (ins),
1682 def DEFAULT : ILFormat< (outs), (ins),
1684 def ELSE : ILFormat< (outs), (ins),
1686 def ENDSWITCH : ILFormat< (outs), (ins),
1688 def ENDMAIN : ILFormat< (outs), (ins),
1690 def END : ILFormat< (outs), (ins),
1692 def ENDFUNC : ILFormat< (outs), (ins),
1694 def ENDIF : ILFormat< (outs), (ins),
1696 def WHILELOOP : ILFormat< (outs), (ins),
1698 def ENDLOOP : ILFormat< (outs), (ins),
1700 def FUNC : ILFormat< (outs), (ins),
1702 def RETDYN : ILFormat< (outs), (ins),
1704 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1705 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
1706 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1707 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
1708 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1709 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
1710 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1711 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
1712 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1713 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
1714 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1715 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
1716 defm IFC : BranchInstr2<"IFC">;
1717 defm BREAKC : BranchInstr2<"BREAKC">;
1718 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
1721 //===----------------------------------------------------------------------===//
1723 //===----------------------------------------------------------------------===//
1725 //CNDGE_INT extra pattern
1727 (selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),
1728 (i32 R600_Reg32:$src2), COND_GT),
1729 (CNDGE_INT R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
1735 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1739 (int_AMDGPU_kill R600_Reg32:$src0),
1740 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
1745 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1746 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1751 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1752 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1755 // SETGT_INT reverse args
1757 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1758 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1761 // SETGE_INT reverse args
1763 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1764 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1767 // SETGT_UINT reverse args
1769 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1770 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1773 // SETGE_UINT reverse args
1775 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1776 (SETGE_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1779 // The next two patterns are special cases for handling 'true if ordered' and
1780 // 'true if unordered' conditionals. The assumption here is that the behavior of
1781 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1783 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1784 // We assume that SETE returns false when one of the operands is NAN and
1785 // SNE returns true when on of the operands is NAN
1787 //SETE - 'true if ordered'
1789 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1790 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1793 //SNE - 'true if unordered'
1795 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1796 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1799 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1800 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1801 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1802 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1804 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 0, sel_x>;
1805 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 1, sel_y>;
1806 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 2, sel_z>;
1807 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 3, sel_w>;
1809 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1810 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1811 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1812 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1814 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 0, sel_x>;
1815 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 1, sel_y>;
1816 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 2, sel_z>;
1817 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sel_w>;
1819 def : Vector_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
1820 def : Vector_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
1822 // bitconvert patterns
1824 def : BitConvert <i32, f32, R600_Reg32>;
1825 def : BitConvert <f32, i32, R600_Reg32>;
1826 def : BitConvert <v4f32, v4i32, R600_Reg128>;
1827 def : BitConvert <v4i32, v4f32, R600_Reg128>;
1829 // DWORDADDR pattern
1830 def : DwordAddrPat <i32, R600_Reg32>;
1832 } // End isR600toCayman Predicate