1 //===-- R600MachineScheduler.cpp - R600 Scheduler Interface -*- C++ -*-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Machine Scheduler interface
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "R600MachineScheduler.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Pass.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/Support/raw_ostream.h"
26 void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
27 assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness");
28 DAG = static_cast<ScheduleDAGMILive*>(dag);
29 TII = static_cast<const R600InstrInfo*>(DAG->TII);
30 TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
31 VLIW5 = !DAG->MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA();
33 CurInstKind = IDOther;
35 OccupedSlotsMask = 31;
36 InstKindLimit[IDAlu] = TII->getMaxAlusPerClause();
37 InstKindLimit[IDOther] = 32;
39 const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
40 InstKindLimit[IDFetch] = ST.getTexVTXClauseSize();
45 void R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc,
46 std::vector<SUnit *> &QDst)
48 QDst.insert(QDst.end(), QSrc.begin(), QSrc.end());
53 unsigned getWFCountLimitedByGPR(unsigned GPRCount) {
54 assert (GPRCount && "GPRCount cannot be 0");
55 return 248 / GPRCount;
58 SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
60 NextInstKind = IDOther;
64 // check if we might want to switch current clause type
65 bool AllowSwitchToAlu = (CurEmitted >= InstKindLimit[CurInstKind]) ||
66 (Available[CurInstKind].empty());
67 bool AllowSwitchFromAlu = (CurEmitted >= InstKindLimit[CurInstKind]) &&
68 (!Available[IDFetch].empty() || !Available[IDOther].empty());
70 if (CurInstKind == IDAlu && !Available[IDFetch].empty()) {
71 // We use the heuristic provided by AMD Accelerated Parallel Processing
72 // OpenCL Programming Guide :
73 // The approx. number of WF that allows TEX inst to hide ALU inst is :
74 // 500 (cycles for TEX) / (AluFetchRatio * 8 (cycles for ALU))
75 float ALUFetchRationEstimate =
76 (AluInstCount + AvailablesAluCount() + Pending[IDAlu].size()) /
77 (FetchInstCount + Available[IDFetch].size());
78 unsigned NeededWF = 62.5f / ALUFetchRationEstimate;
79 DEBUG( dbgs() << NeededWF << " approx. Wavefronts Required\n" );
80 // We assume the local GPR requirements to be "dominated" by the requirement
81 // of the TEX clause (which consumes 128 bits regs) ; ALU inst before and
82 // after TEX are indeed likely to consume or generate values from/for the
84 // Available[IDFetch].size() * 2 : GPRs required in the Fetch clause
85 // We assume that fetch instructions are either TnXYZW = TEX TnXYZW (need
86 // one GPR) or TmXYZW = TnXYZW (need 2 GPR).
87 // (TODO : use RegisterPressure)
88 // If we are going too use too many GPR, we flush Fetch instruction to lower
89 // register pressure on 128 bits regs.
90 unsigned NearRegisterRequirement = 2 * Available[IDFetch].size();
91 if (NeededWF > getWFCountLimitedByGPR(NearRegisterRequirement))
92 AllowSwitchFromAlu = true;
95 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
96 (!AllowSwitchFromAlu && CurInstKind == IDAlu))) {
99 if (!SU && !PhysicalRegCopy.empty()) {
100 SU = PhysicalRegCopy.front();
101 PhysicalRegCopy.erase(PhysicalRegCopy.begin());
104 if (CurEmitted >= InstKindLimit[IDAlu])
106 NextInstKind = IDAlu;
112 SU = pickOther(IDFetch);
114 NextInstKind = IDFetch;
119 SU = pickOther(IDOther);
121 NextInstKind = IDOther;
126 dbgs() << " ** Pick node **\n";
129 dbgs() << "NO NODE \n";
130 for (unsigned i = 0; i < DAG->SUnits.size(); i++) {
131 const SUnit &S = DAG->SUnits[i];
141 void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
142 if (NextInstKind != CurInstKind) {
143 DEBUG(dbgs() << "Instruction Type Switch\n");
144 if (NextInstKind != IDAlu)
145 OccupedSlotsMask |= 31;
147 CurInstKind = NextInstKind;
150 if (CurInstKind == IDAlu) {
152 switch (getAluKind(SU)) {
160 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(),
161 E = SU->getInstr()->operands_end(); It != E; ++It) {
162 MachineOperand &MO = *It;
163 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
173 DEBUG(dbgs() << CurEmitted << " Instructions Emitted in this clause\n");
175 if (CurInstKind != IDFetch) {
176 MoveUnits(Pending[IDFetch], Available[IDFetch]);
182 isPhysicalRegCopy(MachineInstr *MI) {
183 if (MI->getOpcode() != AMDGPU::COPY)
186 return !TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg());
189 void R600SchedStrategy::releaseTopNode(SUnit *SU) {
190 DEBUG(dbgs() << "Top Releasing ";SU->dump(DAG););
193 void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
194 DEBUG(dbgs() << "Bottom Releasing ";SU->dump(DAG););
195 if (isPhysicalRegCopy(SU->getInstr())) {
196 PhysicalRegCopy.push_back(SU);
200 int IK = getInstKind(SU);
202 // There is no export clause, we can schedule one as soon as its ready
204 Available[IDOther].push_back(SU);
206 Pending[IK].push_back(SU);
210 bool R600SchedStrategy::regBelongsToClass(unsigned Reg,
211 const TargetRegisterClass *RC) const {
212 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
213 return RC->contains(Reg);
215 return MRI->getRegClass(Reg) == RC;
219 R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
220 MachineInstr *MI = SU->getInstr();
222 if (TII->isTransOnly(MI))
225 switch (MI->getOpcode()) {
228 case AMDGPU::INTERP_PAIR_XY:
229 case AMDGPU::INTERP_PAIR_ZW:
230 case AMDGPU::INTERP_VEC_LOAD:
234 if (MI->getOperand(1).isUndef()) {
235 // MI will become a KILL, don't considers it in scheduling
242 // Does the instruction take a whole IG ?
243 // XXX: Is it possible to add a helper function in R600InstrInfo that can
244 // be used here and in R600PacketizerList::isSoloInstruction() ?
245 if(TII->isVector(*MI) ||
246 TII->isCubeOp(MI->getOpcode()) ||
247 TII->isReductionOp(MI->getOpcode()) ||
248 MI->getOpcode() == AMDGPU::GROUP_BARRIER) {
252 if (TII->isLDSInstr(MI->getOpcode())) {
256 // Is the result already assigned to a channel ?
257 unsigned DestSubReg = MI->getOperand(0).getSubReg();
258 switch (DestSubReg) {
271 // Is the result already member of a X/Y/Z/W class ?
272 unsigned DestReg = MI->getOperand(0).getReg();
273 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
274 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
276 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
278 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
280 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
282 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
285 // LDS src registers cannot be used in the Trans slot.
286 if (TII->readsLDSSrcReg(MI))
293 int R600SchedStrategy::getInstKind(SUnit* SU) {
294 int Opcode = SU->getInstr()->getOpcode();
296 if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
299 if (TII->isALUInstr(Opcode)) {
306 case AMDGPU::CONST_COPY:
307 case AMDGPU::INTERP_PAIR_XY:
308 case AMDGPU::INTERP_PAIR_ZW:
309 case AMDGPU::INTERP_VEC_LOAD:
317 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) {
320 for (std::vector<SUnit *>::reverse_iterator It = Q.rbegin(), E = Q.rend();
323 InstructionsGroupCandidate.push_back(SU->getInstr());
324 if (TII->fitsConstReadLimitations(InstructionsGroupCandidate)
325 && (!AnyALU || !TII->isVectorOnly(SU->getInstr()))
327 InstructionsGroupCandidate.pop_back();
328 Q.erase((It + 1).base());
331 InstructionsGroupCandidate.pop_back();
337 void R600SchedStrategy::LoadAlu() {
338 std::vector<SUnit *> &QSrc = Pending[IDAlu];
339 for (unsigned i = 0, e = QSrc.size(); i < e; ++i) {
340 AluKind AK = getAluKind(QSrc[i]);
341 AvailableAlus[AK].push_back(QSrc[i]);
346 void R600SchedStrategy::PrepareNextSlot() {
347 DEBUG(dbgs() << "New Slot\n");
348 assert (OccupedSlotsMask && "Slot wasn't filled");
349 OccupedSlotsMask = 0;
350 // if (HwGen == AMDGPUSubtarget::NORTHERN_ISLANDS)
351 // OccupedSlotsMask |= 16;
352 InstructionsGroupCandidate.clear();
356 void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) {
357 int DstIndex = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
358 if (DstIndex == -1) {
361 unsigned DestReg = MI->getOperand(DstIndex).getReg();
362 // PressureRegister crashes if an operand is def and used in the same inst
363 // and we try to constraint its regclass
364 for (MachineInstr::mop_iterator It = MI->operands_begin(),
365 E = MI->operands_end(); It != E; ++It) {
366 MachineOperand &MO = *It;
367 if (MO.isReg() && !MO.isDef() &&
368 MO.getReg() == DestReg)
371 // Constrains the regclass of DestReg to assign it to Slot
374 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass);
377 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass);
380 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass);
383 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);
388 SUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot, bool AnyAlu) {
389 static const AluKind IndexToID[] = {AluT_X, AluT_Y, AluT_Z, AluT_W};
390 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu);
393 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu);
395 AssignSlot(UnslotedSU->getInstr(), Slot);
399 unsigned R600SchedStrategy::AvailablesAluCount() const {
400 return AvailableAlus[AluAny].size() + AvailableAlus[AluT_XYZW].size() +
401 AvailableAlus[AluT_X].size() + AvailableAlus[AluT_Y].size() +
402 AvailableAlus[AluT_Z].size() + AvailableAlus[AluT_W].size() +
403 AvailableAlus[AluTrans].size() + AvailableAlus[AluDiscarded].size() +
404 AvailableAlus[AluPredX].size();
407 SUnit* R600SchedStrategy::pickAlu() {
408 while (AvailablesAluCount() || !Pending[IDAlu].empty()) {
409 if (!OccupedSlotsMask) {
410 // Bottom up scheduling : predX must comes first
411 if (!AvailableAlus[AluPredX].empty()) {
412 OccupedSlotsMask |= 31;
413 return PopInst(AvailableAlus[AluPredX], false);
415 // Flush physical reg copies (RA will discard them)
416 if (!AvailableAlus[AluDiscarded].empty()) {
417 OccupedSlotsMask |= 31;
418 return PopInst(AvailableAlus[AluDiscarded], false);
420 // If there is a T_XYZW alu available, use it
421 if (!AvailableAlus[AluT_XYZW].empty()) {
422 OccupedSlotsMask |= 15;
423 return PopInst(AvailableAlus[AluT_XYZW], false);
426 bool TransSlotOccuped = OccupedSlotsMask & 16;
427 if (!TransSlotOccuped && VLIW5) {
428 if (!AvailableAlus[AluTrans].empty()) {
429 OccupedSlotsMask |= 16;
430 return PopInst(AvailableAlus[AluTrans], false);
432 SUnit *SU = AttemptFillSlot(3, true);
434 OccupedSlotsMask |= 16;
438 for (int Chan = 3; Chan > -1; --Chan) {
439 bool isOccupied = OccupedSlotsMask & (1 << Chan);
441 SUnit *SU = AttemptFillSlot(Chan, false);
443 OccupedSlotsMask |= (1 << Chan);
444 InstructionsGroupCandidate.push_back(SU->getInstr());
454 SUnit* R600SchedStrategy::pickOther(int QID) {
456 std::vector<SUnit *> &AQ = Available[QID];
459 MoveUnits(Pending[QID], AQ);
463 AQ.resize(AQ.size() - 1);