1 //===----- R600Packetizer.cpp - VLIW packetizer ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass implements instructions packetization for R600. It unsets isLast
12 /// bit of instructions inside a bundle and substitutes src register with
13 /// PreviousVector when applicable.
15 //===----------------------------------------------------------------------===//
17 #ifndef R600PACKETIZER_CPP
18 #define R600PACKETIZER_CPP
20 #define DEBUG_TYPE "packets"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/CodeGen/DFAPacketizer.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/ScheduleDAG.h"
30 #include "R600InstrInfo.h"
34 class R600Packetizer : public MachineFunctionPass {
38 R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
40 void getAnalysisUsage(AnalysisUsage &AU) const {
42 AU.addRequired<MachineDominatorTree>();
43 AU.addPreserved<MachineDominatorTree>();
44 AU.addRequired<MachineLoopInfo>();
45 AU.addPreserved<MachineLoopInfo>();
46 MachineFunctionPass::getAnalysisUsage(AU);
49 const char *getPassName() const {
50 return "R600 Packetizer";
53 bool runOnMachineFunction(MachineFunction &Fn);
55 char R600Packetizer::ID = 0;
57 class R600PacketizerList : public VLIWPacketizerList {
60 const R600InstrInfo *TII;
61 const R600RegisterInfo &TRI;
72 unsigned getSlot(const MachineInstr *MI) const {
73 return TRI.getHWRegChan(MI->getOperand(0).getReg());
76 std::vector<unsigned> getPreviousVector(MachineBasicBlock::iterator I) const {
77 std::vector<unsigned> Result;
79 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
81 MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
84 while (BI->isBundledWithPred() && !TII->isPredicated(BI)) {
85 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600Operands::WRITE);
86 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm())
87 Result.push_back(BI->getOperand(0).getReg());
93 void substitutePV(MachineInstr *MI, const std::vector<unsigned> &PV) const {
94 R600Operands::Ops Ops[] = {
99 for (unsigned i = 0; i < 3; i++) {
100 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
103 unsigned Src = MI->getOperand(OperandIdx).getReg();
104 for (unsigned j = 0, e = PV.size(); j < e; j++) {
106 unsigned Chan = TRI.getHWRegChan(Src);
110 PVReg = AMDGPU::PV_X;
113 PVReg = AMDGPU::PV_Y;
116 PVReg = AMDGPU::PV_Z;
119 PVReg = AMDGPU::PV_W;
122 llvm_unreachable("Invalid Chan");
124 MI->getOperand(OperandIdx).setReg(PVReg);
132 R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
133 MachineDominatorTree &MDT)
134 : VLIWPacketizerList(MF, MLI, MDT, true),
135 TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())),
136 TRI(TII->getRegisterInfo()) { }
138 // initPacketizerState - initialize some internal flags.
139 void initPacketizerState() { }
141 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
142 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) {
146 // isSoloInstruction - return true if instruction MI can not be packetized
147 // with any other instruction, which means that MI itself is a packet.
148 bool isSoloInstruction(MachineInstr *MI) {
149 if (TII->isVector(*MI))
151 if (!TII->isALUInstr(MI->getOpcode()))
153 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TRANS_ONLY)
155 if (TII->isTransOnly(MI))
160 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
162 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
163 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
164 if (getSlot(MII) <= getSlot(MIJ))
166 // Does MII and MIJ share the same pred_sel ?
167 int OpI = TII->getOperandIdx(MII->getOpcode(), R600Operands::PRED_SEL),
168 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600Operands::PRED_SEL);
169 unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
170 PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
173 if (SUJ->isSucc(SUI)) {
174 for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
175 const SDep &Dep = SUJ->Succs[i];
176 if (Dep.getSUnit() != SUI)
178 if (Dep.getKind() == SDep::Anti)
180 if (Dep.getKind() == SDep::Output)
181 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
189 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
191 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {return false;}
193 void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
194 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600Operands::LAST);
195 MI->getOperand(LastOp).setImm(Bit);
198 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
199 CurrentPacketMIs.push_back(MI);
200 bool FitsConstLimits = TII->canBundle(CurrentPacketMIs);
202 if (!FitsConstLimits) {
203 dbgs() << "Couldn't pack :\n";
205 dbgs() << "with the following packets :\n";
206 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
207 CurrentPacketMIs[i]->dump();
210 dbgs() << "because of Consts read limitations\n";
212 const std::vector<unsigned> &PV = getPreviousVector(MI);
213 bool FitsReadPortLimits = fitsReadPortLimitation(CurrentPacketMIs, PV);
215 if (!FitsReadPortLimits) {
216 dbgs() << "Couldn't pack :\n";
218 dbgs() << "with the following packets :\n";
219 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
220 CurrentPacketMIs[i]->dump();
223 dbgs() << "because of Read port limitations\n";
225 bool isBundlable = FitsConstLimits && FitsReadPortLimits;
226 CurrentPacketMIs.pop_back();
228 endPacket(MI->getParent(), MI);
229 substitutePV(MI, getPreviousVector(MI));
230 return VLIWPacketizerList::addToPacket(MI);
232 if (!CurrentPacketMIs.empty())
233 setIsLastBit(CurrentPacketMIs.back(), 0);
234 substitutePV(MI, PV);
235 return VLIWPacketizerList::addToPacket(MI);
238 std::vector<std::pair<int, unsigned> >
239 ExtractSrcs(const MachineInstr *MI, const std::vector<unsigned> &PV) const {
240 R600Operands::Ops Ops[] = {
245 std::vector<std::pair<int, unsigned> > Result;
246 for (unsigned i = 0; i < 3; i++) {
247 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
249 Result.push_back(std::pair<int, unsigned>(-1,0));
252 unsigned Src = MI->getOperand(OperandIdx).getReg();
253 if (std::find(PV.begin(), PV.end(), Src) != PV.end()) {
254 Result.push_back(std::pair<int, unsigned>(-1,0));
257 unsigned Reg = TRI.getEncodingValue(Src) & 0xff;
259 Result.push_back(std::pair<int, unsigned>(-1,0));
262 unsigned Chan = TRI.getHWRegChan(Src);
263 Result.push_back(std::pair<int, unsigned>(Reg, Chan));
268 std::vector<std::pair<int, unsigned> >
269 Swizzle(std::vector<std::pair<int, unsigned> > Src,
270 BankSwizzle Swz) const {
275 std::swap(Src[1], Src[2]);
278 std::swap(Src[0], Src[1]);
281 std::swap(Src[0], Src[1]);
282 std::swap(Src[0], Src[2]);
285 std::swap(Src[0], Src[2]);
286 std::swap(Src[0], Src[1]);
289 std::swap(Src[0], Src[2]);
295 bool isLegal(const std::vector<MachineInstr *> &IG,
296 const std::vector<BankSwizzle> &Swz,
297 const std::vector<unsigned> &PV) const {
298 assert (Swz.size() == IG.size());
300 memset(Vector, -1, sizeof(Vector));
301 for (unsigned i = 0, e = IG.size(); i < e; i++) {
302 const std::vector<std::pair<int, unsigned> > &Srcs =
303 Swizzle(ExtractSrcs(IG[i], PV), Swz[i]);
304 for (unsigned j = 0; j < 3; j++) {
305 const std::pair<int, unsigned> &Src = Srcs[j];
308 if (Vector[Src.second][j] < 0)
309 Vector[Src.second][j] = Src.first;
310 if (Vector[Src.second][j] != Src.first)
317 bool recursiveFitsFPLimitation(
318 std::vector<MachineInstr *> IG,
319 const std::vector<unsigned> &PV,
320 std::vector<BankSwizzle> &SwzCandidate,
321 std::vector<MachineInstr *> CurrentlyChecked)
323 if (!isLegal(CurrentlyChecked, SwzCandidate, PV))
325 if (IG.size() == CurrentlyChecked.size()) {
328 BankSwizzle AvailableSwizzle[] = {
336 CurrentlyChecked.push_back(IG[CurrentlyChecked.size()]);
337 for (unsigned i = 0; i < 6; i++) {
338 SwzCandidate.push_back(AvailableSwizzle[i]);
339 if (recursiveFitsFPLimitation(IG, PV, SwzCandidate, CurrentlyChecked))
341 SwzCandidate.pop_back();
346 bool fitsReadPortLimitation(
347 std::vector<MachineInstr *> IG,
348 const std::vector<unsigned> &PV)
350 //Todo : support shared src0 - src1 operand
351 std::vector<BankSwizzle> SwzCandidate;
352 bool Result = recursiveFitsFPLimitation(IG, PV, SwzCandidate,
353 std::vector<MachineInstr *>());
356 for (unsigned i = 0, e = IG.size(); i < e; i++) {
357 MachineInstr *MI = IG[i];
358 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
359 R600Operands::BANK_SWIZZLE);
360 MI->getOperand(Op).setImm(SwzCandidate[i]);
366 bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
367 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
368 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
369 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
371 // Instantiate the packetizer.
372 R600PacketizerList Packetizer(Fn, MLI, MDT);
374 // DFA state table should not be empty.
375 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
378 // Loop over all basic blocks and remove KILL pseudo-instructions
379 // These instructions confuse the dependence analysis. Consider:
381 // R0 = KILL R0, D0 (Insn 1)
383 // Here, Insn 1 will result in the dependence graph not emitting an output
384 // dependence between Insn 0 and Insn 2. This can lead to incorrect
387 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
388 MBB != MBBe; ++MBB) {
389 MachineBasicBlock::iterator End = MBB->end();
390 MachineBasicBlock::iterator MI = MBB->begin();
393 MachineBasicBlock::iterator DeleteMI = MI;
395 MBB->erase(DeleteMI);
403 // Loop over all of the basic blocks.
404 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
405 MBB != MBBe; ++MBB) {
406 // Find scheduling regions and schedule / packetize each region.
407 unsigned RemainingCount = MBB->size();
408 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
409 RegionEnd != MBB->begin();) {
410 // The next region starts above the previous region. Look backward in the
411 // instruction stream until we find the nearest boundary.
412 MachineBasicBlock::iterator I = RegionEnd;
413 for(;I != MBB->begin(); --I, --RemainingCount) {
414 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
419 // Skip empty scheduling regions.
420 if (I == RegionEnd) {
421 RegionEnd = llvm::prior(RegionEnd);
425 // Skip regions with one instruction.
426 if (I == llvm::prior(RegionEnd)) {
427 RegionEnd = llvm::prior(RegionEnd);
431 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
442 llvm::FunctionPass *llvm::createR600Packetizer(TargetMachine &tm) {
443 return new R600Packetizer(tm);
446 #endif // R600PACKETIZER_CPP