1 //===----- R600Packetizer.cpp - VLIW packetizer ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass implements instructions packetization for R600. It unsets isLast
12 /// bit of instructions inside a bundle and substitutes src register with
13 /// PreviousVector when applicable.
15 //===----------------------------------------------------------------------===//
17 #ifndef R600PACKETIZER_CPP
18 #define R600PACKETIZER_CPP
20 #define DEBUG_TYPE "packets"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/CodeGen/DFAPacketizer.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/ScheduleDAG.h"
30 #include "R600InstrInfo.h"
34 class R600Packetizer : public MachineFunctionPass {
38 R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
40 void getAnalysisUsage(AnalysisUsage &AU) const {
42 AU.addRequired<MachineDominatorTree>();
43 AU.addPreserved<MachineDominatorTree>();
44 AU.addRequired<MachineLoopInfo>();
45 AU.addPreserved<MachineLoopInfo>();
46 MachineFunctionPass::getAnalysisUsage(AU);
49 const char *getPassName() const {
50 return "R600 Packetizer";
53 bool runOnMachineFunction(MachineFunction &Fn);
55 char R600Packetizer::ID = 0;
57 class R600PacketizerList : public VLIWPacketizerList {
60 const R600InstrInfo *TII;
61 const R600RegisterInfo &TRI;
72 unsigned getSlot(const MachineInstr *MI) const {
73 return TRI.getHWRegChan(MI->getOperand(0).getReg());
76 /// \returns register to PV chan mapping for bundle/single instructions that
77 /// immediatly precedes I.
78 DenseMap<unsigned, unsigned> getPreviousVector(MachineBasicBlock::iterator I)
80 DenseMap<unsigned, unsigned> Result;
82 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
84 MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
88 if (TII->isPredicated(BI))
90 if (TII->isTransOnly(BI))
92 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600Operands::WRITE);
95 if (BI->getOperand(OperandIdx).getImm() == 0)
97 unsigned Dst = BI->getOperand(0).getReg();
98 if (BI->getOpcode() == AMDGPU::DOT4_r600_real) {
99 Result[Dst] = AMDGPU::PV_X;
103 switch (TRI.getHWRegChan(Dst)) {
105 PVReg = AMDGPU::PV_X;
108 PVReg = AMDGPU::PV_Y;
111 PVReg = AMDGPU::PV_Z;
114 PVReg = AMDGPU::PV_W;
117 llvm_unreachable("Invalid Chan");
120 } while ((++BI)->isBundledWithPred());
124 void substitutePV(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PVs)
126 R600Operands::Ops Ops[] = {
131 for (unsigned i = 0; i < 3; i++) {
132 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
135 unsigned Src = MI->getOperand(OperandIdx).getReg();
136 const DenseMap<unsigned, unsigned>::const_iterator It = PVs.find(Src);
138 MI->getOperand(OperandIdx).setReg(It->second);
143 R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
144 MachineDominatorTree &MDT)
145 : VLIWPacketizerList(MF, MLI, MDT, true),
146 TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())),
147 TRI(TII->getRegisterInfo()) { }
149 // initPacketizerState - initialize some internal flags.
150 void initPacketizerState() { }
152 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
153 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) {
157 // isSoloInstruction - return true if instruction MI can not be packetized
158 // with any other instruction, which means that MI itself is a packet.
159 bool isSoloInstruction(MachineInstr *MI) {
160 if (TII->isVector(*MI))
162 if (!TII->isALUInstr(MI->getOpcode()))
164 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TRANS_ONLY)
166 if (TII->isTransOnly(MI))
171 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
173 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
174 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
175 if (getSlot(MII) <= getSlot(MIJ))
177 // Does MII and MIJ share the same pred_sel ?
178 int OpI = TII->getOperandIdx(MII->getOpcode(), R600Operands::PRED_SEL),
179 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600Operands::PRED_SEL);
180 unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
181 PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
184 if (SUJ->isSucc(SUI)) {
185 for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
186 const SDep &Dep = SUJ->Succs[i];
187 if (Dep.getSUnit() != SUI)
189 if (Dep.getKind() == SDep::Anti)
191 if (Dep.getKind() == SDep::Output)
192 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
200 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
202 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {return false;}
204 void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
205 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600Operands::LAST);
206 MI->getOperand(LastOp).setImm(Bit);
209 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
210 CurrentPacketMIs.push_back(MI);
211 bool FitsConstLimits = TII->canBundle(CurrentPacketMIs);
213 if (!FitsConstLimits) {
214 dbgs() << "Couldn't pack :\n";
216 dbgs() << "with the following packets :\n";
217 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
218 CurrentPacketMIs[i]->dump();
221 dbgs() << "because of Consts read limitations\n";
223 const DenseMap<unsigned, unsigned> &PV =
224 getPreviousVector(CurrentPacketMIs.front());
225 bool FitsReadPortLimits = fitsReadPortLimitation(CurrentPacketMIs, PV);
227 if (!FitsReadPortLimits) {
228 dbgs() << "Couldn't pack :\n";
230 dbgs() << "with the following packets :\n";
231 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
232 CurrentPacketMIs[i]->dump();
235 dbgs() << "because of Read port limitations\n";
237 bool isBundlable = FitsConstLimits && FitsReadPortLimits;
238 CurrentPacketMIs.pop_back();
240 endPacket(MI->getParent(), MI);
241 substitutePV(MI, getPreviousVector(MI));
242 return VLIWPacketizerList::addToPacket(MI);
244 if (!CurrentPacketMIs.empty())
245 setIsLastBit(CurrentPacketMIs.back(), 0);
246 substitutePV(MI, PV);
247 return VLIWPacketizerList::addToPacket(MI);
250 std::vector<std::pair<int, unsigned> >
251 ExtractSrcs(const MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV)
253 R600Operands::Ops Ops[] = {
258 std::vector<std::pair<int, unsigned> > Result;
259 for (unsigned i = 0; i < 3; i++) {
260 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
262 Result.push_back(std::pair<int, unsigned>(-1,0));
265 unsigned Src = MI->getOperand(OperandIdx).getReg();
266 if (PV.find(Src) != PV.end()) {
267 Result.push_back(std::pair<int, unsigned>(-1,0));
270 unsigned Reg = TRI.getEncodingValue(Src) & 0xff;
272 Result.push_back(std::pair<int, unsigned>(-1,0));
275 unsigned Chan = TRI.getHWRegChan(Src);
276 Result.push_back(std::pair<int, unsigned>(Reg, Chan));
281 std::vector<std::pair<int, unsigned> >
282 Swizzle(std::vector<std::pair<int, unsigned> > Src,
283 BankSwizzle Swz) const {
288 std::swap(Src[1], Src[2]);
291 std::swap(Src[0], Src[1]);
294 std::swap(Src[0], Src[1]);
295 std::swap(Src[0], Src[2]);
298 std::swap(Src[0], Src[2]);
299 std::swap(Src[0], Src[1]);
302 std::swap(Src[0], Src[2]);
308 bool isLegal(const std::vector<MachineInstr *> &IG,
309 const std::vector<BankSwizzle> &Swz,
310 const DenseMap<unsigned, unsigned> &PV) const {
311 assert (Swz.size() == IG.size());
313 memset(Vector, -1, sizeof(Vector));
314 for (unsigned i = 0, e = IG.size(); i < e; i++) {
315 const std::vector<std::pair<int, unsigned> > &Srcs =
316 Swizzle(ExtractSrcs(IG[i], PV), Swz[i]);
317 for (unsigned j = 0; j < 3; j++) {
318 const std::pair<int, unsigned> &Src = Srcs[j];
321 if (Vector[Src.second][j] < 0)
322 Vector[Src.second][j] = Src.first;
323 if (Vector[Src.second][j] != Src.first)
330 bool recursiveFitsFPLimitation(
331 std::vector<MachineInstr *> IG,
332 const DenseMap<unsigned, unsigned> &PV,
333 std::vector<BankSwizzle> &SwzCandidate,
334 std::vector<MachineInstr *> CurrentlyChecked)
336 if (!isLegal(CurrentlyChecked, SwzCandidate, PV))
338 if (IG.size() == CurrentlyChecked.size()) {
341 BankSwizzle AvailableSwizzle[] = {
349 CurrentlyChecked.push_back(IG[CurrentlyChecked.size()]);
350 for (unsigned i = 0; i < 6; i++) {
351 SwzCandidate.push_back(AvailableSwizzle[i]);
352 if (recursiveFitsFPLimitation(IG, PV, SwzCandidate, CurrentlyChecked))
354 SwzCandidate.pop_back();
359 bool fitsReadPortLimitation(
360 std::vector<MachineInstr *> IG,
361 const DenseMap<unsigned, unsigned> &PV)
363 //Todo : support shared src0 - src1 operand
364 std::vector<BankSwizzle> SwzCandidate;
365 bool Result = recursiveFitsFPLimitation(IG, PV, SwzCandidate,
366 std::vector<MachineInstr *>());
369 for (unsigned i = 0, e = IG.size(); i < e; i++) {
370 MachineInstr *MI = IG[i];
371 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
372 R600Operands::BANK_SWIZZLE);
373 MI->getOperand(Op).setImm(SwzCandidate[i]);
379 bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
380 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
381 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
382 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
384 // Instantiate the packetizer.
385 R600PacketizerList Packetizer(Fn, MLI, MDT);
387 // DFA state table should not be empty.
388 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
391 // Loop over all basic blocks and remove KILL pseudo-instructions
392 // These instructions confuse the dependence analysis. Consider:
394 // R0 = KILL R0, D0 (Insn 1)
396 // Here, Insn 1 will result in the dependence graph not emitting an output
397 // dependence between Insn 0 and Insn 2. This can lead to incorrect
400 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
401 MBB != MBBe; ++MBB) {
402 MachineBasicBlock::iterator End = MBB->end();
403 MachineBasicBlock::iterator MI = MBB->begin();
406 MachineBasicBlock::iterator DeleteMI = MI;
408 MBB->erase(DeleteMI);
416 // Loop over all of the basic blocks.
417 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
418 MBB != MBBe; ++MBB) {
419 // Find scheduling regions and schedule / packetize each region.
420 unsigned RemainingCount = MBB->size();
421 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
422 RegionEnd != MBB->begin();) {
423 // The next region starts above the previous region. Look backward in the
424 // instruction stream until we find the nearest boundary.
425 MachineBasicBlock::iterator I = RegionEnd;
426 for(;I != MBB->begin(); --I, --RemainingCount) {
427 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
432 // Skip empty scheduling regions.
433 if (I == RegionEnd) {
434 RegionEnd = llvm::prior(RegionEnd);
438 // Skip regions with one instruction.
439 if (I == llvm::prior(RegionEnd)) {
440 RegionEnd = llvm::prior(RegionEnd);
444 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
455 llvm::FunctionPass *llvm::createR600Packetizer(TargetMachine &tm) {
456 return new R600Packetizer(tm);
459 #endif // R600PACKETIZER_CPP