1 //===----- R600Packetizer.cpp - VLIW packetizer ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass implements instructions packetization for R600. It unsets isLast
12 /// bit of instructions inside a bundle and substitutes src register with
13 /// PreviousVector when applicable.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "packets"
18 #include "llvm/Support/Debug.h"
20 #include "R600InstrInfo.h"
21 #include "llvm/CodeGen/DFAPacketizer.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/ScheduleDAG.h"
27 #include "llvm/Support/raw_ostream.h"
33 class R600Packetizer : public MachineFunctionPass {
37 R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
39 void getAnalysisUsage(AnalysisUsage &AU) const {
41 AU.addRequired<MachineDominatorTree>();
42 AU.addPreserved<MachineDominatorTree>();
43 AU.addRequired<MachineLoopInfo>();
44 AU.addPreserved<MachineLoopInfo>();
45 MachineFunctionPass::getAnalysisUsage(AU);
48 const char *getPassName() const {
49 return "R600 Packetizer";
52 bool runOnMachineFunction(MachineFunction &Fn);
54 char R600Packetizer::ID = 0;
56 class R600PacketizerList : public VLIWPacketizerList {
59 const R600InstrInfo *TII;
60 const R600RegisterInfo &TRI;
62 unsigned getSlot(const MachineInstr *MI) const {
63 return TRI.getHWRegChan(MI->getOperand(0).getReg());
66 /// \returns register to PV chan mapping for bundle/single instructions that
67 /// immediatly precedes I.
68 DenseMap<unsigned, unsigned> getPreviousVector(MachineBasicBlock::iterator I)
70 DenseMap<unsigned, unsigned> Result;
72 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
74 MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
78 if (TII->isPredicated(BI))
80 if (TII->isTransOnly(BI))
82 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600Operands::WRITE);
83 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
85 unsigned Dst = BI->getOperand(0).getReg();
86 if (BI->getOpcode() == AMDGPU::DOT4_r600 ||
87 BI->getOpcode() == AMDGPU::DOT4_eg) {
88 Result[Dst] = AMDGPU::PV_X;
92 switch (TRI.getHWRegChan(Dst)) {
100 PVReg = AMDGPU::PV_Z;
103 PVReg = AMDGPU::PV_W;
106 llvm_unreachable("Invalid Chan");
109 } while ((++BI)->isBundledWithPred());
113 void substitutePV(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PVs)
115 R600Operands::Ops Ops[] = {
120 for (unsigned i = 0; i < 3; i++) {
121 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
124 unsigned Src = MI->getOperand(OperandIdx).getReg();
125 const DenseMap<unsigned, unsigned>::const_iterator It = PVs.find(Src);
127 MI->getOperand(OperandIdx).setReg(It->second);
132 R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
133 MachineDominatorTree &MDT)
134 : VLIWPacketizerList(MF, MLI, MDT, true),
135 TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())),
136 TRI(TII->getRegisterInfo()) { }
138 // initPacketizerState - initialize some internal flags.
139 void initPacketizerState() { }
141 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
142 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) {
146 // isSoloInstruction - return true if instruction MI can not be packetized
147 // with any other instruction, which means that MI itself is a packet.
148 bool isSoloInstruction(MachineInstr *MI) {
149 if (TII->isVector(*MI))
151 if (!TII->isALUInstr(MI->getOpcode()))
153 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TRANS_ONLY)
155 if (TII->isTransOnly(MI))
160 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
162 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
163 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
164 if (getSlot(MII) <= getSlot(MIJ))
166 // Does MII and MIJ share the same pred_sel ?
167 int OpI = TII->getOperandIdx(MII->getOpcode(), R600Operands::PRED_SEL),
168 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600Operands::PRED_SEL);
169 unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
170 PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
173 if (SUJ->isSucc(SUI)) {
174 for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
175 const SDep &Dep = SUJ->Succs[i];
176 if (Dep.getSUnit() != SUI)
178 if (Dep.getKind() == SDep::Anti)
180 if (Dep.getKind() == SDep::Output)
181 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
189 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
191 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {return false;}
193 void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
194 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600Operands::LAST);
195 MI->getOperand(LastOp).setImm(Bit);
198 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
199 CurrentPacketMIs.push_back(MI);
200 bool FitsConstLimits = TII->canBundle(CurrentPacketMIs);
202 if (!FitsConstLimits) {
203 dbgs() << "Couldn't pack :\n";
205 dbgs() << "with the following packets :\n";
206 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
207 CurrentPacketMIs[i]->dump();
210 dbgs() << "because of Consts read limitations\n";
212 const DenseMap<unsigned, unsigned> &PV =
213 getPreviousVector(CurrentPacketMIs.front());
214 std::vector<R600InstrInfo::BankSwizzle> BS;
215 bool FitsReadPortLimits =
216 TII->fitsReadPortLimitations(CurrentPacketMIs, PV, BS);
218 if (!FitsReadPortLimits) {
219 dbgs() << "Couldn't pack :\n";
221 dbgs() << "with the following packets :\n";
222 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
223 CurrentPacketMIs[i]->dump();
226 dbgs() << "because of Read port limitations\n";
228 bool isBundlable = FitsConstLimits && FitsReadPortLimits;
230 for (unsigned i = 0, e = CurrentPacketMIs.size(); i < e; i++) {
231 MachineInstr *MI = CurrentPacketMIs[i];
232 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
233 R600Operands::BANK_SWIZZLE);
234 MI->getOperand(Op).setImm(BS[i]);
237 CurrentPacketMIs.pop_back();
239 endPacket(MI->getParent(), MI);
240 substitutePV(MI, getPreviousVector(MI));
241 return VLIWPacketizerList::addToPacket(MI);
243 if (!CurrentPacketMIs.empty())
244 setIsLastBit(CurrentPacketMIs.back(), 0);
245 substitutePV(MI, PV);
246 return VLIWPacketizerList::addToPacket(MI);
250 bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
251 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
252 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
253 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
255 // Instantiate the packetizer.
256 R600PacketizerList Packetizer(Fn, MLI, MDT);
258 // DFA state table should not be empty.
259 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
262 // Loop over all basic blocks and remove KILL pseudo-instructions
263 // These instructions confuse the dependence analysis. Consider:
265 // R0 = KILL R0, D0 (Insn 1)
267 // Here, Insn 1 will result in the dependence graph not emitting an output
268 // dependence between Insn 0 and Insn 2. This can lead to incorrect
271 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
272 MBB != MBBe; ++MBB) {
273 MachineBasicBlock::iterator End = MBB->end();
274 MachineBasicBlock::iterator MI = MBB->begin();
277 MachineBasicBlock::iterator DeleteMI = MI;
279 MBB->erase(DeleteMI);
287 // Loop over all of the basic blocks.
288 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
289 MBB != MBBe; ++MBB) {
290 // Find scheduling regions and schedule / packetize each region.
291 unsigned RemainingCount = MBB->size();
292 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
293 RegionEnd != MBB->begin();) {
294 // The next region starts above the previous region. Look backward in the
295 // instruction stream until we find the nearest boundary.
296 MachineBasicBlock::iterator I = RegionEnd;
297 for(;I != MBB->begin(); --I, --RemainingCount) {
298 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
303 // Skip empty scheduling regions.
304 if (I == RegionEnd) {
305 RegionEnd = llvm::prior(RegionEnd);
309 // Skip regions with one instruction.
310 if (I == llvm::prior(RegionEnd)) {
311 RegionEnd = llvm::prior(RegionEnd);
315 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
324 } // end anonymous namespace
326 llvm::FunctionPass *llvm::createR600Packetizer(TargetMachine &tm) {
327 return new R600Packetizer(tm);