1 //===----- R600Packetizer.cpp - VLIW packetizer ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass implements instructions packetization for R600. It unsets isLast
12 /// bit of instructions inside a bundle and substitutes src register with
13 /// PreviousVector when applicable.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/Support/Debug.h"
19 #include "AMDGPUSubtarget.h"
20 #include "R600InstrInfo.h"
21 #include "llvm/CodeGen/DFAPacketizer.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/ScheduleDAG.h"
27 #include "llvm/Support/raw_ostream.h"
31 #define DEBUG_TYPE "packets"
35 class R600Packetizer : public MachineFunctionPass {
39 R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
41 void getAnalysisUsage(AnalysisUsage &AU) const override {
43 AU.addRequired<MachineDominatorTree>();
44 AU.addPreserved<MachineDominatorTree>();
45 AU.addRequired<MachineLoopInfo>();
46 AU.addPreserved<MachineLoopInfo>();
47 MachineFunctionPass::getAnalysisUsage(AU);
50 const char *getPassName() const override {
51 return "R600 Packetizer";
54 bool runOnMachineFunction(MachineFunction &Fn) override;
56 char R600Packetizer::ID = 0;
58 class R600PacketizerList : public VLIWPacketizerList {
61 const R600InstrInfo *TII;
62 const R600RegisterInfo &TRI;
64 bool ConsideredInstUsesAlreadyWrittenVectorElement;
66 unsigned getSlot(const MachineInstr *MI) const {
67 return TRI.getHWRegChan(MI->getOperand(0).getReg());
70 /// \returns register to PV chan mapping for bundle/single instructions that
71 /// immediately precedes I.
72 DenseMap<unsigned, unsigned> getPreviousVector(MachineBasicBlock::iterator I)
74 DenseMap<unsigned, unsigned> Result;
76 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
78 MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
84 int BISlot = getSlot(BI);
85 if (LastDstChan >= BISlot)
88 if (TII->isPredicated(BI))
90 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
91 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
97 unsigned Dst = BI->getOperand(DstIdx).getReg();
98 if (isTrans || TII->isTransOnly(BI)) {
99 Result[Dst] = AMDGPU::PS;
102 if (BI->getOpcode() == AMDGPU::DOT4_r600 ||
103 BI->getOpcode() == AMDGPU::DOT4_eg) {
104 Result[Dst] = AMDGPU::PV_X;
107 if (Dst == AMDGPU::OQAP) {
111 switch (TRI.getHWRegChan(Dst)) {
113 PVReg = AMDGPU::PV_X;
116 PVReg = AMDGPU::PV_Y;
119 PVReg = AMDGPU::PV_Z;
122 PVReg = AMDGPU::PV_W;
125 llvm_unreachable("Invalid Chan");
128 } while ((++BI)->isBundledWithPred());
132 void substitutePV(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PVs)
135 AMDGPU::OpName::src0,
136 AMDGPU::OpName::src1,
139 for (unsigned i = 0; i < 3; i++) {
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
143 unsigned Src = MI->getOperand(OperandIdx).getReg();
144 const DenseMap<unsigned, unsigned>::const_iterator It = PVs.find(Src);
146 MI->getOperand(OperandIdx).setReg(It->second);
151 R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
152 MachineDominatorTree &MDT)
153 : VLIWPacketizerList(MF, MLI, MDT, true),
154 TII(static_cast<const R600InstrInfo *>(
155 MF.getSubtarget().getInstrInfo())),
156 TRI(TII->getRegisterInfo()) {
157 VLIW5 = !MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA();
160 // initPacketizerState - initialize some internal flags.
161 void initPacketizerState() override {
162 ConsideredInstUsesAlreadyWrittenVectorElement = false;
165 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
166 bool ignorePseudoInstruction(MachineInstr *MI,
167 MachineBasicBlock *MBB) override {
171 // isSoloInstruction - return true if instruction MI can not be packetized
172 // with any other instruction, which means that MI itself is a packet.
173 bool isSoloInstruction(MachineInstr *MI) override {
174 if (TII->isVector(*MI))
176 if (!TII->isALUInstr(MI->getOpcode()))
178 if (MI->getOpcode() == AMDGPU::GROUP_BARRIER)
180 // XXX: This can be removed once the packetizer properly handles all the
181 // LDS instruction group restrictions.
182 if (TII->isLDSInstr(MI->getOpcode()))
187 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
189 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override {
190 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
191 if (getSlot(MII) == getSlot(MIJ))
192 ConsideredInstUsesAlreadyWrittenVectorElement = true;
193 // Does MII and MIJ share the same pred_sel ?
194 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
195 OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel);
196 unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
197 PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
200 if (SUJ->isSucc(SUI)) {
201 for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
202 const SDep &Dep = SUJ->Succs[i];
203 if (Dep.getSUnit() != SUI)
205 if (Dep.getKind() == SDep::Anti)
207 if (Dep.getKind() == SDep::Output)
208 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
214 bool ARDef = TII->definesAddressRegister(MII) ||
215 TII->definesAddressRegister(MIJ);
216 bool ARUse = TII->usesAddressRegister(MII) ||
217 TII->usesAddressRegister(MIJ);
224 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
226 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override {
230 void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
231 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last);
232 MI->getOperand(LastOp).setImm(Bit);
235 bool isBundlableWithCurrentPMI(MachineInstr *MI,
236 const DenseMap<unsigned, unsigned> &PV,
237 std::vector<R600InstrInfo::BankSwizzle> &BS,
239 isTransSlot = TII->isTransOnly(MI);
240 assert (!isTransSlot || VLIW5);
242 // Is the dst reg sequence legal ?
243 if (!isTransSlot && !CurrentPacketMIs.empty()) {
244 if (getSlot(MI) <= getSlot(CurrentPacketMIs.back())) {
245 if (ConsideredInstUsesAlreadyWrittenVectorElement &&
246 !TII->isVectorOnly(MI) && VLIW5) {
248 DEBUG(dbgs() << "Considering as Trans Inst :"; MI->dump(););
255 // Are the Constants limitations met ?
256 CurrentPacketMIs.push_back(MI);
257 if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) {
259 dbgs() << "Couldn't pack :\n";
261 dbgs() << "with the following packets :\n";
262 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
263 CurrentPacketMIs[i]->dump();
266 dbgs() << "because of Consts read limitations\n";
268 CurrentPacketMIs.pop_back();
272 // Is there a BankSwizzle set that meet Read Port limitations ?
273 if (!TII->fitsReadPortLimitations(CurrentPacketMIs,
274 PV, BS, isTransSlot)) {
276 dbgs() << "Couldn't pack :\n";
278 dbgs() << "with the following packets :\n";
279 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
280 CurrentPacketMIs[i]->dump();
283 dbgs() << "because of Read port limitations\n";
285 CurrentPacketMIs.pop_back();
289 // We cannot read LDS source registrs from the Trans slot.
290 if (isTransSlot && TII->readsLDSSrcReg(MI))
293 CurrentPacketMIs.pop_back();
297 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override {
298 MachineBasicBlock::iterator FirstInBundle =
299 CurrentPacketMIs.empty() ? MI : CurrentPacketMIs.front();
300 const DenseMap<unsigned, unsigned> &PV =
301 getPreviousVector(FirstInBundle);
302 std::vector<R600InstrInfo::BankSwizzle> BS;
305 if (isBundlableWithCurrentPMI(MI, PV, BS, isTransSlot)) {
306 for (unsigned i = 0, e = CurrentPacketMIs.size(); i < e; i++) {
307 MachineInstr *MI = CurrentPacketMIs[i];
308 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
309 AMDGPU::OpName::bank_swizzle);
310 MI->getOperand(Op).setImm(BS[i]);
312 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
313 AMDGPU::OpName::bank_swizzle);
314 MI->getOperand(Op).setImm(BS.back());
315 if (!CurrentPacketMIs.empty())
316 setIsLastBit(CurrentPacketMIs.back(), 0);
317 substitutePV(MI, PV);
318 MachineBasicBlock::iterator It = VLIWPacketizerList::addToPacket(MI);
320 endPacket(std::next(It)->getParent(), std::next(It));
324 endPacket(MI->getParent(), MI);
325 if (TII->isTransOnly(MI))
327 return VLIWPacketizerList::addToPacket(MI);
331 bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
332 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
333 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
334 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
336 // Instantiate the packetizer.
337 R600PacketizerList Packetizer(Fn, MLI, MDT);
339 // DFA state table should not be empty.
340 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
343 // Loop over all basic blocks and remove KILL pseudo-instructions
344 // These instructions confuse the dependence analysis. Consider:
346 // R0 = KILL R0, D0 (Insn 1)
348 // Here, Insn 1 will result in the dependence graph not emitting an output
349 // dependence between Insn 0 and Insn 2. This can lead to incorrect
352 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
353 MBB != MBBe; ++MBB) {
354 MachineBasicBlock::iterator End = MBB->end();
355 MachineBasicBlock::iterator MI = MBB->begin();
357 if (MI->isKill() || MI->getOpcode() == AMDGPU::IMPLICIT_DEF ||
358 (MI->getOpcode() == AMDGPU::CF_ALU && !MI->getOperand(8).getImm())) {
359 MachineBasicBlock::iterator DeleteMI = MI;
361 MBB->erase(DeleteMI);
369 // Loop over all of the basic blocks.
370 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
371 MBB != MBBe; ++MBB) {
372 // Find scheduling regions and schedule / packetize each region.
373 unsigned RemainingCount = MBB->size();
374 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
375 RegionEnd != MBB->begin();) {
376 // The next region starts above the previous region. Look backward in the
377 // instruction stream until we find the nearest boundary.
378 MachineBasicBlock::iterator I = RegionEnd;
379 for(;I != MBB->begin(); --I, --RemainingCount) {
380 if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
385 // Skip empty scheduling regions.
386 if (I == RegionEnd) {
387 RegionEnd = std::prev(RegionEnd);
391 // Skip regions with one instruction.
392 if (I == std::prev(RegionEnd)) {
393 RegionEnd = std::prev(RegionEnd);
397 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
406 } // end anonymous namespace
408 llvm::FunctionPass *llvm::createR600Packetizer(TargetMachine &tm) {
409 return new R600Packetizer(tm);