1 //===----- R600Packetizer.cpp - VLIW packetizer ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass implements instructions packetization for R600. It unsets isLast
12 /// bit of instructions inside a bundle and substitutes src register with
13 /// PreviousVector when applicable.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "packets"
18 #include "llvm/Support/Debug.h"
20 #include "R600InstrInfo.h"
21 #include "llvm/CodeGen/DFAPacketizer.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/ScheduleDAG.h"
27 #include "llvm/Support/raw_ostream.h"
33 class R600Packetizer : public MachineFunctionPass {
37 R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
39 void getAnalysisUsage(AnalysisUsage &AU) const {
41 AU.addRequired<MachineDominatorTree>();
42 AU.addPreserved<MachineDominatorTree>();
43 AU.addRequired<MachineLoopInfo>();
44 AU.addPreserved<MachineLoopInfo>();
45 MachineFunctionPass::getAnalysisUsage(AU);
48 const char *getPassName() const {
49 return "R600 Packetizer";
52 bool runOnMachineFunction(MachineFunction &Fn);
54 char R600Packetizer::ID = 0;
56 class R600PacketizerList : public VLIWPacketizerList {
59 const R600InstrInfo *TII;
60 const R600RegisterInfo &TRI;
62 unsigned getSlot(const MachineInstr *MI) const {
63 return TRI.getHWRegChan(MI->getOperand(0).getReg());
66 /// \returns register to PV chan mapping for bundle/single instructions that
67 /// immediatly precedes I.
68 DenseMap<unsigned, unsigned> getPreviousVector(MachineBasicBlock::iterator I)
70 DenseMap<unsigned, unsigned> Result;
72 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
74 MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
78 if (TII->isPredicated(BI))
80 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
81 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
83 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
87 unsigned Dst = BI->getOperand(DstIdx).getReg();
88 if (TII->isTransOnly(BI)) {
89 Result[Dst] = AMDGPU::PS;
92 if (BI->getOpcode() == AMDGPU::DOT4_r600 ||
93 BI->getOpcode() == AMDGPU::DOT4_eg) {
94 Result[Dst] = AMDGPU::PV_X;
97 if (Dst == AMDGPU::OQAP) {
101 switch (TRI.getHWRegChan(Dst)) {
103 PVReg = AMDGPU::PV_X;
106 PVReg = AMDGPU::PV_Y;
109 PVReg = AMDGPU::PV_Z;
112 PVReg = AMDGPU::PV_W;
115 llvm_unreachable("Invalid Chan");
118 } while ((++BI)->isBundledWithPred());
122 void substitutePV(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PVs)
125 AMDGPU::OpName::src0,
126 AMDGPU::OpName::src1,
129 for (unsigned i = 0; i < 3; i++) {
130 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
133 unsigned Src = MI->getOperand(OperandIdx).getReg();
134 const DenseMap<unsigned, unsigned>::const_iterator It = PVs.find(Src);
136 MI->getOperand(OperandIdx).setReg(It->second);
141 R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
142 MachineDominatorTree &MDT)
143 : VLIWPacketizerList(MF, MLI, MDT, true),
144 TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())),
145 TRI(TII->getRegisterInfo()) { }
147 // initPacketizerState - initialize some internal flags.
148 void initPacketizerState() { }
150 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
151 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) {
155 // isSoloInstruction - return true if instruction MI can not be packetized
156 // with any other instruction, which means that MI itself is a packet.
157 bool isSoloInstruction(MachineInstr *MI) {
158 if (TII->isVector(*MI))
160 if (!TII->isALUInstr(MI->getOpcode()))
162 if (MI->getOpcode() == AMDGPU::GROUP_BARRIER)
167 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
169 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
170 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
171 if (getSlot(MII) <= getSlot(MIJ) && !TII->isTransOnly(MII))
173 // Does MII and MIJ share the same pred_sel ?
174 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
175 OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel);
176 unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
177 PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
180 if (SUJ->isSucc(SUI)) {
181 for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
182 const SDep &Dep = SUJ->Succs[i];
183 if (Dep.getSUnit() != SUI)
185 if (Dep.getKind() == SDep::Anti)
187 if (Dep.getKind() == SDep::Output)
188 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
196 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
198 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {return false;}
200 void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
201 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last);
202 MI->getOperand(LastOp).setImm(Bit);
205 bool isBundlableWithCurrentPMI(MachineInstr *MI,
206 const DenseMap<unsigned, unsigned> &PV,
207 std::vector<R600InstrInfo::BankSwizzle> &BS,
209 isTransSlot = TII->isTransOnly(MI);
211 // Are the Constants limitations met ?
212 CurrentPacketMIs.push_back(MI);
213 if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) {
215 dbgs() << "Couldn't pack :\n";
217 dbgs() << "with the following packets :\n";
218 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
219 CurrentPacketMIs[i]->dump();
222 dbgs() << "because of Consts read limitations\n";
224 CurrentPacketMIs.pop_back();
228 // Is there a BankSwizzle set that meet Read Port limitations ?
229 if (!TII->fitsReadPortLimitations(CurrentPacketMIs,
230 PV, BS, isTransSlot)) {
232 dbgs() << "Couldn't pack :\n";
234 dbgs() << "with the following packets :\n";
235 for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
236 CurrentPacketMIs[i]->dump();
239 dbgs() << "because of Read port limitations\n";
241 CurrentPacketMIs.pop_back();
245 CurrentPacketMIs.pop_back();
249 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
250 MachineBasicBlock::iterator FirstInBundle =
251 CurrentPacketMIs.empty() ? MI : CurrentPacketMIs.front();
252 const DenseMap<unsigned, unsigned> &PV =
253 getPreviousVector(FirstInBundle);
254 std::vector<R600InstrInfo::BankSwizzle> BS;
257 if (isBundlableWithCurrentPMI(MI, PV, BS, isTransSlot)) {
258 for (unsigned i = 0, e = CurrentPacketMIs.size(); i < e; i++) {
259 MachineInstr *MI = CurrentPacketMIs[i];
260 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
261 AMDGPU::OpName::bank_swizzle);
262 MI->getOperand(Op).setImm(BS[i]);
264 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
265 AMDGPU::OpName::bank_swizzle);
266 MI->getOperand(Op).setImm(BS.back());
267 if (!CurrentPacketMIs.empty())
268 setIsLastBit(CurrentPacketMIs.back(), 0);
269 substitutePV(MI, PV);
270 MachineBasicBlock::iterator It = VLIWPacketizerList::addToPacket(MI);
272 endPacket(llvm::next(It)->getParent(), llvm::next(It));
276 endPacket(MI->getParent(), MI);
277 return VLIWPacketizerList::addToPacket(MI);
281 bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
282 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
283 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
284 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
286 // Instantiate the packetizer.
287 R600PacketizerList Packetizer(Fn, MLI, MDT);
289 // DFA state table should not be empty.
290 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
293 // Loop over all basic blocks and remove KILL pseudo-instructions
294 // These instructions confuse the dependence analysis. Consider:
296 // R0 = KILL R0, D0 (Insn 1)
298 // Here, Insn 1 will result in the dependence graph not emitting an output
299 // dependence between Insn 0 and Insn 2. This can lead to incorrect
302 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
303 MBB != MBBe; ++MBB) {
304 MachineBasicBlock::iterator End = MBB->end();
305 MachineBasicBlock::iterator MI = MBB->begin();
308 MachineBasicBlock::iterator DeleteMI = MI;
310 MBB->erase(DeleteMI);
318 // Loop over all of the basic blocks.
319 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
320 MBB != MBBe; ++MBB) {
321 // Find scheduling regions and schedule / packetize each region.
322 unsigned RemainingCount = MBB->size();
323 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
324 RegionEnd != MBB->begin();) {
325 // The next region starts above the previous region. Look backward in the
326 // instruction stream until we find the nearest boundary.
327 MachineBasicBlock::iterator I = RegionEnd;
328 for(;I != MBB->begin(); --I, --RemainingCount) {
329 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
334 // Skip empty scheduling regions.
335 if (I == RegionEnd) {
336 RegionEnd = llvm::prior(RegionEnd);
340 // Skip regions with one instruction.
341 if (I == llvm::prior(RegionEnd)) {
342 RegionEnd = llvm::prior(RegionEnd);
346 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
355 } // end anonymous namespace
357 llvm::FunctionPass *llvm::createR600Packetizer(TargetMachine &tm) {
358 return new R600Packetizer(tm);