1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
15 #include "R600RegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "R600Defines.h"
18 #include "R600MachineFunctionInfo.h"
22 R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
23 const TargetInstrInfo &tii)
24 : AMDGPURegisterInfo(tm, tii),
29 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
30 BitVector Reserved(getNumRegs());
31 const R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>();
33 Reserved.set(AMDGPU::ZERO);
34 Reserved.set(AMDGPU::HALF);
35 Reserved.set(AMDGPU::ONE);
36 Reserved.set(AMDGPU::ONE_INT);
37 Reserved.set(AMDGPU::NEG_HALF);
38 Reserved.set(AMDGPU::NEG_ONE);
39 Reserved.set(AMDGPU::PV_X);
40 Reserved.set(AMDGPU::ALU_LITERAL_X);
41 Reserved.set(AMDGPU::PREDICATE_BIT);
42 Reserved.set(AMDGPU::PRED_SEL_OFF);
43 Reserved.set(AMDGPU::PRED_SEL_ZERO);
44 Reserved.set(AMDGPU::PRED_SEL_ONE);
46 for (TargetRegisterClass::iterator I = AMDGPU::R600_CReg32RegClass.begin(),
47 E = AMDGPU::R600_CReg32RegClass.end(); I != E; ++I) {
51 for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(),
52 E = MFI->ReservedRegs.end(); I != E; ++I) {
59 const TargetRegisterClass *
60 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
61 switch (rc->getID()) {
62 case AMDGPU::GPRF32RegClassID:
63 case AMDGPU::GPRI32RegClassID:
64 return &AMDGPU::R600_Reg32RegClass;
69 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
70 return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
73 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
77 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
81 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const {
83 default: assert(!"Invalid channel index"); return 0;
84 case 0: return AMDGPU::sel_x;
85 case 1: return AMDGPU::sel_y;
86 case 2: return AMDGPU::sel_z;
87 case 3: return AMDGPU::sel_w;