lib/Target/R600/R600RegisterInfo.cpp

   1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// \brief R600 implementation of the TargetRegisterInfo class.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "R600RegisterInfo.h"
  16 #include "AMDGPUTargetMachine.h"
  17 #include "R600Defines.h"
  18 #include "R600InstrInfo.h"
  19 #include "R600MachineFunctionInfo.h"
  20
  21 using namespace llvm;
  22
  23 R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm)
  24 : AMDGPURegisterInfo(tm),
  25   TM(tm)
  26   { RCW.RegWeight = 0; RCW.WeightLimit = 0;}
  27
  28 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  29   BitVector Reserved(getNumRegs());
  30
  31   Reserved.set(AMDGPU::ZERO);
  32   Reserved.set(AMDGPU::HALF);
  33   Reserved.set(AMDGPU::ONE);
  34   Reserved.set(AMDGPU::ONE_INT);
  35   Reserved.set(AMDGPU::NEG_HALF);
  36   Reserved.set(AMDGPU::NEG_ONE);
  37   Reserved.set(AMDGPU::PV_X);
  38   Reserved.set(AMDGPU::ALU_LITERAL_X);
  39   Reserved.set(AMDGPU::ALU_CONST);
  40   Reserved.set(AMDGPU::PREDICATE_BIT);
  41   Reserved.set(AMDGPU::PRED_SEL_OFF);
  42   Reserved.set(AMDGPU::PRED_SEL_ZERO);
  43   Reserved.set(AMDGPU::PRED_SEL_ONE);
  44
  45   for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
  46                         E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
  47     Reserved.set(*I);
  48   }
  49
  50   for (TargetRegisterClass::iterator I = AMDGPU::TRegMemRegClass.begin(),
  51                                      E = AMDGPU::TRegMemRegClass.end();
  52                                      I !=  E; ++I) {
  53     Reserved.set(*I);
  54   }
  55
  56   const R600InstrInfo *RII =
  57     static_cast<const R600InstrInfo*>(TM.getInstrInfo());
  58   std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF);
  59   for (std::vector<unsigned>::iterator I = IndirectRegs.begin(),
  60                                        E = IndirectRegs.end();
  61                                        I != E; ++I) {
  62     Reserved.set(*I);
  63   }
  64   return Reserved;
  65 }
  66
  67 const TargetRegisterClass *
  68 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
  69   switch (rc->getID()) {
  70   case AMDGPU::GPRF32RegClassID:
  71   case AMDGPU::GPRI32RegClassID:
  72     return &AMDGPU::R600_Reg32RegClass;
  73   default: return rc;
  74   }
  75 }
  76
  77 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
  78   return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
  79 }
  80
  81 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
  82                                                                    MVT VT) const {
  83   switch(VT.SimpleTy) {
  84   default:
  85   case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
  86   }
  87 }
  88
  89 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const {
  90   switch (Channel) {
  91     default: assert(!"Invalid channel index"); return 0;
  92     case 0: return AMDGPU::sub0;
  93     case 1: return AMDGPU::sub1;
  94     case 2: return AMDGPU::sub2;
  95     case 3: return AMDGPU::sub3;
  96   }
  97 }
  98
  99 const RegClassWeight &R600RegisterInfo::getRegClassWeight(
 100   const TargetRegisterClass *RC) const {
 101   return RCW;
 102 }