1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
15 #include "R600RegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "R600Defines.h"
18 #include "R600InstrInfo.h"
19 #include "R600MachineFunctionInfo.h"
23 R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
24 const TargetInstrInfo &tii)
25 : AMDGPURegisterInfo(tm, tii),
30 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
31 BitVector Reserved(getNumRegs());
33 Reserved.set(AMDGPU::ZERO);
34 Reserved.set(AMDGPU::HALF);
35 Reserved.set(AMDGPU::ONE);
36 Reserved.set(AMDGPU::ONE_INT);
37 Reserved.set(AMDGPU::NEG_HALF);
38 Reserved.set(AMDGPU::NEG_ONE);
39 Reserved.set(AMDGPU::PV_X);
40 Reserved.set(AMDGPU::ALU_LITERAL_X);
41 Reserved.set(AMDGPU::ALU_CONST);
42 Reserved.set(AMDGPU::PREDICATE_BIT);
43 Reserved.set(AMDGPU::PRED_SEL_OFF);
44 Reserved.set(AMDGPU::PRED_SEL_ZERO);
45 Reserved.set(AMDGPU::PRED_SEL_ONE);
47 for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
48 E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
52 for (TargetRegisterClass::iterator I = AMDGPU::TRegMemRegClass.begin(),
53 E = AMDGPU::TRegMemRegClass.end();
58 const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII);
59 std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF);
60 for (std::vector<unsigned>::iterator I = IndirectRegs.begin(),
61 E = IndirectRegs.end();
68 const TargetRegisterClass *
69 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
70 switch (rc->getID()) {
71 case AMDGPU::GPRF32RegClassID:
72 case AMDGPU::GPRI32RegClassID:
73 return &AMDGPU::R600_Reg32RegClass;
78 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
79 return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
82 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
86 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
90 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const {
92 default: assert(!"Invalid channel index"); return 0;
93 case 0: return AMDGPU::sub0;
94 case 1: return AMDGPU::sub1;
95 case 2: return AMDGPU::sub2;
96 case 3: return AMDGPU::sub3;