1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
15 #include "R600RegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "R600Defines.h"
18 #include "R600InstrInfo.h"
19 #include "R600MachineFunctionInfo.h"
23 R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm)
24 : AMDGPURegisterInfo(tm),
26 { RCW.RegWeight = 0; RCW.WeightLimit = 0;}
28 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
29 BitVector Reserved(getNumRegs());
31 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
33 Reserved.set(AMDGPU::ZERO);
34 Reserved.set(AMDGPU::HALF);
35 Reserved.set(AMDGPU::ONE);
36 Reserved.set(AMDGPU::ONE_INT);
37 Reserved.set(AMDGPU::NEG_HALF);
38 Reserved.set(AMDGPU::NEG_ONE);
39 Reserved.set(AMDGPU::PV_X);
40 Reserved.set(AMDGPU::ALU_LITERAL_X);
41 Reserved.set(AMDGPU::ALU_CONST);
42 Reserved.set(AMDGPU::PREDICATE_BIT);
43 Reserved.set(AMDGPU::PRED_SEL_OFF);
44 Reserved.set(AMDGPU::PRED_SEL_ZERO);
45 Reserved.set(AMDGPU::PRED_SEL_ONE);
46 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
48 for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
49 E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
53 TII->reserveIndirectRegisters(Reserved, MF);
58 const TargetRegisterClass *
59 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
60 switch (rc->getID()) {
61 case AMDGPU::GPRF32RegClassID:
62 case AMDGPU::GPRI32RegClassID:
63 return &AMDGPU::R600_Reg32RegClass;
68 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
69 return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
72 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
73 return GET_REG_INDEX(getEncodingValue(Reg));
76 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
80 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
84 const RegClassWeight &R600RegisterInfo::getRegClassWeight(
85 const TargetRegisterClass *RC) const {
89 bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
90 assert(!TargetRegisterInfo::isVirtualRegister(Reg));