1 //===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600RegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600REGISTERINFO_H_
16 #define R600REGISTERINFO_H_
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUTargetMachine.h"
23 class R600TargetMachine;
24 class TargetInstrInfo;
26 struct R600RegisterInfo : public AMDGPURegisterInfo {
27 AMDGPUTargetMachine &TM;
28 const TargetInstrInfo &TII;
30 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
32 virtual BitVector getReservedRegs(const MachineFunction &MF) const;
34 /// \param RC is an AMDIL reg class.
36 /// \returns the R600 reg class that is equivalent to \p RC.
37 virtual const TargetRegisterClass *getISARegClass(
38 const TargetRegisterClass *RC) const;
40 /// \brief get the HW encoding for a register's channel.
41 unsigned getHWRegChan(unsigned reg) const;
43 /// \brief get the register class of the specified type to use in the
45 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
47 /// \returns the sub reg enum value for the given \p Channel
48 /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x)
49 unsigned getSubRegFromChannel(unsigned Channel) const;
53 } // End namespace llvm
55 #endif // AMDIDSAREGISTERINFO_H_