2 class R600Reg <string name, bits<16> encoding> : Register<name> {
3 let Namespace = "AMDGPU";
4 let HWEncoding = encoding;
7 class R600RegWithChan <string name, bits<9> sel, string chan> :
10 field bits<2> chan_encoding = !if(!eq(chan, "X"), 0,
11 !if(!eq(chan, "Y"), 1,
12 !if(!eq(chan, "Z"), 2,
13 !if(!eq(chan, "W"), 3, 0))));
14 let HWEncoding{8-0} = sel;
15 let HWEncoding{10-9} = chan_encoding;
16 let Namespace = "AMDGPU";
19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
20 RegisterWithSubRegs<n, subregs> {
21 let Namespace = "AMDGPU";
22 let SubRegIndices = [sel_x, sel_y, sel_z, sel_w];
23 let HWEncoding = encoding;
26 foreach Index = 0-127 in {
27 foreach Chan = [ "X", "Y", "Z", "W" ] in {
28 // 32-bit Temporary Registers
29 def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
31 // 128-bit Temporary Registers
32 def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",
33 [!cast<Register>("T"#Index#"_X"),
34 !cast<Register>("T"#Index#"_Y"),
35 !cast<Register>("T"#Index#"_Z"),
36 !cast<Register>("T"#Index#"_W")],
40 // Array Base Register holding input in FS
41 foreach Index = 448-464 in {
42 def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;
48 def ZERO : R600Reg<"0.0", 248>;
49 def ONE : R600Reg<"1.0", 249>;
50 def NEG_ONE : R600Reg<"-1.0", 249>;
51 def ONE_INT : R600Reg<"1", 250>;
52 def HALF : R600Reg<"0.5", 252>;
53 def NEG_HALF : R600Reg<"-0.5", 252>;
54 def ALU_LITERAL_X : R600Reg<"literal.x", 253>;
55 def PV_X : R600Reg<"pv.x", 254>;
56 def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
57 def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
58 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
59 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
61 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
62 (add (sequence "ArrayBase%u", 448, 464))>;
63 // special registers for ALU src operands
64 // const buffer reference, SRCx_SEL contains index
65 def ALU_CONST : R600Reg<"CBuf", 0>;
66 // interpolation param reference, SRCx_SEL contains index
67 def ALU_PARAM : R600Reg<"Param", 0>;
69 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
70 (add (sequence "T%u_X", 0, 127))>;
72 def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
73 (add (sequence "T%u_Y", 0, 127))>;
75 def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
76 (add (sequence "T%u_Z", 0, 127))>;
78 def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,
79 (add (sequence "T%u_W", 0, 127))>;
81 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
82 (interleave R600_TReg32_X, R600_TReg32_Y,
83 R600_TReg32_Z, R600_TReg32_W)>;
85 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
88 ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF,
92 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
93 PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>;
95 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
98 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
99 (add (sequence "T%u_XYZW", 0, 127))> {