2 class R600Reg <string name, bits<16> encoding> : Register<name> {
3 let Namespace = "AMDGPU";
4 let HWEncoding = encoding;
7 class R600RegWithChan <string name, bits<9> sel, string chan> :
10 field bits<2> chan_encoding = !if(!eq(chan, "X"), 0,
11 !if(!eq(chan, "Y"), 1,
12 !if(!eq(chan, "Z"), 2,
13 !if(!eq(chan, "W"), 3, 0))));
14 let HWEncoding{8-0} = sel;
15 let HWEncoding{10-9} = chan_encoding;
16 let Namespace = "AMDGPU";
19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
20 RegisterWithSubRegs<n, subregs> {
21 let Namespace = "AMDGPU";
22 let SubRegIndices = [sub0, sub1, sub2, sub3];
23 let HWEncoding = encoding;
26 foreach Index = 0-127 in {
27 foreach Chan = [ "X", "Y", "Z", "W" ] in {
28 // 32-bit Temporary Registers
29 def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
31 // Indirect addressing offset registers
32 def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,
34 def TRegMem#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index,
37 // 128-bit Temporary Registers
38 def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",
39 [!cast<Register>("T"#Index#"_X"),
40 !cast<Register>("T"#Index#"_Y"),
41 !cast<Register>("T"#Index#"_Z"),
42 !cast<Register>("T"#Index#"_W")],
46 // Array Base Register holding input in FS
47 foreach Index = 448-480 in {
48 def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;
54 def ZERO : R600Reg<"0.0", 248>;
55 def ONE : R600Reg<"1.0", 249>;
56 def NEG_ONE : R600Reg<"-1.0", 249>;
57 def ONE_INT : R600Reg<"1", 250>;
58 def HALF : R600Reg<"0.5", 252>;
59 def NEG_HALF : R600Reg<"-0.5", 252>;
60 def ALU_LITERAL_X : R600Reg<"literal.x", 253>;
61 def PV_X : R600Reg<"pv.x", 254>;
62 def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
63 def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
64 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
65 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
66 def AR_X : R600Reg<"AR.x", 0>;
68 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
69 (add (sequence "ArrayBase%u", 448, 480))>;
70 // special registers for ALU src operands
71 // const buffer reference, SRCx_SEL contains index
72 def ALU_CONST : R600Reg<"CBuf", 0>;
73 // interpolation param reference, SRCx_SEL contains index
74 def ALU_PARAM : R600Reg<"Param", 0>;
76 let isAllocatable = 0 in {
78 // XXX: Only use the X channel, until we support wider stack widths
79 def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>;
81 } // End isAllocatable = 0
83 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
84 (add (sequence "T%u_X", 0, 127), AR_X)>;
86 def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
87 (add (sequence "T%u_Y", 0, 127))>;
89 def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
90 (add (sequence "T%u_Z", 0, 127))>;
92 def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,
93 (add (sequence "T%u_W", 0, 127))>;
95 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
96 (interleave R600_TReg32_X, R600_TReg32_Y,
97 R600_TReg32_Z, R600_TReg32_W)>;
99 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
103 ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF,
107 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
108 PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>;
110 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
113 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
114 (add (sequence "T%u_XYZW", 0, 127))> {
118 //===----------------------------------------------------------------------===//
119 // Register classes for indirect addressing
120 //===----------------------------------------------------------------------===//
122 // Super register for all the Indirect Registers. This register class is used
123 // by the REG_SEQUENCE instruction to specify the registers to use for direct
124 // reads / writes which may be written / read by an indirect address.
125 class IndirectSuper<string n, list<Register> subregs> :
126 RegisterWithSubRegs<n, subregs> {
127 let Namespace = "AMDGPU";
129 [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
130 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15];
133 def IndirectSuperReg : IndirectSuper<"Indirect",
134 [TRegMem0_X, TRegMem1_X, TRegMem2_X, TRegMem3_X, TRegMem4_X, TRegMem5_X,
135 TRegMem6_X, TRegMem7_X, TRegMem8_X, TRegMem9_X, TRegMem10_X, TRegMem11_X,
136 TRegMem12_X, TRegMem13_X, TRegMem14_X, TRegMem15_X]
139 def IndirectReg : RegisterClass<"AMDGPU", [f32, i32], 32, (add IndirectSuperReg)>;
141 // This register class defines the registers that are the storage units for
142 // the "Indirect Addressing" pseudo memory space.
143 // XXX: Only use the X channel, until we support wider stack widths
144 def TRegMem : RegisterClass<"AMDGPU", [f32, i32], 32,
145 (add (sequence "TRegMem%u_X", 0, 16))