1 //===-- SIFixSGPRLiveRanges.cpp - Fix SGPR live ranges ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// SALU instructions ignore control flow, so we need to modify the live ranges
12 /// of the registers they define in some cases.
14 /// The main case we need to handle is when a def is used in one side of a
15 /// branch and not another. For example:
26 /// Here we need the register allocator to avoid assigning any of the defs
27 /// inside of the IF to the same register as %def. In traditional live
28 /// interval analysis %def is not live inside the IF branch, however, since
29 /// SALU instructions inside of IF will be executed even if the branch is not
30 /// taken, there is the chance that one of the instructions will overwrite the
31 /// value of %def, so the use in ELSE will see the wrong value.
33 /// The strategy we use for solving this is to add an extra use after the ENDIF:
45 /// Adding this use will make the def live thoughout the IF branch, which is
49 #include "SIInstrInfo.h"
50 #include "SIRegisterInfo.h"
51 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
52 #include "llvm/CodeGen/MachineFunctionPass.h"
53 #include "llvm/CodeGen/MachineInstrBuilder.h"
54 #include "llvm/CodeGen/MachinePostDominators.h"
55 #include "llvm/CodeGen/MachineRegisterInfo.h"
56 #include "llvm/Support/Debug.h"
57 #include "llvm/Target/TargetMachine.h"
61 #define DEBUG_TYPE "si-fix-sgpr-live-ranges"
65 class SIFixSGPRLiveRanges : public MachineFunctionPass {
70 SIFixSGPRLiveRanges() : MachineFunctionPass(ID) {
71 initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry());
74 bool runOnMachineFunction(MachineFunction &MF) override;
76 const char *getPassName() const override {
77 return "SI Fix SGPR live ranges";
80 void getAnalysisUsage(AnalysisUsage &AU) const override {
81 AU.addRequired<LiveIntervals>();
82 AU.addRequired<MachinePostDominatorTree>();
84 MachineFunctionPass::getAnalysisUsage(AU);
88 } // End anonymous namespace.
90 INITIALIZE_PASS_BEGIN(SIFixSGPRLiveRanges, DEBUG_TYPE,
91 "SI Fix SGPR Live Ranges", false, false)
92 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
93 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
94 INITIALIZE_PASS_END(SIFixSGPRLiveRanges, DEBUG_TYPE,
95 "SI Fix SGPR Live Ranges", false, false)
97 char SIFixSGPRLiveRanges::ID = 0;
99 char &llvm::SIFixSGPRLiveRangesID = SIFixSGPRLiveRanges::ID;
101 FunctionPass *llvm::createSIFixSGPRLiveRangesPass() {
102 return new SIFixSGPRLiveRanges();
105 bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
106 MachineRegisterInfo &MRI = MF.getRegInfo();
107 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
108 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
109 MF.getSubtarget().getRegisterInfo());
110 LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
111 MachinePostDominatorTree *PDT = &getAnalysis<MachinePostDominatorTree>();
112 std::vector<std::pair<unsigned, LiveRange *>> SGPRLiveRanges;
114 // First pass, collect all live intervals for SGPRs
115 for (const MachineBasicBlock &MBB : MF) {
116 for (const MachineInstr &MI : MBB) {
117 for (const MachineOperand &MO : MI.defs()) {
120 unsigned Def = MO.getReg();
121 if (TargetRegisterInfo::isVirtualRegister(Def)) {
122 if (TRI->isSGPRClass(MRI.getRegClass(Def)))
123 SGPRLiveRanges.push_back(
124 std::make_pair(Def, &LIS->getInterval(Def)));
125 } else if (TRI->isSGPRClass(TRI->getPhysRegClass(Def))) {
126 SGPRLiveRanges.push_back(
127 std::make_pair(Def, &LIS->getRegUnit(Def)));
133 // Second pass fix the intervals
134 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
136 MachineBasicBlock &MBB = *BI;
137 if (MBB.succ_size() < 2)
140 // We have structured control flow, so number of succesors should be two.
141 assert(MBB.succ_size() == 2);
142 MachineBasicBlock *SuccA = *MBB.succ_begin();
143 MachineBasicBlock *SuccB = *(++MBB.succ_begin());
144 MachineBasicBlock *NCD = PDT->findNearestCommonDominator(SuccA, SuccB);
149 MachineBasicBlock::iterator NCDTerm = NCD->getFirstTerminator();
151 if (NCDTerm != NCD->end() && NCDTerm->getOpcode() == AMDGPU::SI_ELSE) {
152 assert(NCD->succ_size() == 2);
153 // We want to make sure we insert the Use after the ENDIF, not after
155 NCD = PDT->findNearestCommonDominator(*NCD->succ_begin(),
156 *(++NCD->succ_begin()));
158 assert(SuccA && SuccB);
159 for (std::pair<unsigned, LiveRange*> RegLR : SGPRLiveRanges) {
160 unsigned Reg = RegLR.first;
161 LiveRange *LR = RegLR.second;
163 // FIXME: We could be smarter here. If the register is Live-In to
164 // one block, but the other doesn't have any SGPR defs, then there
165 // won't be a conflict. Also, if the branch decision is based on
166 // a value in an SGPR, then there will be no conflict.
167 bool LiveInToA = LIS->isLiveInToMBB(*LR, SuccA);
168 bool LiveInToB = LIS->isLiveInToMBB(*LR, SuccB);
170 if ((!LiveInToA && !LiveInToB) ||
171 (LiveInToA && LiveInToB))
174 // This interval is live in to one successor, but not the other, so
175 // we need to update its range so it is live in to both.
176 DEBUG(dbgs() << "Possible SGPR conflict detected " << " in " << *LR <<
177 " BB#" << SuccA->getNumber() << ", BB#" <<
178 SuccB->getNumber() <<
179 " with NCD = " << NCD->getNumber() << '\n');
181 // FIXME: Need to figure out how to update LiveRange here so this pass
182 // will be able to preserve LiveInterval analysis.
183 BuildMI(*NCD, NCD->getFirstNonPHI(), DebugLoc(),
184 TII->get(AMDGPU::SGPR_USE))
185 .addReg(Reg, RegState::Implicit);
186 DEBUG(NCD->getFirstNonPHI()->dump());