1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUIntrinsicInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/ADT/SmallString.h"
38 SITargetLowering::SITargetLowering(TargetMachine &TM) :
39 AMDGPUTargetLowering(TM) {
40 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
41 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
43 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
44 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
46 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
47 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
49 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
50 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
51 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
53 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
54 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
56 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
57 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
59 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
60 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
62 computeRegisterProperties();
65 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
66 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
67 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
68 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
69 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
70 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
72 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
73 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
74 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
75 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
76 setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
77 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
79 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
80 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
81 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
82 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
84 setOperationAction(ISD::ADD, MVT::i32, Legal);
85 setOperationAction(ISD::ADDC, MVT::i32, Legal);
86 setOperationAction(ISD::ADDE, MVT::i32, Legal);
87 setOperationAction(ISD::SUBC, MVT::i32, Legal);
88 setOperationAction(ISD::SUBE, MVT::i32, Legal);
90 setOperationAction(ISD::FSIN, MVT::f32, Custom);
91 setOperationAction(ISD::FCOS, MVT::f32, Custom);
93 // We need to custom lower vector stores from local memory
94 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
95 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
96 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
98 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
99 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
101 setOperationAction(ISD::STORE, MVT::i1, Custom);
102 setOperationAction(ISD::STORE, MVT::i32, Custom);
103 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
104 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
106 setOperationAction(ISD::SELECT, MVT::f32, Promote);
107 AddPromotedToType(ISD::SELECT, MVT::f32, MVT::i32);
108 setOperationAction(ISD::SELECT, MVT::i64, Custom);
109 setOperationAction(ISD::SELECT, MVT::f64, Promote);
110 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
112 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
113 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
114 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
115 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
117 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
118 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
128 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
134 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
136 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
137 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
138 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
139 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
141 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
142 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
145 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
146 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
147 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
148 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
149 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
152 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
153 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
154 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
156 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
157 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
158 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
159 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
160 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
162 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
163 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
164 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
165 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
166 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
167 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
169 setOperationAction(ISD::LOAD, MVT::i1, Custom);
171 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
172 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
173 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
175 // These should use UDIVREM, so set them to expand
176 setOperationAction(ISD::UDIV, MVT::i64, Expand);
177 setOperationAction(ISD::UREM, MVT::i64, Expand);
179 // We only support LOAD/STORE and vector manipulation ops for vectors
180 // with > 4 elements.
182 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
185 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
186 setOperationAction(ISD::SELECT, MVT::i1, Promote);
188 for (MVT VT : VecTypes) {
189 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
193 case ISD::BUILD_VECTOR:
195 case ISD::EXTRACT_VECTOR_ELT:
196 case ISD::INSERT_VECTOR_ELT:
197 case ISD::INSERT_SUBVECTOR:
198 case ISD::EXTRACT_SUBVECTOR:
200 case ISD::CONCAT_VECTORS:
201 setOperationAction(Op, VT, Custom);
204 setOperationAction(Op, VT, Expand);
210 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
211 MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
212 setOperationAction(ISD::FTRUNC, VT, Expand);
213 setOperationAction(ISD::FCEIL, VT, Expand);
214 setOperationAction(ISD::FFLOOR, VT, Expand);
217 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
218 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
219 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
220 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
221 setOperationAction(ISD::FRINT, MVT::f64, Legal);
224 setOperationAction(ISD::FDIV, MVT::f32, Custom);
226 setTargetDAGCombine(ISD::FADD);
227 setTargetDAGCombine(ISD::FSUB);
228 setTargetDAGCombine(ISD::SELECT_CC);
229 setTargetDAGCombine(ISD::SETCC);
231 setTargetDAGCombine(ISD::UINT_TO_FP);
233 // All memory operations. Some folding on the pointer operand is done to help
234 // matching the constant offsets in the addressing modes.
235 setTargetDAGCombine(ISD::LOAD);
236 setTargetDAGCombine(ISD::STORE);
237 setTargetDAGCombine(ISD::ATOMIC_LOAD);
238 setTargetDAGCombine(ISD::ATOMIC_STORE);
239 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
240 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
241 setTargetDAGCombine(ISD::ATOMIC_SWAP);
242 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
243 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
244 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
245 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
246 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
247 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
248 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
249 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
250 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
251 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
253 setSchedulingPreference(Sched::RegPressure);
256 //===----------------------------------------------------------------------===//
257 // TargetLowering queries
258 //===----------------------------------------------------------------------===//
260 // FIXME: This really needs an address space argument. The immediate offset
261 // size is different for different sets of memory instruction sets.
263 // The single offset DS instructions have a 16-bit unsigned byte offset.
265 // MUBUF / MTBUF have a 12-bit unsigned byte offset, and additionally can do r +
266 // r + i with addr64. 32-bit has more addressing mode options. Depending on the
267 // resource constant, it can also do (i64 r0) + (i32 r1) * (i14 i).
269 // SMRD instructions have an 8-bit, dword offset.
271 bool SITargetLowering::isLegalAddressingMode(const AddrMode &AM,
273 // No global is ever allowed as a base.
277 // Allow a 16-bit unsigned immediate field, since this is what DS instructions
279 if (!isUInt<16>(AM.BaseOffs))
284 case 0: // "r+i" or just "i", depending on HasBaseReg.
287 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
289 // Otherwise we have r+r or r+i.
292 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
296 default: // Don't allow n * r
303 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
306 bool *IsFast) const {
310 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
311 // which isn't a simple VT.
312 if (!VT.isSimple() || VT == MVT::Other)
315 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
316 // see what for specifically. The wording everywhere else seems to be the
319 // XXX - The only mention I see of this in the ISA manual is for LDS direct
320 // reads the "byte address and must be dword aligned". Is it also true for the
321 // normal loads and stores?
322 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
323 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
324 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
325 // with adjacent offsets.
326 return Align % 4 == 0;
329 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
330 // byte-address are ignored, thus forcing Dword alignment.
331 // This applies to private, global, and constant memory.
334 return VT.bitsGT(MVT::i32);
337 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
338 unsigned SrcAlign, bool IsMemset,
341 MachineFunction &MF) const {
342 // FIXME: Should account for address space here.
344 // The default fallback uses the private pointer size as a guess for a type to
345 // use. Make sure we switch these to 64-bit accesses.
347 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
350 if (Size >= 8 && DstAlign >= 4)
357 TargetLoweringBase::LegalizeTypeAction
358 SITargetLowering::getPreferredVectorAction(EVT VT) const {
359 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
360 return TypeSplitVector;
362 return TargetLoweringBase::getPreferredVectorAction(VT);
365 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
367 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
368 getTargetMachine().getSubtargetImpl()->getInstrInfo());
369 return TII->isInlineConstant(Imm);
372 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
373 SDLoc SL, SDValue Chain,
374 unsigned Offset, bool Signed) const {
375 const DataLayout *DL = getDataLayout();
376 MachineFunction &MF = DAG.getMachineFunction();
377 const SIRegisterInfo *TRI =
378 static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
379 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
381 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
383 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
384 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
385 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
386 MRI.getLiveInVirtReg(InputPtrReg), MVT::i64);
387 SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
388 DAG.getConstant(Offset, MVT::i64));
389 SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
390 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
392 return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD,
393 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
395 true, // isNonTemporal
397 DL->getABITypeAlignment(Ty)); // Alignment
400 SDValue SITargetLowering::LowerFormalArguments(
402 CallingConv::ID CallConv,
404 const SmallVectorImpl<ISD::InputArg> &Ins,
405 SDLoc DL, SelectionDAG &DAG,
406 SmallVectorImpl<SDValue> &InVals) const {
408 const TargetMachine &TM = getTargetMachine();
409 const SIRegisterInfo *TRI =
410 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
412 MachineFunction &MF = DAG.getMachineFunction();
413 FunctionType *FType = MF.getFunction()->getFunctionType();
414 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
416 assert(CallConv == CallingConv::C);
418 SmallVector<ISD::InputArg, 16> Splits;
419 BitVector Skipped(Ins.size());
421 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
422 const ISD::InputArg &Arg = Ins[i];
424 // First check if it's a PS input addr
425 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
426 !Arg.Flags.isByVal()) {
428 assert((PSInputNum <= 15) && "Too many PS inputs!");
431 // We can savely skip PS inputs
437 Info->PSInputAddr |= 1 << PSInputNum++;
440 // Second split vertices into their elements
441 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
442 ISD::InputArg NewArg = Arg;
443 NewArg.Flags.setSplit();
444 NewArg.VT = Arg.VT.getVectorElementType();
446 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
447 // three or five element vertex only needs three or five registers,
448 // NOT four or eigth.
449 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
450 unsigned NumElements = ParamType->getVectorNumElements();
452 for (unsigned j = 0; j != NumElements; ++j) {
453 Splits.push_back(NewArg);
454 NewArg.PartOffset += NewArg.VT.getStoreSize();
457 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
458 Splits.push_back(Arg);
462 SmallVector<CCValAssign, 16> ArgLocs;
463 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
466 // At least one interpolation mode must be enabled or else the GPU will hang.
467 if (Info->getShaderType() == ShaderType::PIXEL &&
468 (Info->PSInputAddr & 0x7F) == 0) {
469 Info->PSInputAddr |= 1;
470 CCInfo.AllocateReg(AMDGPU::VGPR0);
471 CCInfo.AllocateReg(AMDGPU::VGPR1);
474 // The pointer to the list of arguments is stored in SGPR0, SGPR1
475 // The pointer to the scratch buffer is stored in SGPR2, SGPR3
476 if (Info->getShaderType() == ShaderType::COMPUTE) {
477 Info->NumUserSGPRs = 4;
479 unsigned InputPtrReg =
480 TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
481 unsigned InputPtrRegLo =
482 TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0);
483 unsigned InputPtrRegHi =
484 TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1);
486 unsigned ScratchPtrReg =
487 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
488 unsigned ScratchPtrRegLo =
489 TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0);
490 unsigned ScratchPtrRegHi =
491 TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1);
493 CCInfo.AllocateReg(InputPtrRegLo);
494 CCInfo.AllocateReg(InputPtrRegHi);
495 CCInfo.AllocateReg(ScratchPtrRegLo);
496 CCInfo.AllocateReg(ScratchPtrRegHi);
497 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
498 MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
501 if (Info->getShaderType() == ShaderType::COMPUTE) {
502 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
506 AnalyzeFormalArguments(CCInfo, Splits);
508 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
510 const ISD::InputArg &Arg = Ins[i];
512 InVals.push_back(DAG.getUNDEF(Arg.VT));
516 CCValAssign &VA = ArgLocs[ArgIdx++];
517 EVT VT = VA.getLocVT();
521 EVT MemVT = Splits[i].VT;
522 const unsigned Offset = 36 + VA.getLocMemOffset();
523 // The first 36 bytes of the input buffer contains information about
524 // thread group and global sizes.
525 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
526 Offset, Ins[i].Flags.isSExt());
528 const PointerType *ParamTy =
529 dyn_cast<PointerType>(FType->getParamType(Ins[i].OrigArgIndex));
530 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
531 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
532 // On SI local pointers are just offsets into LDS, so they are always
533 // less than 16-bits. On CI and newer they could potentially be
534 // real pointers, so we can't guarantee their size.
535 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
536 DAG.getValueType(MVT::i16));
539 InVals.push_back(Arg);
540 Info->ABIArgOffset = Offset + MemVT.getStoreSize();
543 assert(VA.isRegLoc() && "Parameter must be in a register!");
545 unsigned Reg = VA.getLocReg();
547 if (VT == MVT::i64) {
548 // For now assume it is a pointer
549 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
550 &AMDGPU::SReg_64RegClass);
551 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
552 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
556 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
558 Reg = MF.addLiveIn(Reg, RC);
559 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
561 if (Arg.VT.isVector()) {
563 // Build a vector from the registers
564 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
565 unsigned NumElements = ParamType->getVectorNumElements();
567 SmallVector<SDValue, 4> Regs;
569 for (unsigned j = 1; j != NumElements; ++j) {
570 Reg = ArgLocs[ArgIdx++].getLocReg();
571 Reg = MF.addLiveIn(Reg, RC);
572 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
575 // Fill up the missing vector elements
576 NumElements = Arg.VT.getVectorNumElements() - NumElements;
577 for (unsigned j = 0; j != NumElements; ++j)
578 Regs.push_back(DAG.getUNDEF(VT));
580 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
584 InVals.push_back(Val);
589 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
590 MachineInstr * MI, MachineBasicBlock * BB) const {
592 MachineBasicBlock::iterator I = *MI;
593 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
594 getTargetMachine().getSubtargetImpl()->getInstrInfo());
595 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
597 switch (MI->getOpcode()) {
599 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
600 case AMDGPU::BRANCH: return BB;
601 case AMDGPU::SI_ADDR64_RSRC: {
602 unsigned SuperReg = MI->getOperand(0).getReg();
603 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
604 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
605 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
606 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
607 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
608 .addOperand(MI->getOperand(1));
609 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
611 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
612 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
613 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
615 .addImm(AMDGPU::sub0)
617 .addImm(AMDGPU::sub1);
618 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
620 .addImm(AMDGPU::sub0_sub1)
622 .addImm(AMDGPU::sub2_sub3);
623 MI->eraseFromParent();
626 case AMDGPU::SI_BUFFER_RSRC: {
627 unsigned SuperReg = MI->getOperand(0).getReg();
629 for (unsigned i = 0, e = 4; i < e; ++i) {
630 MachineOperand &Arg = MI->getOperand(i + 1);
633 Args[i] = Arg.getReg();
638 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
639 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), Reg)
640 .addImm(Arg.getImm());
643 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE),
646 .addImm(AMDGPU::sub0)
648 .addImm(AMDGPU::sub1)
650 .addImm(AMDGPU::sub2)
652 .addImm(AMDGPU::sub3);
653 MI->eraseFromParent();
656 case AMDGPU::V_SUB_F64: {
657 unsigned DestReg = MI->getOperand(0).getReg();
658 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
659 .addImm(0) // SRC0 modifiers
660 .addReg(MI->getOperand(1).getReg())
661 .addImm(1) // SRC1 modifiers
662 .addReg(MI->getOperand(2).getReg())
665 MI->eraseFromParent();
668 case AMDGPU::SI_RegisterStorePseudo: {
669 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
670 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
671 MachineInstrBuilder MIB =
672 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
674 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
675 MIB.addOperand(MI->getOperand(i));
677 MI->eraseFromParent();
680 case AMDGPU::FCLAMP_SI: {
681 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
682 getTargetMachine().getSubtargetImpl()->getInstrInfo());
683 DebugLoc DL = MI->getDebugLoc();
684 unsigned DestReg = MI->getOperand(0).getReg();
685 BuildMI(*BB, I, DL, TII->get(AMDGPU::V_ADD_F32_e64), DestReg)
686 .addImm(0) // SRC0 modifiers
687 .addOperand(MI->getOperand(1))
688 .addImm(0) // SRC1 modifiers
692 MI->eraseFromParent();
698 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
699 if (!VT.isVector()) {
702 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
705 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
709 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
710 VT = VT.getScalarType();
715 switch (VT.getSimpleVT().SimpleTy) {
717 return false; /* There is V_MAD_F32 for f32 */
727 //===----------------------------------------------------------------------===//
728 // Custom DAG Lowering Operations
729 //===----------------------------------------------------------------------===//
731 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
732 switch (Op.getOpcode()) {
733 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
734 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
735 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
737 SDValue Result = LowerLOAD(Op, DAG);
738 assert((!Result.getNode() ||
739 Result.getNode()->getNumValues() == 2) &&
740 "Load should return a value and a chain");
746 return LowerTrig(Op, DAG);
747 case ISD::SELECT: return LowerSELECT(Op, DAG);
748 case ISD::FDIV: return LowerFDIV(Op, DAG);
749 case ISD::STORE: return LowerSTORE(Op, DAG);
750 case ISD::GlobalAddress: {
751 MachineFunction &MF = DAG.getMachineFunction();
752 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
753 return LowerGlobalAddress(MFI, Op, DAG);
755 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
756 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
761 /// \brief Helper function for LowerBRCOND
762 static SDNode *findUser(SDValue Value, unsigned Opcode) {
764 SDNode *Parent = Value.getNode();
765 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
768 if (I.getUse().get() != Value)
771 if (I->getOpcode() == Opcode)
777 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
779 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
780 unsigned FrameIndex = FINode->getIndex();
782 return DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
785 /// This transforms the control flow intrinsics to get the branch destination as
786 /// last parameter, also switches branch target with BR if the need arise
787 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
788 SelectionDAG &DAG) const {
792 SDNode *Intr = BRCOND.getOperand(1).getNode();
793 SDValue Target = BRCOND.getOperand(2);
794 SDNode *BR = nullptr;
796 if (Intr->getOpcode() == ISD::SETCC) {
797 // As long as we negate the condition everything is fine
798 SDNode *SetCC = Intr;
799 assert(SetCC->getConstantOperandVal(1) == 1);
800 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
802 Intr = SetCC->getOperand(0).getNode();
805 // Get the target from BR if we don't negate the condition
806 BR = findUser(BRCOND, ISD::BR);
807 Target = BR->getOperand(1);
810 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
812 // Build the result and
813 SmallVector<EVT, 4> Res;
814 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
815 Res.push_back(Intr->getValueType(i));
817 // operands of the new intrinsic call
818 SmallVector<SDValue, 4> Ops;
819 Ops.push_back(BRCOND.getOperand(0));
820 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
821 Ops.push_back(Intr->getOperand(i));
822 Ops.push_back(Target);
824 // build the new intrinsic call
825 SDNode *Result = DAG.getNode(
826 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
827 DAG.getVTList(Res), Ops).getNode();
830 // Give the branch instruction our target
835 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
836 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
837 BR = NewBR.getNode();
840 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
842 // Copy the intrinsic results to registers
843 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
844 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
848 Chain = DAG.getCopyToReg(
850 CopyToReg->getOperand(1),
851 SDValue(Result, i - 1),
854 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
857 // Remove the old intrinsic from the chain
858 DAG.ReplaceAllUsesOfValueWith(
859 SDValue(Intr, Intr->getNumValues() - 1),
860 Intr->getOperand(0));
865 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
867 SelectionDAG &DAG) const {
868 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
870 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
871 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
874 const GlobalValue *GV = GSD->getGlobal();
875 MVT PtrVT = getPointerTy(GSD->getAddressSpace());
877 SDValue Ptr = DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT);
878 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
880 SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
881 DAG.getConstant(0, MVT::i32));
882 SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
883 DAG.getConstant(1, MVT::i32));
885 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
887 SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue),
888 PtrHi, DAG.getConstant(0, MVT::i32),
889 SDValue(Lo.getNode(), 1));
890 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
893 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
894 SelectionDAG &DAG) const {
895 MachineFunction &MF = DAG.getMachineFunction();
896 const SIRegisterInfo *TRI =
897 static_cast<const SIRegisterInfo*>(MF.getSubtarget().getRegisterInfo());
899 EVT VT = Op.getValueType();
901 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
903 switch (IntrinsicID) {
904 case Intrinsic::r600_read_ngroups_x:
905 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
906 SI::KernelInputOffsets::NGROUPS_X, false);
907 case Intrinsic::r600_read_ngroups_y:
908 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
909 SI::KernelInputOffsets::NGROUPS_Y, false);
910 case Intrinsic::r600_read_ngroups_z:
911 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
912 SI::KernelInputOffsets::NGROUPS_Z, false);
913 case Intrinsic::r600_read_global_size_x:
914 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
915 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
916 case Intrinsic::r600_read_global_size_y:
917 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
918 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
919 case Intrinsic::r600_read_global_size_z:
920 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
921 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
922 case Intrinsic::r600_read_local_size_x:
923 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
924 SI::KernelInputOffsets::LOCAL_SIZE_X, false);
925 case Intrinsic::r600_read_local_size_y:
926 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
927 SI::KernelInputOffsets::LOCAL_SIZE_Y, false);
928 case Intrinsic::r600_read_local_size_z:
929 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
930 SI::KernelInputOffsets::LOCAL_SIZE_Z, false);
932 case Intrinsic::AMDGPU_read_workdim:
933 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
934 MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset,
937 case Intrinsic::r600_read_tgid_x:
938 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
939 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT);
940 case Intrinsic::r600_read_tgid_y:
941 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
942 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Y), VT);
943 case Intrinsic::r600_read_tgid_z:
944 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
945 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Z), VT);
946 case Intrinsic::r600_read_tidig_x:
947 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
948 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_X), VT);
949 case Intrinsic::r600_read_tidig_y:
950 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
951 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Y), VT);
952 case Intrinsic::r600_read_tidig_z:
953 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
954 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Z), VT);
955 case AMDGPUIntrinsic::SI_load_const: {
961 MachineMemOperand *MMO = MF.getMachineMemOperand(
962 MachinePointerInfo(),
963 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
964 VT.getStoreSize(), 4);
965 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
966 Op->getVTList(), Ops, VT, MMO);
968 case AMDGPUIntrinsic::SI_sample:
969 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
970 case AMDGPUIntrinsic::SI_sampleb:
971 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
972 case AMDGPUIntrinsic::SI_sampled:
973 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
974 case AMDGPUIntrinsic::SI_samplel:
975 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
976 case AMDGPUIntrinsic::SI_vs_load_input:
977 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
982 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
986 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
987 SelectionDAG &DAG) const {
988 MachineFunction &MF = DAG.getMachineFunction();
989 SDValue Chain = Op.getOperand(0);
990 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
992 switch (IntrinsicID) {
993 case AMDGPUIntrinsic::SI_tbuffer_store: {
1012 EVT VT = Op.getOperand(3).getValueType();
1014 MachineMemOperand *MMO = MF.getMachineMemOperand(
1015 MachinePointerInfo(),
1016 MachineMemOperand::MOStore,
1017 VT.getStoreSize(), 4);
1018 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
1019 Op->getVTList(), Ops, VT, MMO);
1026 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1028 LoadSDNode *Load = cast<LoadSDNode>(Op);
1030 if (Op.getValueType().isVector()) {
1031 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
1032 "Custom lowering for non-i32 vectors hasn't been implemented.");
1033 unsigned NumElements = Op.getValueType().getVectorNumElements();
1034 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
1035 switch (Load->getAddressSpace()) {
1037 case AMDGPUAS::GLOBAL_ADDRESS:
1038 case AMDGPUAS::PRIVATE_ADDRESS:
1039 // v4 loads are supported for private and global memory.
1040 if (NumElements <= 4)
1043 case AMDGPUAS::LOCAL_ADDRESS:
1044 return ScalarizeVectorLoad(Op, DAG);
1048 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1051 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1053 SelectionDAG &DAG) const {
1054 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
1060 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1061 if (Op.getValueType() != MVT::i64)
1065 SDValue Cond = Op.getOperand(0);
1067 SDValue Zero = DAG.getConstant(0, MVT::i32);
1068 SDValue One = DAG.getConstant(1, MVT::i32);
1070 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1071 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1073 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1074 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1076 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1078 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1079 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1081 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1083 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1084 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1087 // Catch division cases where we can use shortcuts with rcp and rsq
1089 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1091 SDValue LHS = Op.getOperand(0);
1092 SDValue RHS = Op.getOperand(1);
1093 EVT VT = Op.getValueType();
1094 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1096 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1097 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1098 CLHS->isExactlyValue(1.0)) {
1099 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1100 // the CI documentation has a worst case error of 1 ulp.
1101 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1102 // use it as long as we aren't trying to use denormals.
1104 // 1.0 / sqrt(x) -> rsq(x)
1106 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1107 // error seems really high at 2^29 ULP.
1108 if (RHS.getOpcode() == ISD::FSQRT)
1109 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1111 // 1.0 / x -> rcp(x)
1112 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1117 // Turn into multiply by the reciprocal.
1118 // x / y -> x * (1.0 / y)
1119 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1120 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip);
1126 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1127 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1128 if (FastLowered.getNode())
1131 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1132 // selection error for now rather than do something incorrect.
1133 if (Subtarget->hasFP32Denormals())
1137 SDValue LHS = Op.getOperand(0);
1138 SDValue RHS = Op.getOperand(1);
1140 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1142 const APFloat K0Val(BitsToFloat(0x6f800000));
1143 const SDValue K0 = DAG.getConstantFP(K0Val, MVT::f32);
1145 const APFloat K1Val(BitsToFloat(0x2f800000));
1146 const SDValue K1 = DAG.getConstantFP(K1Val, MVT::f32);
1148 const SDValue One = DAG.getTargetConstantFP(1.0, MVT::f32);
1150 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
1152 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1154 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1156 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1158 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1160 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1162 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1165 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1169 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1170 EVT VT = Op.getValueType();
1173 return LowerFDIV32(Op, DAG);
1176 return LowerFDIV64(Op, DAG);
1178 llvm_unreachable("Unexpected type for fdiv");
1181 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1183 StoreSDNode *Store = cast<StoreSDNode>(Op);
1184 EVT VT = Store->getMemoryVT();
1186 // These stores are legal.
1187 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
1188 VT.isVector() && VT.getVectorNumElements() == 2 &&
1189 VT.getVectorElementType() == MVT::i32)
1192 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1193 if (VT.isVector() && VT.getVectorNumElements() > 4)
1194 return ScalarizeVectorStore(Op, DAG);
1198 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1202 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1203 return ScalarizeVectorStore(Op, DAG);
1206 return DAG.getTruncStore(Store->getChain(), DL,
1207 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1208 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1213 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1214 EVT VT = Op.getValueType();
1215 SDValue Arg = Op.getOperand(0);
1216 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
1217 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
1218 DAG.getConstantFP(0.5 / M_PI, VT)));
1220 switch (Op.getOpcode()) {
1222 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1224 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1226 llvm_unreachable("Wrong trig opcode");
1230 //===----------------------------------------------------------------------===//
1231 // Custom DAG optimizations
1232 //===----------------------------------------------------------------------===//
1234 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1235 DAGCombinerInfo &DCI) {
1236 EVT VT = N->getValueType(0);
1237 EVT ScalarVT = VT.getScalarType();
1238 if (ScalarVT != MVT::f32)
1241 SelectionDAG &DAG = DCI.DAG;
1244 SDValue Src = N->getOperand(0);
1245 EVT SrcVT = Src.getValueType();
1247 // TODO: We could try to match extracting the higher bytes, which would be
1248 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1249 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1250 // about in practice.
1251 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1252 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1253 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1254 DCI.AddToWorklist(Cvt.getNode());
1259 // We are primarily trying to catch operations on illegal vector types
1260 // before they are expanded.
1261 // For scalars, we can use the more flexible method of checking masked bits
1262 // after legalization.
1263 if (!DCI.isBeforeLegalize() ||
1264 !SrcVT.isVector() ||
1265 SrcVT.getVectorElementType() != MVT::i8) {
1269 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1271 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1273 unsigned NElts = SrcVT.getVectorNumElements();
1274 if (!SrcVT.isSimple() && NElts != 3)
1277 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1278 // prevent a mess from expanding to v4i32 and repacking.
1279 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1280 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1281 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1282 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1284 LoadSDNode *Load = cast<LoadSDNode>(Src);
1285 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1289 Load->getMemOperand());
1291 // Make sure successors of the original load stay after it by updating
1292 // them to use the new Chain.
1293 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1295 SmallVector<SDValue, 4> Elts;
1296 if (RegVT.isVector())
1297 DAG.ExtractVectorElements(NewLoad, Elts);
1299 Elts.push_back(NewLoad);
1301 SmallVector<SDValue, 4> Ops;
1303 unsigned EltIdx = 0;
1304 for (SDValue Elt : Elts) {
1305 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1306 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1307 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1308 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1309 DCI.AddToWorklist(Cvt.getNode());
1316 assert(Ops.size() == NElts);
1318 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1324 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
1326 // This is a variant of
1327 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
1329 // The normal DAG combiner will do this, but only if the add has one use since
1330 // that would increase the number of instructions.
1332 // This prevents us from seeing a constant offset that can be folded into a
1333 // memory instruction's addressing mode. If we know the resulting add offset of
1334 // a pointer can be folded into an addressing offset, we can replace the pointer
1335 // operand with the add of new constant offset. This eliminates one of the uses,
1336 // and may allow the remaining use to also be simplified.
1338 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1340 DAGCombinerInfo &DCI) const {
1341 SDValue N0 = N->getOperand(0);
1342 SDValue N1 = N->getOperand(1);
1344 if (N0.getOpcode() != ISD::ADD)
1347 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
1351 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1355 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1356 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1358 // If the resulting offset is too large, we can't fold it into the addressing
1360 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
1361 if (!TII->canFoldOffset(Offset.getZExtValue(), AddrSpace))
1364 SelectionDAG &DAG = DCI.DAG;
1366 EVT VT = N->getValueType(0);
1368 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
1369 SDValue COffset = DAG.getConstant(Offset, MVT::i32);
1371 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
1374 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1375 DAGCombinerInfo &DCI) const {
1376 SelectionDAG &DAG = DCI.DAG;
1378 EVT VT = N->getValueType(0);
1380 switch (N->getOpcode()) {
1381 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1383 SDValue Arg0 = N->getOperand(0);
1384 SDValue Arg1 = N->getOperand(1);
1385 SDValue CC = N->getOperand(2);
1386 ConstantSDNode * C = nullptr;
1387 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1389 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1391 && Arg0.getOpcode() == ISD::SIGN_EXTEND
1392 && Arg0.getOperand(0).getValueType() == MVT::i1
1393 && (C = dyn_cast<ConstantSDNode>(Arg1))
1395 && CCOp == ISD::SETNE) {
1396 return SimplifySetCC(VT, Arg0.getOperand(0),
1397 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1402 case AMDGPUISD::CVT_F32_UBYTE0:
1403 case AMDGPUISD::CVT_F32_UBYTE1:
1404 case AMDGPUISD::CVT_F32_UBYTE2:
1405 case AMDGPUISD::CVT_F32_UBYTE3: {
1406 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1408 SDValue Src = N->getOperand(0);
1409 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1411 APInt KnownZero, KnownOne;
1412 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1413 !DCI.isBeforeLegalizeOps());
1414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1415 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1416 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1417 DCI.CommitTargetLoweringOpt(TLO);
1423 case ISD::UINT_TO_FP: {
1424 return performUCharToFloatCombine(N, DCI);
1427 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1430 EVT VT = N->getValueType(0);
1434 SDValue LHS = N->getOperand(0);
1435 SDValue RHS = N->getOperand(1);
1437 // These should really be instruction patterns, but writing patterns with
1438 // source modiifiers is a pain.
1440 // fadd (fadd (a, a), b) -> mad 2.0, a, b
1441 if (LHS.getOpcode() == ISD::FADD) {
1442 SDValue A = LHS.getOperand(0);
1443 if (A == LHS.getOperand(1)) {
1444 const SDValue Two = DAG.getTargetConstantFP(2.0, MVT::f32);
1445 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, RHS);
1449 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
1450 if (RHS.getOpcode() == ISD::FADD) {
1451 SDValue A = RHS.getOperand(0);
1452 if (A == RHS.getOperand(1)) {
1453 const SDValue Two = DAG.getTargetConstantFP(2.0, MVT::f32);
1454 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, LHS);
1461 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1464 EVT VT = N->getValueType(0);
1466 // Try to get the fneg to fold into the source modifier. This undoes generic
1467 // DAG combines and folds them into the mad.
1468 if (VT == MVT::f32) {
1469 SDValue LHS = N->getOperand(0);
1470 SDValue RHS = N->getOperand(1);
1472 if (LHS.getOpcode() == ISD::FMUL) {
1473 // (fsub (fmul a, b), c) -> mad a, b, (fneg c)
1475 SDValue A = LHS.getOperand(0);
1476 SDValue B = LHS.getOperand(1);
1477 SDValue C = DAG.getNode(ISD::FNEG, DL, VT, RHS);
1479 return DAG.getNode(AMDGPUISD::MAD, DL, VT, A, B, C);
1482 if (RHS.getOpcode() == ISD::FMUL) {
1483 // (fsub c, (fmul a, b)) -> mad (fneg a), b, c
1485 SDValue A = DAG.getNode(ISD::FNEG, DL, VT, RHS.getOperand(0));
1486 SDValue B = RHS.getOperand(1);
1489 return DAG.getNode(AMDGPUISD::MAD, DL, VT, A, B, C);
1492 if (LHS.getOpcode() == ISD::FADD) {
1493 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
1495 SDValue A = LHS.getOperand(0);
1496 if (A == LHS.getOperand(1)) {
1497 const SDValue Two = DAG.getTargetConstantFP(2.0, MVT::f32);
1498 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
1500 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, NegRHS);
1504 if (RHS.getOpcode() == ISD::FADD) {
1505 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
1507 SDValue A = RHS.getOperand(0);
1508 if (A == RHS.getOperand(1)) {
1509 const SDValue NegTwo = DAG.getTargetConstantFP(-2.0, MVT::f32);
1510 return DAG.getNode(AMDGPUISD::MAD, DL, VT, NegTwo, A, LHS);
1520 case ISD::ATOMIC_LOAD:
1521 case ISD::ATOMIC_STORE:
1522 case ISD::ATOMIC_CMP_SWAP:
1523 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
1524 case ISD::ATOMIC_SWAP:
1525 case ISD::ATOMIC_LOAD_ADD:
1526 case ISD::ATOMIC_LOAD_SUB:
1527 case ISD::ATOMIC_LOAD_AND:
1528 case ISD::ATOMIC_LOAD_OR:
1529 case ISD::ATOMIC_LOAD_XOR:
1530 case ISD::ATOMIC_LOAD_NAND:
1531 case ISD::ATOMIC_LOAD_MIN:
1532 case ISD::ATOMIC_LOAD_MAX:
1533 case ISD::ATOMIC_LOAD_UMIN:
1534 case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics.
1535 if (DCI.isBeforeLegalize())
1538 MemSDNode *MemNode = cast<MemSDNode>(N);
1539 SDValue Ptr = MemNode->getBasePtr();
1541 // TODO: We could also do this for multiplies.
1542 unsigned AS = MemNode->getAddressSpace();
1543 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
1544 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
1546 SmallVector<SDValue, 8> NewOps;
1547 for (unsigned I = 0, E = MemNode->getNumOperands(); I != E; ++I)
1548 NewOps.push_back(MemNode->getOperand(I));
1550 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
1551 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
1557 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1560 /// \brief Test if RegClass is one of the VSrc classes
1561 static bool isVSrc(unsigned RegClass) {
1563 default: return false;
1564 case AMDGPU::VSrc_32RegClassID:
1565 case AMDGPU::VCSrc_32RegClassID:
1566 case AMDGPU::VSrc_64RegClassID:
1567 case AMDGPU::VCSrc_64RegClassID:
1572 /// \brief Test if RegClass is one of the SSrc classes
1573 static bool isSSrc(unsigned RegClass) {
1574 return AMDGPU::SSrc_32RegClassID == RegClass ||
1575 AMDGPU::SSrc_64RegClassID == RegClass;
1578 /// \brief Analyze the possible immediate value Op
1580 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1581 /// and the immediate value if it's a literal immediate
1582 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1589 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1590 if (Node->getZExtValue() >> 32) {
1593 Imm.I = Node->getSExtValue();
1594 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1595 if (N->getValueType(0) != MVT::f32)
1597 Imm.F = Node->getValueAPF().convertToFloat();
1599 return -1; // It isn't an immediate
1601 if ((Imm.I >= -16 && Imm.I <= 64) ||
1602 Imm.F == 0.5f || Imm.F == -0.5f ||
1603 Imm.F == 1.0f || Imm.F == -1.0f ||
1604 Imm.F == 2.0f || Imm.F == -2.0f ||
1605 Imm.F == 4.0f || Imm.F == -4.0f)
1606 return 0; // It's an inline immediate
1608 return Imm.I; // It's a literal immediate
1611 /// \brief Try to fold an immediate directly into an instruction
1612 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1613 bool &ScalarSlotUsed) const {
1615 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1616 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1617 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1618 if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1621 const SDValue &Op = Mov->getOperand(0);
1622 int32_t Value = analyzeImmediate(Op.getNode());
1624 // Not an immediate at all
1627 } else if (Value == 0) {
1628 // Inline immediates can always be fold
1632 } else if (Value == Immediate) {
1633 // Already fold literal immediate
1637 } else if (!ScalarSlotUsed && !Immediate) {
1638 // Fold this literal immediate
1639 ScalarSlotUsed = true;
1649 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1650 SelectionDAG &DAG, const SDValue &Op) const {
1651 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1652 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1653 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1655 if (!Op->isMachineOpcode()) {
1656 switch(Op->getOpcode()) {
1657 case ISD::CopyFromReg: {
1658 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1659 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1660 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1661 return MRI.getRegClass(Reg);
1663 return TRI.getPhysRegClass(Reg);
1665 default: return nullptr;
1668 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1669 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1670 if (OpClassID != -1) {
1671 return TRI.getRegClass(OpClassID);
1673 switch(Op.getMachineOpcode()) {
1674 case AMDGPU::COPY_TO_REGCLASS:
1675 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1676 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1678 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1679 // class, then the register class for the value could be either a
1680 // VReg or and SReg. In order to get a more accurate
1681 if (isVSrc(OpClassID))
1682 return getRegClassForNode(DAG, Op.getOperand(0));
1684 return TRI.getRegClass(OpClassID);
1685 case AMDGPU::EXTRACT_SUBREG: {
1686 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1687 const TargetRegisterClass *SuperClass =
1688 getRegClassForNode(DAG, Op.getOperand(0));
1689 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1691 case AMDGPU::REG_SEQUENCE:
1692 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1693 return TRI.getRegClass(
1694 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1696 return getRegClassFor(Op.getSimpleValueType());
1700 /// \brief Does "Op" fit into register class "RegClass" ?
1701 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1702 unsigned RegClass) const {
1703 const TargetRegisterInfo *TRI =
1704 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
1705 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1709 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1712 /// \returns true if \p Node's operands are different from the SDValue list
1714 static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1715 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1716 if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1723 /// TODO: This needs to be removed. It's current primary purpose is to fold
1724 /// immediates into operands when legal. The legalization parts are redundant
1725 /// with SIInstrInfo::legalizeOperands which is called in a post-isel hook.
1726 SDNode *SITargetLowering::legalizeOperands(MachineSDNode *Node,
1727 SelectionDAG &DAG) const {
1728 // Original encoding (either e32 or e64)
1729 int Opcode = Node->getMachineOpcode();
1730 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1731 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1732 const MCInstrDesc *Desc = &TII->get(Opcode);
1734 unsigned NumDefs = Desc->getNumDefs();
1735 unsigned NumOps = Desc->getNumOperands();
1737 // Commuted opcode if available
1738 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1739 const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1741 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1742 assert(!DescRev || DescRev->getNumOperands() == NumOps);
1744 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1745 bool HaveVSrc = false, HaveSSrc = false;
1747 // First figure out what we already have in this instruction.
1748 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1749 i != e && Op < NumOps; ++i, ++Op) {
1751 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1752 if (isVSrc(RegClass))
1754 else if (isSSrc(RegClass))
1759 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1760 if (Imm != -1 && Imm != 0) {
1761 // Literal immediate
1766 // If we neither have VSrc nor SSrc, it makes no sense to continue.
1767 if (!HaveVSrc && !HaveSSrc)
1770 // No scalar allowed when we have both VSrc and SSrc
1771 bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1773 // If this instruction has an implicit use of VCC, then it can't use the
1775 for (unsigned i = 0, e = Desc->getNumImplicitUses(); i != e; ++i) {
1776 if (Desc->ImplicitUses[i] == AMDGPU::VCC) {
1777 ScalarSlotUsed = true;
1782 // Second go over the operands and try to fold them
1783 std::vector<SDValue> Ops;
1784 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1785 i != e && Op < NumOps; ++i, ++Op) {
1787 const SDValue &Operand = Node->getOperand(i);
1788 Ops.push_back(Operand);
1790 // Already folded immediate?
1791 if (isa<ConstantSDNode>(Operand.getNode()) ||
1792 isa<ConstantFPSDNode>(Operand.getNode()))
1795 // Is this a VSrc or SSrc operand?
1796 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1797 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1798 // Try to fold the immediates. If this ends up with multiple constant bus
1799 // uses, it will be legalized later.
1800 foldImm(Ops[i], Immediate, ScalarSlotUsed);
1804 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1806 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1807 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1809 // Test if it makes sense to swap operands
1810 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1811 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1812 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1814 // Swap commutable operands
1815 std::swap(Ops[0], Ops[1]);
1824 // Add optional chain and glue
1825 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1826 Ops.push_back(Node->getOperand(i));
1828 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1829 // this case a brand new node is always be created, even if the operands
1830 // are the same as before. So, manually check if anything has been changed.
1831 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1835 // Create a complete new instruction
1836 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1839 /// \brief Helper function for adjustWritemask
1840 static unsigned SubIdx2Lane(unsigned Idx) {
1843 case AMDGPU::sub0: return 0;
1844 case AMDGPU::sub1: return 1;
1845 case AMDGPU::sub2: return 2;
1846 case AMDGPU::sub3: return 3;
1850 /// \brief Adjust the writemask of MIMG instructions
1851 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1852 SelectionDAG &DAG) const {
1853 SDNode *Users[4] = { };
1855 unsigned OldDmask = Node->getConstantOperandVal(0);
1856 unsigned NewDmask = 0;
1858 // Try to figure out the used register components
1859 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1862 // Abort if we can't understand the usage
1863 if (!I->isMachineOpcode() ||
1864 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1867 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1868 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1869 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1871 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1873 // Set which texture component corresponds to the lane.
1875 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1877 Comp = countTrailingZeros(Dmask);
1878 Dmask &= ~(1 << Comp);
1881 // Abort if we have more than one user per component
1886 NewDmask |= 1 << Comp;
1889 // Abort if there's no change
1890 if (NewDmask == OldDmask)
1893 // Adjust the writemask in the node
1894 std::vector<SDValue> Ops;
1895 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1896 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1897 Ops.push_back(Node->getOperand(i));
1898 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1900 // If we only got one lane, replace it with a copy
1901 // (if NewDmask has only one bit set...)
1902 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1903 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1904 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1905 SDLoc(), Users[Lane]->getValueType(0),
1906 SDValue(Node, 0), RC);
1907 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1911 // Update the users of the node with the new indices
1912 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1914 SDNode *User = Users[i];
1918 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1919 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1923 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1924 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1925 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1930 /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
1931 /// with frame index operands.
1932 /// LLVM assumes that inputs are to these instructions are registers.
1933 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
1934 SelectionDAG &DAG) const {
1936 SmallVector<SDValue, 8> Ops;
1937 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
1938 if (!isa<FrameIndexSDNode>(Node->getOperand(i))) {
1939 Ops.push_back(Node->getOperand(i));
1944 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
1945 Node->getOperand(i).getValueType(),
1946 Node->getOperand(i)), 0));
1949 DAG.UpdateNodeOperands(Node, Ops);
1952 /// \brief Fold the instructions after selecting them.
1953 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1954 SelectionDAG &DAG) const {
1955 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1956 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1957 Node = AdjustRegClass(Node, DAG);
1959 if (TII->isMIMG(Node->getMachineOpcode()))
1960 adjustWritemask(Node, DAG);
1962 if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG) {
1963 legalizeTargetIndependentNode(Node, DAG);
1967 return legalizeOperands(Node, DAG);
1970 /// \brief Assign the register class depending on the number of
1971 /// bits set in the writemask
1972 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1973 SDNode *Node) const {
1974 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1975 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1977 TII->legalizeOperands(MI);
1979 if (TII->isMIMG(MI->getOpcode())) {
1980 unsigned VReg = MI->getOperand(0).getReg();
1981 unsigned Writemask = MI->getOperand(1).getImm();
1982 unsigned BitsSet = 0;
1983 for (unsigned i = 0; i < 4; ++i)
1984 BitsSet += Writemask & (1 << i) ? 1 : 0;
1986 const TargetRegisterClass *RC;
1989 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1990 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1991 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1994 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1995 MI->setDesc(TII->get(NewOpcode));
1996 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1997 MRI.setRegClass(VReg, RC);
2001 // Replace unused atomics with the no return version.
2002 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode());
2003 if (NoRetAtomicOp != -1) {
2004 if (!Node->hasAnyUseOfValue(0)) {
2005 MI->setDesc(TII->get(NoRetAtomicOp));
2006 MI->RemoveOperand(0);
2013 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
2014 SelectionDAG &DAG) const {
2017 unsigned NewOpcode = N->getMachineOpcode();
2019 switch (N->getMachineOpcode()) {
2021 case AMDGPU::S_LOAD_DWORD_IMM:
2022 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
2024 case AMDGPU::S_LOAD_DWORDX2_SGPR:
2025 if (NewOpcode == N->getMachineOpcode()) {
2026 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
2029 case AMDGPU::S_LOAD_DWORDX4_IMM:
2030 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
2031 if (NewOpcode == N->getMachineOpcode()) {
2032 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
2034 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
2037 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
2038 MachineSDNode *RSrc = DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL,
2040 DAG.getConstant(0, MVT::i64));
2042 SmallVector<SDValue, 8> Ops;
2043 Ops.push_back(SDValue(RSrc, 0));
2044 Ops.push_back(N->getOperand(0));
2045 Ops.push_back(DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32));
2047 // Copy remaining operands so we keep any chain and glue nodes that follow
2048 // the normal operands.
2049 for (unsigned I = 2, E = N->getNumOperands(); I != E; ++I)
2050 Ops.push_back(N->getOperand(I));
2052 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
2057 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2058 const TargetRegisterClass *RC,
2059 unsigned Reg, EVT VT) const {
2060 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
2062 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
2063 cast<RegisterSDNode>(VReg)->getReg(), VT);