1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
15 #include "SIISelLowering.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDILIntrinsicInfo.h"
19 #include "SIInstrInfo.h"
20 #include "SIMachineFunctionInfo.h"
21 #include "SIRegisterInfo.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/ADT/SmallString.h"
31 SITargetLowering::SITargetLowering(TargetMachine &TM) :
32 AMDGPUTargetLowering(TM) {
33 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
34 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
37 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
40 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
42 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
43 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
44 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
46 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
47 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
49 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
50 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
52 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
53 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
55 computeRegisterProperties();
58 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
60 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
61 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
62 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
63 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
65 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
66 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
67 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
68 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
69 setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
70 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
73 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
74 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
75 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
77 setOperationAction(ISD::ADD, MVT::i32, Legal);
78 setOperationAction(ISD::ADDC, MVT::i32, Legal);
79 setOperationAction(ISD::ADDE, MVT::i32, Legal);
81 // We need to custom lower vector stores from local memory
82 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
83 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
84 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
85 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
87 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
88 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
90 // We need to custom lower loads/stores from private memory
91 setOperationAction(ISD::LOAD, MVT::i32, Custom);
92 setOperationAction(ISD::LOAD, MVT::i64, Custom);
93 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
94 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
95 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
97 setOperationAction(ISD::STORE, MVT::i1, Custom);
98 setOperationAction(ISD::STORE, MVT::i32, Custom);
99 setOperationAction(ISD::STORE, MVT::i64, Custom);
100 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
101 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
103 setOperationAction(ISD::SELECT, MVT::f32, Promote);
104 AddPromotedToType(ISD::SELECT, MVT::f32, MVT::i32);
105 setOperationAction(ISD::SELECT, MVT::i64, Custom);
106 setOperationAction(ISD::SELECT, MVT::f64, Promote);
107 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
109 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
110 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
111 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
114 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
115 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
134 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
135 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
136 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
138 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
140 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
141 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
142 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
143 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
145 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
147 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
148 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
149 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
152 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
153 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
154 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
155 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
156 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
159 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
160 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
162 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
163 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
165 setOperationAction(ISD::LOAD, MVT::i1, Custom);
167 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
168 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
169 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
171 // These should use UDIVREM, so set them to expand
172 setOperationAction(ISD::UDIV, MVT::i64, Expand);
173 setOperationAction(ISD::UREM, MVT::i64, Expand);
175 // We only support LOAD/STORE and vector manipulation ops for vectors
176 // with > 4 elements.
178 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
181 for (MVT VT : VecTypes) {
182 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
186 case ISD::BUILD_VECTOR:
188 case ISD::EXTRACT_VECTOR_ELT:
189 case ISD::INSERT_VECTOR_ELT:
190 case ISD::CONCAT_VECTORS:
191 case ISD::INSERT_SUBVECTOR:
192 case ISD::EXTRACT_SUBVECTOR:
195 setOperationAction(Op, VT, Expand);
201 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
202 MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
203 setOperationAction(ISD::FTRUNC, VT, Expand);
204 setOperationAction(ISD::FCEIL, VT, Expand);
205 setOperationAction(ISD::FFLOOR, VT, Expand);
208 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
209 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
210 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
211 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
212 setOperationAction(ISD::FRINT, MVT::f64, Legal);
215 // FIXME: This should be removed and handled the same was as f32 fneg. Source
216 // modifiers also work for the double instructions.
217 setOperationAction(ISD::FNEG, MVT::f64, Expand);
219 setTargetDAGCombine(ISD::SELECT_CC);
220 setTargetDAGCombine(ISD::SETCC);
222 setTargetDAGCombine(ISD::UINT_TO_FP);
224 setSchedulingPreference(Sched::RegPressure);
227 //===----------------------------------------------------------------------===//
228 // TargetLowering queries
229 //===----------------------------------------------------------------------===//
231 bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
233 bool *IsFast) const {
237 // XXX: This depends on the address space and also we may want to revist
238 // the alignment values we specify in the DataLayout.
240 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
241 // which isn't a simple VT.
242 if (!VT.isSimple() || VT == MVT::Other)
245 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
246 // see what for specifically. The wording everywhere else seems to be the
249 // 3.6.4 - Operations using pairs of VGPRs (for example: double-floats) have
250 // no alignment restrictions.
251 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
252 // Using any pair of GPRs should be the same as any other pair.
255 return VT.bitsGE(MVT::i64);
258 // XXX - The only mention I see of this in the ISA manual is for LDS direct
259 // reads the "byte address and must be dword aligned". Is it also true for the
260 // normal loads and stores?
261 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
264 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
265 // byte-address are ignored, thus forcing Dword alignment.
268 return VT.bitsGT(MVT::i32);
271 bool SITargetLowering::shouldSplitVectorType(EVT VT) const {
272 return VT.getScalarType().bitsLE(MVT::i16);
275 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
277 const SIInstrInfo *TII =
278 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
279 return TII->isInlineConstant(Imm);
282 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
283 SDLoc DL, SDValue Chain,
284 unsigned Offset, bool Signed) const {
285 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
286 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
287 AMDGPUAS::CONSTANT_ADDRESS);
288 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
289 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
290 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
291 DAG.getConstant(Offset, MVT::i64));
292 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
293 MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
294 false, false, MemVT.getSizeInBits() >> 3);
298 SDValue SITargetLowering::LowerFormalArguments(
300 CallingConv::ID CallConv,
302 const SmallVectorImpl<ISD::InputArg> &Ins,
303 SDLoc DL, SelectionDAG &DAG,
304 SmallVectorImpl<SDValue> &InVals) const {
306 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
308 MachineFunction &MF = DAG.getMachineFunction();
309 FunctionType *FType = MF.getFunction()->getFunctionType();
310 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
312 assert(CallConv == CallingConv::C);
314 SmallVector<ISD::InputArg, 16> Splits;
315 uint32_t Skipped = 0;
317 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
318 const ISD::InputArg &Arg = Ins[i];
320 // First check if it's a PS input addr
321 if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
322 !Arg.Flags.isByVal()) {
324 assert((PSInputNum <= 15) && "Too many PS inputs!");
327 // We can savely skip PS inputs
333 Info->PSInputAddr |= 1 << PSInputNum++;
336 // Second split vertices into their elements
337 if (Info->ShaderType != ShaderType::COMPUTE && Arg.VT.isVector()) {
338 ISD::InputArg NewArg = Arg;
339 NewArg.Flags.setSplit();
340 NewArg.VT = Arg.VT.getVectorElementType();
342 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
343 // three or five element vertex only needs three or five registers,
344 // NOT four or eigth.
345 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
346 unsigned NumElements = ParamType->getVectorNumElements();
348 for (unsigned j = 0; j != NumElements; ++j) {
349 Splits.push_back(NewArg);
350 NewArg.PartOffset += NewArg.VT.getStoreSize();
353 } else if (Info->ShaderType != ShaderType::COMPUTE) {
354 Splits.push_back(Arg);
358 SmallVector<CCValAssign, 16> ArgLocs;
359 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
360 getTargetMachine(), ArgLocs, *DAG.getContext());
362 // At least one interpolation mode must be enabled or else the GPU will hang.
363 if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) {
364 Info->PSInputAddr |= 1;
365 CCInfo.AllocateReg(AMDGPU::VGPR0);
366 CCInfo.AllocateReg(AMDGPU::VGPR1);
369 // The pointer to the list of arguments is stored in SGPR0, SGPR1
370 if (Info->ShaderType == ShaderType::COMPUTE) {
371 CCInfo.AllocateReg(AMDGPU::SGPR0);
372 CCInfo.AllocateReg(AMDGPU::SGPR1);
373 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
376 if (Info->ShaderType == ShaderType::COMPUTE) {
377 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
381 AnalyzeFormalArguments(CCInfo, Splits);
383 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
385 const ISD::InputArg &Arg = Ins[i];
386 if (Skipped & (1 << i)) {
387 InVals.push_back(DAG.getUNDEF(Arg.VT));
391 CCValAssign &VA = ArgLocs[ArgIdx++];
392 EVT VT = VA.getLocVT();
396 EVT MemVT = Splits[i].VT;
397 // The first 36 bytes of the input buffer contains information about
398 // thread group and global sizes.
399 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
400 36 + VA.getLocMemOffset(),
401 Ins[i].Flags.isSExt());
402 InVals.push_back(Arg);
405 assert(VA.isRegLoc() && "Parameter must be in a register!");
407 unsigned Reg = VA.getLocReg();
409 if (VT == MVT::i64) {
410 // For now assume it is a pointer
411 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
412 &AMDGPU::SReg_64RegClass);
413 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
414 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
418 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
420 Reg = MF.addLiveIn(Reg, RC);
421 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
423 if (Arg.VT.isVector()) {
425 // Build a vector from the registers
426 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
427 unsigned NumElements = ParamType->getVectorNumElements();
429 SmallVector<SDValue, 4> Regs;
431 for (unsigned j = 1; j != NumElements; ++j) {
432 Reg = ArgLocs[ArgIdx++].getLocReg();
433 Reg = MF.addLiveIn(Reg, RC);
434 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
437 // Fill up the missing vector elements
438 NumElements = Arg.VT.getVectorNumElements() - NumElements;
439 for (unsigned j = 0; j != NumElements; ++j)
440 Regs.push_back(DAG.getUNDEF(VT));
442 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
446 InVals.push_back(Val);
451 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
452 MachineInstr * MI, MachineBasicBlock * BB) const {
454 MachineBasicBlock::iterator I = *MI;
455 const SIInstrInfo *TII =
456 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
457 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
459 switch (MI->getOpcode()) {
461 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
462 case AMDGPU::BRANCH: return BB;
463 case AMDGPU::SI_ADDR64_RSRC: {
464 unsigned SuperReg = MI->getOperand(0).getReg();
465 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
466 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
467 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
468 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
469 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
470 .addOperand(MI->getOperand(1));
471 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
473 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
474 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
475 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
477 .addImm(AMDGPU::sub0)
479 .addImm(AMDGPU::sub1);
480 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
482 .addImm(AMDGPU::sub0_sub1)
484 .addImm(AMDGPU::sub2_sub3);
485 MI->eraseFromParent();
488 case AMDGPU::V_SUB_F64: {
489 unsigned DestReg = MI->getOperand(0).getReg();
490 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
491 .addImm(0) // SRC0 modifiers
492 .addReg(MI->getOperand(1).getReg())
493 .addImm(1) // SRC1 modifiers
494 .addReg(MI->getOperand(2).getReg())
495 .addImm(0) // SRC2 modifiers
499 MI->eraseFromParent();
502 case AMDGPU::SI_RegisterStorePseudo: {
503 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
504 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
505 MachineInstrBuilder MIB =
506 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
508 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
509 MIB.addOperand(MI->getOperand(i));
511 MI->eraseFromParent();
514 case AMDGPU::FABS_SI: {
515 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
516 const SIInstrInfo *TII =
517 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
518 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
519 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
522 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
523 MI->getOperand(0).getReg())
524 .addReg(MI->getOperand(1).getReg())
526 MI->eraseFromParent();
529 case AMDGPU::FNEG_SI: {
530 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
531 const SIInstrInfo *TII =
532 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
533 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
534 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
537 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
538 MI->getOperand(0).getReg())
539 .addReg(MI->getOperand(1).getReg())
541 MI->eraseFromParent();
544 case AMDGPU::FCLAMP_SI: {
545 const SIInstrInfo *TII =
546 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
547 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
548 MI->getOperand(0).getReg())
549 .addImm(0) // SRC0 modifiers
550 .addOperand(MI->getOperand(1))
551 .addImm(0) // SRC1 modifiers
555 MI->eraseFromParent();
561 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
562 if (!VT.isVector()) {
565 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
568 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
572 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
573 VT = VT.getScalarType();
578 switch (VT.getSimpleVT().SimpleTy) {
580 return false; /* There is V_MAD_F32 for f32 */
590 //===----------------------------------------------------------------------===//
591 // Custom DAG Lowering Operations
592 //===----------------------------------------------------------------------===//
594 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
595 MachineFunction &MF = DAG.getMachineFunction();
596 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
597 switch (Op.getOpcode()) {
598 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
599 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
601 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
602 if (Op.getValueType().isVector() &&
603 (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
604 Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
605 (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
606 Op.getValueType().getVectorNumElements() > 4))) {
607 SDValue MergedValues[2] = {
608 SplitVectorLoad(Op, DAG),
611 return DAG.getMergeValues(MergedValues, SDLoc(Op));
613 return LowerLOAD(Op, DAG);
617 case ISD::SELECT: return LowerSELECT(Op, DAG);
618 case ISD::STORE: return LowerSTORE(Op, DAG);
619 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
620 case ISD::INTRINSIC_WO_CHAIN: {
621 unsigned IntrinsicID =
622 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
623 EVT VT = Op.getValueType();
625 //XXX: Hardcoded we only use two to store the pointer to the parameters.
626 unsigned NumUserSGPRs = 2;
627 switch (IntrinsicID) {
628 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
629 case Intrinsic::r600_read_ngroups_x:
630 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
631 case Intrinsic::r600_read_ngroups_y:
632 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
633 case Intrinsic::r600_read_ngroups_z:
634 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
635 case Intrinsic::r600_read_global_size_x:
636 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
637 case Intrinsic::r600_read_global_size_y:
638 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
639 case Intrinsic::r600_read_global_size_z:
640 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
641 case Intrinsic::r600_read_local_size_x:
642 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
643 case Intrinsic::r600_read_local_size_y:
644 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
645 case Intrinsic::r600_read_local_size_z:
646 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
647 case Intrinsic::r600_read_tgid_x:
648 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
649 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 0), VT);
650 case Intrinsic::r600_read_tgid_y:
651 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
652 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 1), VT);
653 case Intrinsic::r600_read_tgid_z:
654 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
655 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 2), VT);
656 case Intrinsic::r600_read_tidig_x:
657 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
659 case Intrinsic::r600_read_tidig_y:
660 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
662 case Intrinsic::r600_read_tidig_z:
663 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
665 case AMDGPUIntrinsic::SI_load_const: {
671 MachineMemOperand *MMO = MF.getMachineMemOperand(
672 MachinePointerInfo(),
673 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
674 VT.getSizeInBits() / 8, 4);
675 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
676 Op->getVTList(), Ops, VT, MMO);
678 case AMDGPUIntrinsic::SI_sample:
679 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
680 case AMDGPUIntrinsic::SI_sampleb:
681 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
682 case AMDGPUIntrinsic::SI_sampled:
683 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
684 case AMDGPUIntrinsic::SI_samplel:
685 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
686 case AMDGPUIntrinsic::SI_vs_load_input:
687 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
694 case ISD::INTRINSIC_VOID:
695 SDValue Chain = Op.getOperand(0);
696 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
698 switch (IntrinsicID) {
699 case AMDGPUIntrinsic::SI_tbuffer_store: {
717 EVT VT = Op.getOperand(3).getValueType();
719 MachineMemOperand *MMO = MF.getMachineMemOperand(
720 MachinePointerInfo(),
721 MachineMemOperand::MOStore,
722 VT.getSizeInBits() / 8, 4);
723 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
724 Op->getVTList(), Ops, VT, MMO);
733 /// \brief Helper function for LowerBRCOND
734 static SDNode *findUser(SDValue Value, unsigned Opcode) {
736 SDNode *Parent = Value.getNode();
737 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
740 if (I.getUse().get() != Value)
743 if (I->getOpcode() == Opcode)
749 /// This transforms the control flow intrinsics to get the branch destination as
750 /// last parameter, also switches branch target with BR if the need arise
751 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
752 SelectionDAG &DAG) const {
756 SDNode *Intr = BRCOND.getOperand(1).getNode();
757 SDValue Target = BRCOND.getOperand(2);
758 SDNode *BR = nullptr;
760 if (Intr->getOpcode() == ISD::SETCC) {
761 // As long as we negate the condition everything is fine
762 SDNode *SetCC = Intr;
763 assert(SetCC->getConstantOperandVal(1) == 1);
764 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
766 Intr = SetCC->getOperand(0).getNode();
769 // Get the target from BR if we don't negate the condition
770 BR = findUser(BRCOND, ISD::BR);
771 Target = BR->getOperand(1);
774 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
776 // Build the result and
777 SmallVector<EVT, 4> Res;
778 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
779 Res.push_back(Intr->getValueType(i));
781 // operands of the new intrinsic call
782 SmallVector<SDValue, 4> Ops;
783 Ops.push_back(BRCOND.getOperand(0));
784 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
785 Ops.push_back(Intr->getOperand(i));
786 Ops.push_back(Target);
788 // build the new intrinsic call
789 SDNode *Result = DAG.getNode(
790 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
791 DAG.getVTList(Res), Ops).getNode();
794 // Give the branch instruction our target
799 DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops);
802 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
804 // Copy the intrinsic results to registers
805 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
806 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
810 Chain = DAG.getCopyToReg(
812 CopyToReg->getOperand(1),
813 SDValue(Result, i - 1),
816 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
819 // Remove the old intrinsic from the chain
820 DAG.ReplaceAllUsesOfValueWith(
821 SDValue(Intr, Intr->getNumValues() - 1),
822 Intr->getOperand(0));
827 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
829 LoadSDNode *Load = cast<LoadSDNode>(Op);
830 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
831 SDValue MergedValues[2];
832 MergedValues[1] = Load->getChain();
834 MergedValues[0] = Ret;
835 return DAG.getMergeValues(MergedValues, DL);
838 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
842 EVT MemVT = Load->getMemoryVT();
844 assert(!MemVT.isVector() && "Private loads should be scalarized");
845 assert(!MemVT.isFloatingPoint() && "FP loads should be promoted to int");
847 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
848 DAG.getConstant(2, MVT::i32));
849 Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
850 Load->getChain(), Ptr,
851 DAG.getTargetConstant(0, MVT::i32),
853 if (MemVT.getSizeInBits() == 64) {
854 SDValue IncPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
855 DAG.getConstant(1, MVT::i32));
857 SDValue LoadUpper = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
858 Load->getChain(), IncPtr,
859 DAG.getTargetConstant(0, MVT::i32),
862 Ret = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ret, LoadUpper);
865 MergedValues[0] = Ret;
866 return DAG.getMergeValues(MergedValues, DL);
870 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
872 SelectionDAG &DAG) const {
873 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
879 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
880 if (Op.getValueType() != MVT::i64)
884 SDValue Cond = Op.getOperand(0);
886 SDValue Zero = DAG.getConstant(0, MVT::i32);
887 SDValue One = DAG.getConstant(1, MVT::i32);
889 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
890 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
892 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
893 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
895 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
897 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
898 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
900 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
902 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
903 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
906 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
908 StoreSDNode *Store = cast<StoreSDNode>(Op);
909 EVT VT = Store->getMemoryVT();
911 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
915 if (VT.isVector() && VT.getVectorNumElements() >= 8)
916 return SplitVectorStore(Op, DAG);
919 return DAG.getTruncStore(Store->getChain(), DL,
920 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
921 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
923 if (Store->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
926 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Store->getBasePtr(),
927 DAG.getConstant(2, MVT::i32));
928 SDValue Chain = Store->getChain();
929 SmallVector<SDValue, 8> Values;
931 if (Store->isTruncatingStore()) {
933 if (Store->getMemoryVT() == MVT::i8) {
935 } else if (Store->getMemoryVT() == MVT::i16) {
938 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
939 Chain, Store->getBasePtr(),
940 DAG.getConstant(0, MVT::i32));
941 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getBasePtr(),
942 DAG.getConstant(0x3, MVT::i32));
943 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
944 DAG.getConstant(3, MVT::i32));
945 SDValue MaskedValue = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getValue(),
946 DAG.getConstant(Mask, MVT::i32));
947 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
948 MaskedValue, ShiftAmt);
949 SDValue RotrAmt = DAG.getNode(ISD::SUB, DL, MVT::i32,
950 DAG.getConstant(32, MVT::i32), ShiftAmt);
951 SDValue DstMask = DAG.getNode(ISD::ROTR, DL, MVT::i32,
952 DAG.getConstant(Mask, MVT::i32),
954 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
955 Dst = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
957 Values.push_back(Dst);
958 } else if (VT == MVT::i64) {
959 for (unsigned i = 0; i < 2; ++i) {
960 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
961 Store->getValue(), DAG.getConstant(i, MVT::i32)));
963 } else if (VT == MVT::i128) {
964 for (unsigned i = 0; i < 2; ++i) {
965 for (unsigned j = 0; j < 2; ++j) {
966 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
967 DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64,
968 Store->getValue(), DAG.getConstant(i, MVT::i32)),
969 DAG.getConstant(j, MVT::i32)));
973 Values.push_back(Store->getValue());
976 for (unsigned i = 0; i < Values.size(); ++i) {
977 SDValue PartPtr = DAG.getNode(ISD::ADD, DL, MVT::i32,
978 Ptr, DAG.getConstant(i, MVT::i32));
979 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
980 Chain, Values[i], PartPtr,
981 DAG.getTargetConstant(0, MVT::i32));
986 //===----------------------------------------------------------------------===//
987 // Custom DAG optimizations
988 //===----------------------------------------------------------------------===//
990 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
991 DAGCombinerInfo &DCI) {
992 EVT VT = N->getValueType(0);
993 EVT ScalarVT = VT.getScalarType();
994 if (ScalarVT != MVT::f32)
997 SelectionDAG &DAG = DCI.DAG;
1000 SDValue Src = N->getOperand(0);
1001 EVT SrcVT = Src.getValueType();
1003 // TODO: We could try to match extracting the higher bytes, which would be
1004 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1005 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1006 // about in practice.
1007 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1008 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1009 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1010 DCI.AddToWorklist(Cvt.getNode());
1015 // We are primarily trying to catch operations on illegal vector types
1016 // before they are expanded.
1017 // For scalars, we can use the more flexible method of checking masked bits
1018 // after legalization.
1019 if (!DCI.isBeforeLegalize() ||
1020 !SrcVT.isVector() ||
1021 SrcVT.getVectorElementType() != MVT::i8) {
1025 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1027 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1029 unsigned NElts = SrcVT.getVectorNumElements();
1030 if (!SrcVT.isSimple() && NElts != 3)
1033 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1034 // prevent a mess from expanding to v4i32 and repacking.
1035 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1036 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1037 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1038 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1040 LoadSDNode *Load = cast<LoadSDNode>(Src);
1041 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1045 Load->getMemOperand());
1047 // Make sure successors of the original load stay after it by updating
1048 // them to use the new Chain.
1049 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1051 SmallVector<SDValue, 4> Elts;
1052 if (RegVT.isVector())
1053 DAG.ExtractVectorElements(NewLoad, Elts);
1055 Elts.push_back(NewLoad);
1057 SmallVector<SDValue, 4> Ops;
1059 unsigned EltIdx = 0;
1060 for (SDValue Elt : Elts) {
1061 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1062 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1063 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1064 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1065 DCI.AddToWorklist(Cvt.getNode());
1072 assert(Ops.size() == NElts);
1074 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1080 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1081 DAGCombinerInfo &DCI) const {
1082 SelectionDAG &DAG = DCI.DAG;
1084 EVT VT = N->getValueType(0);
1086 switch (N->getOpcode()) {
1087 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1088 case ISD::SELECT_CC: {
1089 ConstantSDNode *True, *False;
1090 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
1091 if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1092 && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1093 && True->isAllOnesValue()
1094 && False->isNullValue()
1096 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
1097 N->getOperand(1), N->getOperand(4));
1103 SDValue Arg0 = N->getOperand(0);
1104 SDValue Arg1 = N->getOperand(1);
1105 SDValue CC = N->getOperand(2);
1106 ConstantSDNode * C = nullptr;
1107 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1109 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1111 && Arg0.getOpcode() == ISD::SIGN_EXTEND
1112 && Arg0.getOperand(0).getValueType() == MVT::i1
1113 && (C = dyn_cast<ConstantSDNode>(Arg1))
1115 && CCOp == ISD::SETNE) {
1116 return SimplifySetCC(VT, Arg0.getOperand(0),
1117 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1122 case AMDGPUISD::CVT_F32_UBYTE0:
1123 case AMDGPUISD::CVT_F32_UBYTE1:
1124 case AMDGPUISD::CVT_F32_UBYTE2:
1125 case AMDGPUISD::CVT_F32_UBYTE3: {
1126 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1128 SDValue Src = N->getOperand(0);
1129 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1131 APInt KnownZero, KnownOne;
1132 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1133 !DCI.isBeforeLegalizeOps());
1134 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1135 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1136 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1137 DCI.CommitTargetLoweringOpt(TLO);
1143 case ISD::UINT_TO_FP: {
1144 return performUCharToFloatCombine(N, DCI);
1148 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1151 /// \brief Test if RegClass is one of the VSrc classes
1152 static bool isVSrc(unsigned RegClass) {
1153 return AMDGPU::VSrc_32RegClassID == RegClass ||
1154 AMDGPU::VSrc_64RegClassID == RegClass;
1157 /// \brief Test if RegClass is one of the SSrc classes
1158 static bool isSSrc(unsigned RegClass) {
1159 return AMDGPU::SSrc_32RegClassID == RegClass ||
1160 AMDGPU::SSrc_64RegClassID == RegClass;
1163 /// \brief Analyze the possible immediate value Op
1165 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1166 /// and the immediate value if it's a literal immediate
1167 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1174 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1175 if (Node->getZExtValue() >> 32) {
1178 Imm.I = Node->getSExtValue();
1179 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1180 if (N->getValueType(0) != MVT::f32)
1182 Imm.F = Node->getValueAPF().convertToFloat();
1184 return -1; // It isn't an immediate
1186 if ((Imm.I >= -16 && Imm.I <= 64) ||
1187 Imm.F == 0.5f || Imm.F == -0.5f ||
1188 Imm.F == 1.0f || Imm.F == -1.0f ||
1189 Imm.F == 2.0f || Imm.F == -2.0f ||
1190 Imm.F == 4.0f || Imm.F == -4.0f)
1191 return 0; // It's an inline immediate
1193 return Imm.I; // It's a literal immediate
1196 /// \brief Try to fold an immediate directly into an instruction
1197 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1198 bool &ScalarSlotUsed) const {
1200 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1201 const SIInstrInfo *TII =
1202 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1203 if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1206 const SDValue &Op = Mov->getOperand(0);
1207 int32_t Value = analyzeImmediate(Op.getNode());
1209 // Not an immediate at all
1212 } else if (Value == 0) {
1213 // Inline immediates can always be fold
1217 } else if (Value == Immediate) {
1218 // Already fold literal immediate
1222 } else if (!ScalarSlotUsed && !Immediate) {
1223 // Fold this literal immediate
1224 ScalarSlotUsed = true;
1234 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1235 SelectionDAG &DAG, const SDValue &Op) const {
1236 const SIInstrInfo *TII =
1237 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1238 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1240 if (!Op->isMachineOpcode()) {
1241 switch(Op->getOpcode()) {
1242 case ISD::CopyFromReg: {
1243 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1244 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1245 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1246 return MRI.getRegClass(Reg);
1248 return TRI.getPhysRegClass(Reg);
1250 default: return nullptr;
1253 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1254 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1255 if (OpClassID != -1) {
1256 return TRI.getRegClass(OpClassID);
1258 switch(Op.getMachineOpcode()) {
1259 case AMDGPU::COPY_TO_REGCLASS:
1260 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1261 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1263 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1264 // class, then the register class for the value could be either a
1265 // VReg or and SReg. In order to get a more accurate
1266 if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1267 OpClassID == AMDGPU::VSrc_64RegClassID) {
1268 return getRegClassForNode(DAG, Op.getOperand(0));
1270 return TRI.getRegClass(OpClassID);
1271 case AMDGPU::EXTRACT_SUBREG: {
1272 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1273 const TargetRegisterClass *SuperClass =
1274 getRegClassForNode(DAG, Op.getOperand(0));
1275 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1277 case AMDGPU::REG_SEQUENCE:
1278 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1279 return TRI.getRegClass(
1280 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1282 return getRegClassFor(Op.getSimpleValueType());
1286 /// \brief Does "Op" fit into register class "RegClass" ?
1287 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1288 unsigned RegClass) const {
1289 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1290 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1294 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1297 /// \brief Make sure that we don't exeed the number of allowed scalars
1298 void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
1300 bool &ScalarSlotUsed) const {
1302 // First map the operands register class to a destination class
1303 if (RegClass == AMDGPU::VSrc_32RegClassID)
1304 RegClass = AMDGPU::VReg_32RegClassID;
1305 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1306 RegClass = AMDGPU::VReg_64RegClassID;
1310 // Nothing to do if they fit naturally
1311 if (fitsRegClass(DAG, Operand, RegClass))
1314 // If the scalar slot isn't used yet use it now
1315 if (!ScalarSlotUsed) {
1316 ScalarSlotUsed = true;
1320 // This is a conservative aproach. It is possible that we can't determine the
1321 // correct register class and copy too often, but better safe than sorry.
1322 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1323 SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
1324 Operand.getValueType(), Operand, RC);
1325 Operand = SDValue(Node, 0);
1328 /// \returns true if \p Node's operands are different from the SDValue list
1330 static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1331 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1332 if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1339 /// \brief Try to fold the Nodes operands into the Node
1340 SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
1341 SelectionDAG &DAG) const {
1343 // Original encoding (either e32 or e64)
1344 int Opcode = Node->getMachineOpcode();
1345 const SIInstrInfo *TII =
1346 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1347 const MCInstrDesc *Desc = &TII->get(Opcode);
1349 unsigned NumDefs = Desc->getNumDefs();
1350 unsigned NumOps = Desc->getNumOperands();
1352 // Commuted opcode if available
1353 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1354 const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1356 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1357 assert(!DescRev || DescRev->getNumOperands() == NumOps);
1359 // e64 version if available, -1 otherwise
1360 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1361 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
1362 int InputModifiers[3] = {0};
1364 assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
1366 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1367 bool HaveVSrc = false, HaveSSrc = false;
1369 // First figure out what we already have in this instruction.
1370 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1371 i != e && Op < NumOps; ++i, ++Op) {
1373 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1374 if (isVSrc(RegClass))
1376 else if (isSSrc(RegClass))
1381 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1382 if (Imm != -1 && Imm != 0) {
1383 // Literal immediate
1388 // If we neither have VSrc nor SSrc, it makes no sense to continue.
1389 if (!HaveVSrc && !HaveSSrc)
1392 // No scalar allowed when we have both VSrc and SSrc
1393 bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1395 // Second go over the operands and try to fold them
1396 std::vector<SDValue> Ops;
1397 bool Promote2e64 = false;
1398 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1399 i != e && Op < NumOps; ++i, ++Op) {
1401 const SDValue &Operand = Node->getOperand(i);
1402 Ops.push_back(Operand);
1404 // Already folded immediate?
1405 if (isa<ConstantSDNode>(Operand.getNode()) ||
1406 isa<ConstantFPSDNode>(Operand.getNode()))
1409 // Is this a VSrc or SSrc operand?
1410 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1411 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1412 // Try to fold the immediates
1413 if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
1414 // Folding didn't work, make sure we don't hit the SReg limit.
1415 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1420 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1422 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1423 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1425 // Test if it makes sense to swap operands
1426 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1427 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1428 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1430 // Swap commutable operands
1431 std::swap(Ops[0], Ops[1]);
1443 // Test if it makes sense to switch to e64 encoding
1444 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1445 if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
1448 int32_t TmpImm = -1;
1449 if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
1450 (!fitsRegClass(DAG, Ops[i], RegClass) &&
1451 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1453 // Switch to e64 encoding
1461 if (!DescE64 && !Promote2e64)
1463 if (!Operand.isMachineOpcode())
1465 if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) {
1467 Ops.push_back(Operand.getOperand(0));
1468 InputModifiers[i] = 1;
1475 else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) {
1477 Ops.push_back(Operand.getOperand(0));
1478 InputModifiers[i] = 2;
1488 std::vector<SDValue> OldOps(Ops);
1490 for (unsigned i = 0; i < OldOps.size(); ++i) {
1492 Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
1493 Ops.push_back(OldOps[i]);
1495 // Add the modifier flags while promoting
1496 for (unsigned i = 0; i < 2; ++i)
1497 Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
1500 // Add optional chain and glue
1501 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1502 Ops.push_back(Node->getOperand(i));
1504 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1505 // this case a brand new node is always be created, even if the operands
1506 // are the same as before. So, manually check if anything has been changed.
1507 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1511 // Create a complete new instruction
1512 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1515 /// \brief Helper function for adjustWritemask
1516 static unsigned SubIdx2Lane(unsigned Idx) {
1519 case AMDGPU::sub0: return 0;
1520 case AMDGPU::sub1: return 1;
1521 case AMDGPU::sub2: return 2;
1522 case AMDGPU::sub3: return 3;
1526 /// \brief Adjust the writemask of MIMG instructions
1527 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1528 SelectionDAG &DAG) const {
1529 SDNode *Users[4] = { };
1531 unsigned OldDmask = Node->getConstantOperandVal(0);
1532 unsigned NewDmask = 0;
1534 // Try to figure out the used register components
1535 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1538 // Abort if we can't understand the usage
1539 if (!I->isMachineOpcode() ||
1540 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1543 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1544 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1545 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1547 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1549 // Set which texture component corresponds to the lane.
1551 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1553 Comp = countTrailingZeros(Dmask);
1554 Dmask &= ~(1 << Comp);
1557 // Abort if we have more than one user per component
1562 NewDmask |= 1 << Comp;
1565 // Abort if there's no change
1566 if (NewDmask == OldDmask)
1569 // Adjust the writemask in the node
1570 std::vector<SDValue> Ops;
1571 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1572 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1573 Ops.push_back(Node->getOperand(i));
1574 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1576 // If we only got one lane, replace it with a copy
1577 // (if NewDmask has only one bit set...)
1578 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1579 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1580 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1581 SDLoc(), Users[Lane]->getValueType(0),
1582 SDValue(Node, 0), RC);
1583 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1587 // Update the users of the node with the new indices
1588 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1590 SDNode *User = Users[i];
1594 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1595 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1599 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1600 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1601 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1606 /// \brief Fold the instructions after selecting them.
1607 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1608 SelectionDAG &DAG) const {
1609 const SIInstrInfo *TII =
1610 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1611 Node = AdjustRegClass(Node, DAG);
1613 if (TII->isMIMG(Node->getMachineOpcode()))
1614 adjustWritemask(Node, DAG);
1616 return foldOperands(Node, DAG);
1619 /// \brief Assign the register class depending on the number of
1620 /// bits set in the writemask
1621 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1622 SDNode *Node) const {
1623 const SIInstrInfo *TII =
1624 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1625 if (!TII->isMIMG(MI->getOpcode()))
1628 unsigned VReg = MI->getOperand(0).getReg();
1629 unsigned Writemask = MI->getOperand(1).getImm();
1630 unsigned BitsSet = 0;
1631 for (unsigned i = 0; i < 4; ++i)
1632 BitsSet += Writemask & (1 << i) ? 1 : 0;
1634 const TargetRegisterClass *RC;
1637 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1638 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1639 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1642 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1643 MI->setDesc(TII->get(NewOpcode));
1644 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1645 MRI.setRegClass(VReg, RC);
1648 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1649 SelectionDAG &DAG) const {
1652 unsigned NewOpcode = N->getMachineOpcode();
1654 switch (N->getMachineOpcode()) {
1656 case AMDGPU::S_LOAD_DWORD_IMM:
1657 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1659 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1660 if (NewOpcode == N->getMachineOpcode()) {
1661 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1664 case AMDGPU::S_LOAD_DWORDX4_IMM:
1665 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1666 if (NewOpcode == N->getMachineOpcode()) {
1667 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1669 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1672 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
1674 SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
1675 DAG.getConstant(0, MVT::i64)), 0),
1677 DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
1679 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
1684 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1685 const TargetRegisterClass *RC,
1686 unsigned Reg, EVT VT) const {
1687 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1689 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1690 cast<RegisterSDNode>(VReg)->getReg(), VT);