1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
15 #include "SIISelLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "SIInstrInfo.h"
20 #include "SIMachineFunctionInfo.h"
21 #include "SIRegisterInfo.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/ADT/SmallString.h"
31 SITargetLowering::SITargetLowering(TargetMachine &TM) :
32 AMDGPUTargetLowering(TM) {
33 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
34 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
37 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
40 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
42 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
43 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
44 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
46 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
47 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
49 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
50 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
52 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
53 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
55 computeRegisterProperties();
58 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
60 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
61 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
62 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
63 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
65 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
66 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
67 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
68 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
69 setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
70 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
73 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
74 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
75 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
77 setOperationAction(ISD::ADD, MVT::i32, Legal);
78 setOperationAction(ISD::ADDC, MVT::i32, Legal);
79 setOperationAction(ISD::ADDE, MVT::i32, Legal);
80 setOperationAction(ISD::SUBC, MVT::i32, Legal);
81 setOperationAction(ISD::SUBE, MVT::i32, Legal);
83 // We need to custom lower vector stores from local memory
84 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
85 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
86 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
87 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
89 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
90 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
92 // We need to custom lower loads/stores from private memory
93 setOperationAction(ISD::LOAD, MVT::i32, Custom);
94 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
95 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
96 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
98 setOperationAction(ISD::STORE, MVT::i1, Custom);
99 setOperationAction(ISD::STORE, MVT::i32, Custom);
100 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
101 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
103 setOperationAction(ISD::SELECT, MVT::f32, Promote);
104 AddPromotedToType(ISD::SELECT, MVT::f32, MVT::i32);
105 setOperationAction(ISD::SELECT, MVT::i64, Custom);
106 setOperationAction(ISD::SELECT, MVT::f64, Promote);
107 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
109 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
110 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
111 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
114 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
115 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
134 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
135 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
136 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
138 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
139 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
141 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
142 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
143 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
145 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
146 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
148 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
149 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
154 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
155 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
156 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
157 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
159 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
160 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
163 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
164 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
166 setOperationAction(ISD::LOAD, MVT::i1, Custom);
168 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
169 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
171 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
172 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
173 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
175 // These should use UDIVREM, so set them to expand
176 setOperationAction(ISD::UDIV, MVT::i64, Expand);
177 setOperationAction(ISD::UREM, MVT::i64, Expand);
179 // We only support LOAD/STORE and vector manipulation ops for vectors
180 // with > 4 elements.
182 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
185 for (MVT VT : VecTypes) {
186 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
190 case ISD::BUILD_VECTOR:
192 case ISD::EXTRACT_VECTOR_ELT:
193 case ISD::INSERT_VECTOR_ELT:
194 case ISD::CONCAT_VECTORS:
195 case ISD::INSERT_SUBVECTOR:
196 case ISD::EXTRACT_SUBVECTOR:
199 setOperationAction(Op, VT, Expand);
205 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
206 MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
207 setOperationAction(ISD::FTRUNC, VT, Expand);
208 setOperationAction(ISD::FCEIL, VT, Expand);
209 setOperationAction(ISD::FFLOOR, VT, Expand);
212 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
213 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
214 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
215 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
216 setOperationAction(ISD::FRINT, MVT::f64, Legal);
219 // FIXME: These should be removed and handled the same was as f32 fneg. Source
220 // modifiers also work for the double instructions.
221 setOperationAction(ISD::FNEG, MVT::f64, Expand);
222 setOperationAction(ISD::FABS, MVT::f64, Expand);
224 setOperationAction(ISD::FDIV, MVT::f32, Custom);
226 setTargetDAGCombine(ISD::SELECT_CC);
227 setTargetDAGCombine(ISD::SETCC);
229 setTargetDAGCombine(ISD::UINT_TO_FP);
231 setSchedulingPreference(Sched::RegPressure);
234 //===----------------------------------------------------------------------===//
235 // TargetLowering queries
236 //===----------------------------------------------------------------------===//
238 bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
240 bool *IsFast) const {
244 // XXX: This depends on the address space and also we may want to revist
245 // the alignment values we specify in the DataLayout.
247 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
248 // which isn't a simple VT.
249 if (!VT.isSimple() || VT == MVT::Other)
252 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
253 // see what for specifically. The wording everywhere else seems to be the
256 // 3.6.4 - Operations using pairs of VGPRs (for example: double-floats) have
257 // no alignment restrictions.
258 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
259 // Using any pair of GPRs should be the same as any other pair.
262 return VT.bitsGE(MVT::i64);
265 // XXX - The only mention I see of this in the ISA manual is for LDS direct
266 // reads the "byte address and must be dword aligned". Is it also true for the
267 // normal loads and stores?
268 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
271 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
272 // byte-address are ignored, thus forcing Dword alignment.
275 return VT.bitsGT(MVT::i32);
278 TargetLoweringBase::LegalizeTypeAction
279 SITargetLowering::getPreferredVectorAction(EVT VT) const {
280 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
281 return TypeSplitVector;
283 return TargetLoweringBase::getPreferredVectorAction(VT);
286 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
288 const SIInstrInfo *TII =
289 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
290 return TII->isInlineConstant(Imm);
293 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
294 SDLoc DL, SDValue Chain,
295 unsigned Offset, bool Signed) const {
296 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
297 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
298 AMDGPUAS::CONSTANT_ADDRESS);
299 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
300 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
301 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
302 DAG.getConstant(Offset, MVT::i64));
303 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
304 MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
305 false, false, MemVT.getSizeInBits() >> 3);
309 SDValue SITargetLowering::LowerFormalArguments(
311 CallingConv::ID CallConv,
313 const SmallVectorImpl<ISD::InputArg> &Ins,
314 SDLoc DL, SelectionDAG &DAG,
315 SmallVectorImpl<SDValue> &InVals) const {
317 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
319 MachineFunction &MF = DAG.getMachineFunction();
320 FunctionType *FType = MF.getFunction()->getFunctionType();
321 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
323 assert(CallConv == CallingConv::C);
325 SmallVector<ISD::InputArg, 16> Splits;
326 uint32_t Skipped = 0;
328 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
329 const ISD::InputArg &Arg = Ins[i];
331 // First check if it's a PS input addr
332 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
333 !Arg.Flags.isByVal()) {
335 assert((PSInputNum <= 15) && "Too many PS inputs!");
338 // We can savely skip PS inputs
344 Info->PSInputAddr |= 1 << PSInputNum++;
347 // Second split vertices into their elements
348 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
349 ISD::InputArg NewArg = Arg;
350 NewArg.Flags.setSplit();
351 NewArg.VT = Arg.VT.getVectorElementType();
353 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
354 // three or five element vertex only needs three or five registers,
355 // NOT four or eigth.
356 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
357 unsigned NumElements = ParamType->getVectorNumElements();
359 for (unsigned j = 0; j != NumElements; ++j) {
360 Splits.push_back(NewArg);
361 NewArg.PartOffset += NewArg.VT.getStoreSize();
364 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
365 Splits.push_back(Arg);
369 SmallVector<CCValAssign, 16> ArgLocs;
370 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
371 getTargetMachine(), ArgLocs, *DAG.getContext());
373 // At least one interpolation mode must be enabled or else the GPU will hang.
374 if (Info->getShaderType() == ShaderType::PIXEL &&
375 (Info->PSInputAddr & 0x7F) == 0) {
376 Info->PSInputAddr |= 1;
377 CCInfo.AllocateReg(AMDGPU::VGPR0);
378 CCInfo.AllocateReg(AMDGPU::VGPR1);
381 // The pointer to the list of arguments is stored in SGPR0, SGPR1
382 if (Info->getShaderType() == ShaderType::COMPUTE) {
383 CCInfo.AllocateReg(AMDGPU::SGPR0);
384 CCInfo.AllocateReg(AMDGPU::SGPR1);
385 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
388 if (Info->getShaderType() == ShaderType::COMPUTE) {
389 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
393 AnalyzeFormalArguments(CCInfo, Splits);
395 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
397 const ISD::InputArg &Arg = Ins[i];
398 if (Skipped & (1 << i)) {
399 InVals.push_back(DAG.getUNDEF(Arg.VT));
403 CCValAssign &VA = ArgLocs[ArgIdx++];
404 EVT VT = VA.getLocVT();
408 EVT MemVT = Splits[i].VT;
409 // The first 36 bytes of the input buffer contains information about
410 // thread group and global sizes.
411 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
412 36 + VA.getLocMemOffset(),
413 Ins[i].Flags.isSExt());
414 InVals.push_back(Arg);
417 assert(VA.isRegLoc() && "Parameter must be in a register!");
419 unsigned Reg = VA.getLocReg();
421 if (VT == MVT::i64) {
422 // For now assume it is a pointer
423 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
424 &AMDGPU::SReg_64RegClass);
425 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
426 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
430 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
432 Reg = MF.addLiveIn(Reg, RC);
433 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
435 if (Arg.VT.isVector()) {
437 // Build a vector from the registers
438 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
439 unsigned NumElements = ParamType->getVectorNumElements();
441 SmallVector<SDValue, 4> Regs;
443 for (unsigned j = 1; j != NumElements; ++j) {
444 Reg = ArgLocs[ArgIdx++].getLocReg();
445 Reg = MF.addLiveIn(Reg, RC);
446 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
449 // Fill up the missing vector elements
450 NumElements = Arg.VT.getVectorNumElements() - NumElements;
451 for (unsigned j = 0; j != NumElements; ++j)
452 Regs.push_back(DAG.getUNDEF(VT));
454 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
458 InVals.push_back(Val);
463 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
464 MachineInstr * MI, MachineBasicBlock * BB) const {
466 MachineBasicBlock::iterator I = *MI;
467 const SIInstrInfo *TII =
468 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
469 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
471 switch (MI->getOpcode()) {
473 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
474 case AMDGPU::BRANCH: return BB;
475 case AMDGPU::SI_ADDR64_RSRC: {
476 unsigned SuperReg = MI->getOperand(0).getReg();
477 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
478 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
479 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
480 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
481 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
482 .addOperand(MI->getOperand(1));
483 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
485 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
486 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
487 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
489 .addImm(AMDGPU::sub0)
491 .addImm(AMDGPU::sub1);
492 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
494 .addImm(AMDGPU::sub0_sub1)
496 .addImm(AMDGPU::sub2_sub3);
497 MI->eraseFromParent();
500 case AMDGPU::V_SUB_F64: {
501 unsigned DestReg = MI->getOperand(0).getReg();
502 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
503 .addImm(0) // SRC0 modifiers
504 .addReg(MI->getOperand(1).getReg())
505 .addImm(1) // SRC1 modifiers
506 .addReg(MI->getOperand(2).getReg())
507 .addImm(0) // SRC2 modifiers
511 MI->eraseFromParent();
514 case AMDGPU::SI_RegisterStorePseudo: {
515 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
516 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
517 MachineInstrBuilder MIB =
518 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
520 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
521 MIB.addOperand(MI->getOperand(i));
523 MI->eraseFromParent();
526 case AMDGPU::FABS_SI: {
527 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
528 const SIInstrInfo *TII =
529 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
530 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
531 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
534 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
535 MI->getOperand(0).getReg())
536 .addReg(MI->getOperand(1).getReg())
538 MI->eraseFromParent();
541 case AMDGPU::FNEG_SI: {
542 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
543 const SIInstrInfo *TII =
544 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
545 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
546 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
549 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
550 MI->getOperand(0).getReg())
551 .addReg(MI->getOperand(1).getReg())
553 MI->eraseFromParent();
556 case AMDGPU::FCLAMP_SI: {
557 const SIInstrInfo *TII =
558 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
559 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
560 MI->getOperand(0).getReg())
561 .addImm(0) // SRC0 modifiers
562 .addOperand(MI->getOperand(1))
563 .addImm(0) // SRC1 modifiers
567 MI->eraseFromParent();
573 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
574 if (!VT.isVector()) {
577 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
580 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
584 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
585 VT = VT.getScalarType();
590 switch (VT.getSimpleVT().SimpleTy) {
592 return false; /* There is V_MAD_F32 for f32 */
602 //===----------------------------------------------------------------------===//
603 // Custom DAG Lowering Operations
604 //===----------------------------------------------------------------------===//
606 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
607 MachineFunction &MF = DAG.getMachineFunction();
608 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
609 switch (Op.getOpcode()) {
610 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
611 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
613 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
614 EVT VT = Op.getValueType();
616 // These loads are legal.
617 if (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
618 VT.isVector() && VT.getVectorNumElements() == 2 &&
619 VT.getVectorElementType() == MVT::i32)
622 if (Op.getValueType().isVector() &&
623 (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
624 Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
625 (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
626 Op.getValueType().getVectorNumElements() > 4))) {
627 return SplitVectorLoad(Op, DAG);
629 SDValue Result = LowerLOAD(Op, DAG);
630 assert((!Result.getNode() ||
631 Result.getNode()->getNumValues() == 2) &&
632 "Load should return a value and a chain");
637 case ISD::SELECT: return LowerSELECT(Op, DAG);
638 case ISD::FDIV: return LowerFDIV(Op, DAG);
639 case ISD::STORE: return LowerSTORE(Op, DAG);
640 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
641 case ISD::INTRINSIC_WO_CHAIN: {
642 unsigned IntrinsicID =
643 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
644 EVT VT = Op.getValueType();
646 //XXX: Hardcoded we only use two to store the pointer to the parameters.
647 unsigned NumUserSGPRs = 2;
648 switch (IntrinsicID) {
649 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
650 case Intrinsic::r600_read_ngroups_x:
651 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
652 case Intrinsic::r600_read_ngroups_y:
653 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
654 case Intrinsic::r600_read_ngroups_z:
655 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
656 case Intrinsic::r600_read_global_size_x:
657 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
658 case Intrinsic::r600_read_global_size_y:
659 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
660 case Intrinsic::r600_read_global_size_z:
661 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
662 case Intrinsic::r600_read_local_size_x:
663 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
664 case Intrinsic::r600_read_local_size_y:
665 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
666 case Intrinsic::r600_read_local_size_z:
667 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
668 case Intrinsic::r600_read_tgid_x:
669 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
670 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 0), VT);
671 case Intrinsic::r600_read_tgid_y:
672 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
673 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 1), VT);
674 case Intrinsic::r600_read_tgid_z:
675 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
676 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 2), VT);
677 case Intrinsic::r600_read_tidig_x:
678 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
680 case Intrinsic::r600_read_tidig_y:
681 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
683 case Intrinsic::r600_read_tidig_z:
684 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
686 case AMDGPUIntrinsic::SI_load_const: {
692 MachineMemOperand *MMO = MF.getMachineMemOperand(
693 MachinePointerInfo(),
694 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
695 VT.getSizeInBits() / 8, 4);
696 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
697 Op->getVTList(), Ops, VT, MMO);
699 case AMDGPUIntrinsic::SI_sample:
700 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
701 case AMDGPUIntrinsic::SI_sampleb:
702 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
703 case AMDGPUIntrinsic::SI_sampled:
704 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
705 case AMDGPUIntrinsic::SI_samplel:
706 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
707 case AMDGPUIntrinsic::SI_vs_load_input:
708 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
715 case ISD::INTRINSIC_VOID:
716 SDValue Chain = Op.getOperand(0);
717 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
719 switch (IntrinsicID) {
720 case AMDGPUIntrinsic::SI_tbuffer_store: {
738 EVT VT = Op.getOperand(3).getValueType();
740 MachineMemOperand *MMO = MF.getMachineMemOperand(
741 MachinePointerInfo(),
742 MachineMemOperand::MOStore,
743 VT.getSizeInBits() / 8, 4);
744 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
745 Op->getVTList(), Ops, VT, MMO);
754 /// \brief Helper function for LowerBRCOND
755 static SDNode *findUser(SDValue Value, unsigned Opcode) {
757 SDNode *Parent = Value.getNode();
758 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
761 if (I.getUse().get() != Value)
764 if (I->getOpcode() == Opcode)
770 /// This transforms the control flow intrinsics to get the branch destination as
771 /// last parameter, also switches branch target with BR if the need arise
772 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
773 SelectionDAG &DAG) const {
777 SDNode *Intr = BRCOND.getOperand(1).getNode();
778 SDValue Target = BRCOND.getOperand(2);
779 SDNode *BR = nullptr;
781 if (Intr->getOpcode() == ISD::SETCC) {
782 // As long as we negate the condition everything is fine
783 SDNode *SetCC = Intr;
784 assert(SetCC->getConstantOperandVal(1) == 1);
785 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
787 Intr = SetCC->getOperand(0).getNode();
790 // Get the target from BR if we don't negate the condition
791 BR = findUser(BRCOND, ISD::BR);
792 Target = BR->getOperand(1);
795 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
797 // Build the result and
798 SmallVector<EVT, 4> Res;
799 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
800 Res.push_back(Intr->getValueType(i));
802 // operands of the new intrinsic call
803 SmallVector<SDValue, 4> Ops;
804 Ops.push_back(BRCOND.getOperand(0));
805 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
806 Ops.push_back(Intr->getOperand(i));
807 Ops.push_back(Target);
809 // build the new intrinsic call
810 SDNode *Result = DAG.getNode(
811 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
812 DAG.getVTList(Res), Ops).getNode();
815 // Give the branch instruction our target
820 DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops);
823 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
825 // Copy the intrinsic results to registers
826 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
827 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
831 Chain = DAG.getCopyToReg(
833 CopyToReg->getOperand(1),
834 SDValue(Result, i - 1),
837 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
840 // Remove the old intrinsic from the chain
841 DAG.ReplaceAllUsesOfValueWith(
842 SDValue(Intr, Intr->getNumValues() - 1),
843 Intr->getOperand(0));
848 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
850 LoadSDNode *Load = cast<LoadSDNode>(Op);
851 SDValue Lowered = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
852 if (Lowered.getNode())
855 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
859 EVT MemVT = Load->getMemoryVT();
861 assert(!MemVT.isVector() && "Private loads should be scalarized");
862 assert(!MemVT.isFloatingPoint() && "FP loads should be promoted to int");
864 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
865 DAG.getConstant(2, MVT::i32));
867 // FIXME: REGISTER_LOAD should probably have a chain result.
868 SDValue Chain = Load->getChain();
869 SDValue LoLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
871 DAG.getTargetConstant(0, MVT::i32),
874 SDValue Ret = LoLoad.getValue(0);
875 if (MemVT.getSizeInBits() == 64) {
876 // TODO: This needs a test to make sure the right thing is happening with
877 // the chain. That is hard without general function support.
879 SDValue IncPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
880 DAG.getConstant(1, MVT::i32));
882 SDValue HiLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
884 DAG.getTargetConstant(0, MVT::i32),
887 Ret = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, LoLoad, HiLoad);
888 // Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
889 // LoLoad.getValue(1), HiLoad.getValue(1));
897 return DAG.getMergeValues(Ops, DL);
900 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
902 SelectionDAG &DAG) const {
903 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
909 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
910 if (Op.getValueType() != MVT::i64)
914 SDValue Cond = Op.getOperand(0);
916 SDValue Zero = DAG.getConstant(0, MVT::i32);
917 SDValue One = DAG.getConstant(1, MVT::i32);
919 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
920 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
922 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
923 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
925 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
927 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
928 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
930 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
932 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
933 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
936 static SDValue performUnsafeFDIV(SDValue Op, SelectionDAG &DAG) {
938 SDValue LHS = Op.getOperand(0);
939 SDValue RHS = Op.getOperand(1);
940 EVT VT = Op.getValueType();
942 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
943 if (CLHS->isExactlyValue(1.0)) {
945 // 1.0 / sqrt(x) -> rsq(x)
946 if (RHS.getOpcode() == ISD::FSQRT)
947 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
950 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
954 // Turn into multiply by the reciprocal
955 // x / y -> x * (1.0 / y)
956 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
957 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip);
960 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
961 if (DAG.getTarget().Options.UnsafeFPMath)
962 return performUnsafeFDIV(Op, DAG);
965 SDValue LHS = Op.getOperand(0);
966 SDValue RHS = Op.getOperand(1);
968 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
970 const APFloat K0Val(BitsToFloat(0x6f800000));
971 const SDValue K0 = DAG.getConstantFP(K0Val, MVT::f32);
973 const APFloat K1Val(BitsToFloat(0x2f800000));
974 const SDValue K1 = DAG.getConstantFP(K1Val, MVT::f32);
976 const SDValue One = DAG.getTargetConstantFP(1.0, MVT::f32);
978 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
980 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
982 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
984 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
986 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
988 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
990 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
993 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
997 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
998 EVT VT = Op.getValueType();
1001 return LowerFDIV32(Op, DAG);
1004 return LowerFDIV64(Op, DAG);
1006 llvm_unreachable("Unexpected type for fdiv");
1009 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1011 StoreSDNode *Store = cast<StoreSDNode>(Op);
1012 EVT VT = Store->getMemoryVT();
1014 // These stores are legal.
1015 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
1016 VT.isVector() && VT.getVectorNumElements() == 2 &&
1017 VT.getVectorElementType() == MVT::i32)
1020 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1024 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1025 return SplitVectorStore(Op, DAG);
1028 return DAG.getTruncStore(Store->getChain(), DL,
1029 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1030 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1032 if (Store->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
1035 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Store->getBasePtr(),
1036 DAG.getConstant(2, MVT::i32));
1037 SDValue Chain = Store->getChain();
1038 SmallVector<SDValue, 8> Values;
1040 if (Store->isTruncatingStore()) {
1042 if (Store->getMemoryVT() == MVT::i8) {
1044 } else if (Store->getMemoryVT() == MVT::i16) {
1047 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1048 Chain, Store->getBasePtr(),
1049 DAG.getConstant(0, MVT::i32));
1050 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getBasePtr(),
1051 DAG.getConstant(0x3, MVT::i32));
1052 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1053 DAG.getConstant(3, MVT::i32));
1054 SDValue MaskedValue = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getValue(),
1055 DAG.getConstant(Mask, MVT::i32));
1056 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1057 MaskedValue, ShiftAmt);
1058 SDValue RotrAmt = DAG.getNode(ISD::SUB, DL, MVT::i32,
1059 DAG.getConstant(32, MVT::i32), ShiftAmt);
1060 SDValue DstMask = DAG.getNode(ISD::ROTR, DL, MVT::i32,
1061 DAG.getConstant(Mask, MVT::i32),
1063 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1064 Dst = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1066 Values.push_back(Dst);
1067 } else if (VT == MVT::i64) {
1068 for (unsigned i = 0; i < 2; ++i) {
1069 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
1070 Store->getValue(), DAG.getConstant(i, MVT::i32)));
1072 } else if (VT == MVT::i128) {
1073 for (unsigned i = 0; i < 2; ++i) {
1074 for (unsigned j = 0; j < 2; ++j) {
1075 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
1076 DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64,
1077 Store->getValue(), DAG.getConstant(i, MVT::i32)),
1078 DAG.getConstant(j, MVT::i32)));
1082 Values.push_back(Store->getValue());
1085 for (unsigned i = 0; i < Values.size(); ++i) {
1086 SDValue PartPtr = DAG.getNode(ISD::ADD, DL, MVT::i32,
1087 Ptr, DAG.getConstant(i, MVT::i32));
1088 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1089 Chain, Values[i], PartPtr,
1090 DAG.getTargetConstant(0, MVT::i32));
1095 //===----------------------------------------------------------------------===//
1096 // Custom DAG optimizations
1097 //===----------------------------------------------------------------------===//
1099 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1100 DAGCombinerInfo &DCI) {
1101 EVT VT = N->getValueType(0);
1102 EVT ScalarVT = VT.getScalarType();
1103 if (ScalarVT != MVT::f32)
1106 SelectionDAG &DAG = DCI.DAG;
1109 SDValue Src = N->getOperand(0);
1110 EVT SrcVT = Src.getValueType();
1112 // TODO: We could try to match extracting the higher bytes, which would be
1113 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1114 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1115 // about in practice.
1116 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1117 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1118 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1119 DCI.AddToWorklist(Cvt.getNode());
1124 // We are primarily trying to catch operations on illegal vector types
1125 // before they are expanded.
1126 // For scalars, we can use the more flexible method of checking masked bits
1127 // after legalization.
1128 if (!DCI.isBeforeLegalize() ||
1129 !SrcVT.isVector() ||
1130 SrcVT.getVectorElementType() != MVT::i8) {
1134 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1136 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1138 unsigned NElts = SrcVT.getVectorNumElements();
1139 if (!SrcVT.isSimple() && NElts != 3)
1142 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1143 // prevent a mess from expanding to v4i32 and repacking.
1144 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1145 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1146 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1147 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1149 LoadSDNode *Load = cast<LoadSDNode>(Src);
1150 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1154 Load->getMemOperand());
1156 // Make sure successors of the original load stay after it by updating
1157 // them to use the new Chain.
1158 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1160 SmallVector<SDValue, 4> Elts;
1161 if (RegVT.isVector())
1162 DAG.ExtractVectorElements(NewLoad, Elts);
1164 Elts.push_back(NewLoad);
1166 SmallVector<SDValue, 4> Ops;
1168 unsigned EltIdx = 0;
1169 for (SDValue Elt : Elts) {
1170 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1171 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1172 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1173 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1174 DCI.AddToWorklist(Cvt.getNode());
1181 assert(Ops.size() == NElts);
1183 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1189 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1190 DAGCombinerInfo &DCI) const {
1191 SelectionDAG &DAG = DCI.DAG;
1193 EVT VT = N->getValueType(0);
1195 switch (N->getOpcode()) {
1196 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1197 case ISD::SELECT_CC: {
1198 ConstantSDNode *True, *False;
1199 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
1200 if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1201 && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1202 && True->isAllOnesValue()
1203 && False->isNullValue()
1205 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
1206 N->getOperand(1), N->getOperand(4));
1212 SDValue Arg0 = N->getOperand(0);
1213 SDValue Arg1 = N->getOperand(1);
1214 SDValue CC = N->getOperand(2);
1215 ConstantSDNode * C = nullptr;
1216 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1218 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1220 && Arg0.getOpcode() == ISD::SIGN_EXTEND
1221 && Arg0.getOperand(0).getValueType() == MVT::i1
1222 && (C = dyn_cast<ConstantSDNode>(Arg1))
1224 && CCOp == ISD::SETNE) {
1225 return SimplifySetCC(VT, Arg0.getOperand(0),
1226 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1231 case AMDGPUISD::CVT_F32_UBYTE0:
1232 case AMDGPUISD::CVT_F32_UBYTE1:
1233 case AMDGPUISD::CVT_F32_UBYTE2:
1234 case AMDGPUISD::CVT_F32_UBYTE3: {
1235 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1237 SDValue Src = N->getOperand(0);
1238 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1240 APInt KnownZero, KnownOne;
1241 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1242 !DCI.isBeforeLegalizeOps());
1243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1244 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1245 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1246 DCI.CommitTargetLoweringOpt(TLO);
1252 case ISD::UINT_TO_FP: {
1253 return performUCharToFloatCombine(N, DCI);
1257 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1260 /// \brief Test if RegClass is one of the VSrc classes
1261 static bool isVSrc(unsigned RegClass) {
1262 return AMDGPU::VSrc_32RegClassID == RegClass ||
1263 AMDGPU::VSrc_64RegClassID == RegClass;
1266 /// \brief Test if RegClass is one of the SSrc classes
1267 static bool isSSrc(unsigned RegClass) {
1268 return AMDGPU::SSrc_32RegClassID == RegClass ||
1269 AMDGPU::SSrc_64RegClassID == RegClass;
1272 /// \brief Analyze the possible immediate value Op
1274 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1275 /// and the immediate value if it's a literal immediate
1276 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1283 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1284 if (Node->getZExtValue() >> 32) {
1287 Imm.I = Node->getSExtValue();
1288 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1289 if (N->getValueType(0) != MVT::f32)
1291 Imm.F = Node->getValueAPF().convertToFloat();
1293 return -1; // It isn't an immediate
1295 if ((Imm.I >= -16 && Imm.I <= 64) ||
1296 Imm.F == 0.5f || Imm.F == -0.5f ||
1297 Imm.F == 1.0f || Imm.F == -1.0f ||
1298 Imm.F == 2.0f || Imm.F == -2.0f ||
1299 Imm.F == 4.0f || Imm.F == -4.0f)
1300 return 0; // It's an inline immediate
1302 return Imm.I; // It's a literal immediate
1305 /// \brief Try to fold an immediate directly into an instruction
1306 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1307 bool &ScalarSlotUsed) const {
1309 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1310 const SIInstrInfo *TII =
1311 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1312 if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1315 const SDValue &Op = Mov->getOperand(0);
1316 int32_t Value = analyzeImmediate(Op.getNode());
1318 // Not an immediate at all
1321 } else if (Value == 0) {
1322 // Inline immediates can always be fold
1326 } else if (Value == Immediate) {
1327 // Already fold literal immediate
1331 } else if (!ScalarSlotUsed && !Immediate) {
1332 // Fold this literal immediate
1333 ScalarSlotUsed = true;
1343 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1344 SelectionDAG &DAG, const SDValue &Op) const {
1345 const SIInstrInfo *TII =
1346 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1347 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1349 if (!Op->isMachineOpcode()) {
1350 switch(Op->getOpcode()) {
1351 case ISD::CopyFromReg: {
1352 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1353 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1354 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1355 return MRI.getRegClass(Reg);
1357 return TRI.getPhysRegClass(Reg);
1359 default: return nullptr;
1362 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1363 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1364 if (OpClassID != -1) {
1365 return TRI.getRegClass(OpClassID);
1367 switch(Op.getMachineOpcode()) {
1368 case AMDGPU::COPY_TO_REGCLASS:
1369 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1370 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1372 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1373 // class, then the register class for the value could be either a
1374 // VReg or and SReg. In order to get a more accurate
1375 if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1376 OpClassID == AMDGPU::VSrc_64RegClassID) {
1377 return getRegClassForNode(DAG, Op.getOperand(0));
1379 return TRI.getRegClass(OpClassID);
1380 case AMDGPU::EXTRACT_SUBREG: {
1381 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1382 const TargetRegisterClass *SuperClass =
1383 getRegClassForNode(DAG, Op.getOperand(0));
1384 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1386 case AMDGPU::REG_SEQUENCE:
1387 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1388 return TRI.getRegClass(
1389 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1391 return getRegClassFor(Op.getSimpleValueType());
1395 /// \brief Does "Op" fit into register class "RegClass" ?
1396 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1397 unsigned RegClass) const {
1398 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1399 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1403 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1406 /// \brief Make sure that we don't exeed the number of allowed scalars
1407 void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
1409 bool &ScalarSlotUsed) const {
1411 // First map the operands register class to a destination class
1412 if (RegClass == AMDGPU::VSrc_32RegClassID)
1413 RegClass = AMDGPU::VReg_32RegClassID;
1414 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1415 RegClass = AMDGPU::VReg_64RegClassID;
1419 // Nothing to do if they fit naturally
1420 if (fitsRegClass(DAG, Operand, RegClass))
1423 // If the scalar slot isn't used yet use it now
1424 if (!ScalarSlotUsed) {
1425 ScalarSlotUsed = true;
1429 // This is a conservative aproach. It is possible that we can't determine the
1430 // correct register class and copy too often, but better safe than sorry.
1431 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1432 SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
1433 Operand.getValueType(), Operand, RC);
1434 Operand = SDValue(Node, 0);
1437 /// \returns true if \p Node's operands are different from the SDValue list
1439 static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1440 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1441 if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1448 /// \brief Try to fold the Nodes operands into the Node
1449 SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
1450 SelectionDAG &DAG) const {
1452 // Original encoding (either e32 or e64)
1453 int Opcode = Node->getMachineOpcode();
1454 const SIInstrInfo *TII =
1455 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1456 const MCInstrDesc *Desc = &TII->get(Opcode);
1458 unsigned NumDefs = Desc->getNumDefs();
1459 unsigned NumOps = Desc->getNumOperands();
1461 // Commuted opcode if available
1462 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1463 const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1465 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1466 assert(!DescRev || DescRev->getNumOperands() == NumOps);
1468 // e64 version if available, -1 otherwise
1469 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1470 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
1471 int InputModifiers[3] = {0};
1473 assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
1475 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1476 bool HaveVSrc = false, HaveSSrc = false;
1478 // First figure out what we already have in this instruction.
1479 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1480 i != e && Op < NumOps; ++i, ++Op) {
1482 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1483 if (isVSrc(RegClass))
1485 else if (isSSrc(RegClass))
1490 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1491 if (Imm != -1 && Imm != 0) {
1492 // Literal immediate
1497 // If we neither have VSrc nor SSrc, it makes no sense to continue.
1498 if (!HaveVSrc && !HaveSSrc)
1501 // No scalar allowed when we have both VSrc and SSrc
1502 bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1504 // Second go over the operands and try to fold them
1505 std::vector<SDValue> Ops;
1506 bool Promote2e64 = false;
1507 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1508 i != e && Op < NumOps; ++i, ++Op) {
1510 const SDValue &Operand = Node->getOperand(i);
1511 Ops.push_back(Operand);
1513 // Already folded immediate?
1514 if (isa<ConstantSDNode>(Operand.getNode()) ||
1515 isa<ConstantFPSDNode>(Operand.getNode()))
1518 // Is this a VSrc or SSrc operand?
1519 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1520 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1521 // Try to fold the immediates
1522 if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
1523 // Folding didn't work, make sure we don't hit the SReg limit.
1524 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1529 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1531 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1532 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1534 // Test if it makes sense to swap operands
1535 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1536 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1537 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1539 // Swap commutable operands
1540 std::swap(Ops[0], Ops[1]);
1552 // Test if it makes sense to switch to e64 encoding
1553 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1554 if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
1557 int32_t TmpImm = -1;
1558 if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
1559 (!fitsRegClass(DAG, Ops[i], RegClass) &&
1560 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1562 // Switch to e64 encoding
1570 if (!DescE64 && !Promote2e64)
1572 if (!Operand.isMachineOpcode())
1574 if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) {
1576 Ops.push_back(Operand.getOperand(0));
1577 InputModifiers[i] = 1;
1584 else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) {
1586 Ops.push_back(Operand.getOperand(0));
1587 InputModifiers[i] = 2;
1597 std::vector<SDValue> OldOps(Ops);
1599 for (unsigned i = 0; i < OldOps.size(); ++i) {
1601 Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
1602 Ops.push_back(OldOps[i]);
1604 // Add the modifier flags while promoting
1605 for (unsigned i = 0; i < 2; ++i)
1606 Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
1609 // Add optional chain and glue
1610 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1611 Ops.push_back(Node->getOperand(i));
1613 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1614 // this case a brand new node is always be created, even if the operands
1615 // are the same as before. So, manually check if anything has been changed.
1616 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1620 // Create a complete new instruction
1621 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1624 /// \brief Helper function for adjustWritemask
1625 static unsigned SubIdx2Lane(unsigned Idx) {
1628 case AMDGPU::sub0: return 0;
1629 case AMDGPU::sub1: return 1;
1630 case AMDGPU::sub2: return 2;
1631 case AMDGPU::sub3: return 3;
1635 /// \brief Adjust the writemask of MIMG instructions
1636 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1637 SelectionDAG &DAG) const {
1638 SDNode *Users[4] = { };
1640 unsigned OldDmask = Node->getConstantOperandVal(0);
1641 unsigned NewDmask = 0;
1643 // Try to figure out the used register components
1644 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1647 // Abort if we can't understand the usage
1648 if (!I->isMachineOpcode() ||
1649 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1652 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1653 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1654 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1656 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1658 // Set which texture component corresponds to the lane.
1660 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1662 Comp = countTrailingZeros(Dmask);
1663 Dmask &= ~(1 << Comp);
1666 // Abort if we have more than one user per component
1671 NewDmask |= 1 << Comp;
1674 // Abort if there's no change
1675 if (NewDmask == OldDmask)
1678 // Adjust the writemask in the node
1679 std::vector<SDValue> Ops;
1680 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1681 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1682 Ops.push_back(Node->getOperand(i));
1683 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1685 // If we only got one lane, replace it with a copy
1686 // (if NewDmask has only one bit set...)
1687 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1688 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1689 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1690 SDLoc(), Users[Lane]->getValueType(0),
1691 SDValue(Node, 0), RC);
1692 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1696 // Update the users of the node with the new indices
1697 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1699 SDNode *User = Users[i];
1703 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1704 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1708 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1709 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1710 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1715 /// \brief Fold the instructions after selecting them.
1716 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1717 SelectionDAG &DAG) const {
1718 const SIInstrInfo *TII =
1719 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1720 Node = AdjustRegClass(Node, DAG);
1722 if (TII->isMIMG(Node->getMachineOpcode()))
1723 adjustWritemask(Node, DAG);
1725 return foldOperands(Node, DAG);
1728 /// \brief Assign the register class depending on the number of
1729 /// bits set in the writemask
1730 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1731 SDNode *Node) const {
1732 const SIInstrInfo *TII =
1733 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1734 if (!TII->isMIMG(MI->getOpcode()))
1737 unsigned VReg = MI->getOperand(0).getReg();
1738 unsigned Writemask = MI->getOperand(1).getImm();
1739 unsigned BitsSet = 0;
1740 for (unsigned i = 0; i < 4; ++i)
1741 BitsSet += Writemask & (1 << i) ? 1 : 0;
1743 const TargetRegisterClass *RC;
1746 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1747 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1748 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1751 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1752 MI->setDesc(TII->get(NewOpcode));
1753 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1754 MRI.setRegClass(VReg, RC);
1757 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1758 SelectionDAG &DAG) const {
1761 unsigned NewOpcode = N->getMachineOpcode();
1763 switch (N->getMachineOpcode()) {
1765 case AMDGPU::S_LOAD_DWORD_IMM:
1766 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1768 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1769 if (NewOpcode == N->getMachineOpcode()) {
1770 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1773 case AMDGPU::S_LOAD_DWORDX4_IMM:
1774 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1775 if (NewOpcode == N->getMachineOpcode()) {
1776 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1778 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1781 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
1783 SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
1784 DAG.getConstant(0, MVT::i64)), 0),
1786 DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
1788 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
1793 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1794 const TargetRegisterClass *RC,
1795 unsigned Reg, EVT VT) const {
1796 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1798 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1799 cast<RegisterSDNode>(VReg)->getReg(), VT);