1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUIntrinsicInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAG.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/ADT/SmallString.h"
37 SITargetLowering::SITargetLowering(TargetMachine &TM) :
38 AMDGPUTargetLowering(TM) {
39 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
40 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
42 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
43 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
45 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
46 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
48 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
49 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
50 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
52 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
53 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
55 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
56 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
58 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
59 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
61 computeRegisterProperties();
64 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
65 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
66 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
67 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
68 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
69 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
71 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
72 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
73 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
74 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
75 setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
76 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
78 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
79 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
80 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
81 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
83 setOperationAction(ISD::ADD, MVT::i32, Legal);
84 setOperationAction(ISD::ADDC, MVT::i32, Legal);
85 setOperationAction(ISD::ADDE, MVT::i32, Legal);
86 setOperationAction(ISD::SUBC, MVT::i32, Legal);
87 setOperationAction(ISD::SUBE, MVT::i32, Legal);
89 setOperationAction(ISD::FSIN, MVT::f32, Custom);
90 setOperationAction(ISD::FCOS, MVT::f32, Custom);
92 // We need to custom lower vector stores from local memory
93 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
94 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
95 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
96 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
98 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
99 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
101 // We need to custom lower loads/stores from private memory
102 setOperationAction(ISD::LOAD, MVT::i32, Custom);
103 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
104 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
105 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
107 setOperationAction(ISD::STORE, MVT::i1, Custom);
108 setOperationAction(ISD::STORE, MVT::i32, Custom);
109 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
110 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
112 setOperationAction(ISD::SELECT, MVT::f32, Promote);
113 AddPromotedToType(ISD::SELECT, MVT::f32, MVT::i32);
114 setOperationAction(ISD::SELECT, MVT::i64, Custom);
115 setOperationAction(ISD::SELECT, MVT::f64, Promote);
116 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
118 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
119 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
120 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
121 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
123 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
124 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
128 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
134 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
135 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
136 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
142 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
143 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
144 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
145 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
147 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
148 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
150 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
151 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
152 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
153 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
154 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
155 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
157 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
158 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
159 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
160 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
162 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
163 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
164 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
165 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
166 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
168 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
169 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
170 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
171 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
172 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
173 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
175 setOperationAction(ISD::LOAD, MVT::i1, Custom);
177 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
178 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
180 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
181 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
182 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
184 // These should use UDIVREM, so set them to expand
185 setOperationAction(ISD::UDIV, MVT::i64, Expand);
186 setOperationAction(ISD::UREM, MVT::i64, Expand);
188 // We only support LOAD/STORE and vector manipulation ops for vectors
189 // with > 4 elements.
191 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
194 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
195 setOperationAction(ISD::SELECT, MVT::i1, Promote);
197 for (MVT VT : VecTypes) {
198 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
202 case ISD::BUILD_VECTOR:
204 case ISD::EXTRACT_VECTOR_ELT:
205 case ISD::INSERT_VECTOR_ELT:
206 case ISD::CONCAT_VECTORS:
207 case ISD::INSERT_SUBVECTOR:
208 case ISD::EXTRACT_SUBVECTOR:
211 setOperationAction(Op, VT, Expand);
217 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
218 MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
219 setOperationAction(ISD::FTRUNC, VT, Expand);
220 setOperationAction(ISD::FCEIL, VT, Expand);
221 setOperationAction(ISD::FFLOOR, VT, Expand);
224 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
225 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
226 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
227 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
228 setOperationAction(ISD::FRINT, MVT::f64, Legal);
231 // FIXME: These should be removed and handled the same was as f32 fneg. Source
232 // modifiers also work for the double instructions.
233 setOperationAction(ISD::FNEG, MVT::f64, Expand);
234 setOperationAction(ISD::FABS, MVT::f64, Expand);
236 setOperationAction(ISD::FDIV, MVT::f32, Custom);
238 setTargetDAGCombine(ISD::SELECT_CC);
239 setTargetDAGCombine(ISD::SETCC);
241 setTargetDAGCombine(ISD::UINT_TO_FP);
243 setSchedulingPreference(Sched::RegPressure);
246 //===----------------------------------------------------------------------===//
247 // TargetLowering queries
248 //===----------------------------------------------------------------------===//
250 bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
252 bool *IsFast) const {
256 // XXX: This depends on the address space and also we may want to revist
257 // the alignment values we specify in the DataLayout.
259 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
260 // which isn't a simple VT.
261 if (!VT.isSimple() || VT == MVT::Other)
264 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
265 // see what for specifically. The wording everywhere else seems to be the
268 // 3.6.4 - Operations using pairs of VGPRs (for example: double-floats) have
269 // no alignment restrictions.
270 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
271 // Using any pair of GPRs should be the same as any other pair.
274 return VT.bitsGE(MVT::i64);
277 // XXX - The only mention I see of this in the ISA manual is for LDS direct
278 // reads the "byte address and must be dword aligned". Is it also true for the
279 // normal loads and stores?
280 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
283 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
284 // byte-address are ignored, thus forcing Dword alignment.
287 return VT.bitsGT(MVT::i32);
290 TargetLoweringBase::LegalizeTypeAction
291 SITargetLowering::getPreferredVectorAction(EVT VT) const {
292 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
293 return TypeSplitVector;
295 return TargetLoweringBase::getPreferredVectorAction(VT);
298 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
300 const SIInstrInfo *TII =
301 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
302 return TII->isInlineConstant(Imm);
305 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
306 SDLoc DL, SDValue Chain,
307 unsigned Offset, bool Signed) const {
308 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
309 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
310 AMDGPUAS::CONSTANT_ADDRESS);
311 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
312 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
313 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
314 DAG.getConstant(Offset, MVT::i64));
315 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
316 MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
317 false, false, MemVT.getSizeInBits() >> 3);
321 SDValue SITargetLowering::LowerFormalArguments(
323 CallingConv::ID CallConv,
325 const SmallVectorImpl<ISD::InputArg> &Ins,
326 SDLoc DL, SelectionDAG &DAG,
327 SmallVectorImpl<SDValue> &InVals) const {
329 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
331 MachineFunction &MF = DAG.getMachineFunction();
332 FunctionType *FType = MF.getFunction()->getFunctionType();
333 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
335 assert(CallConv == CallingConv::C);
337 SmallVector<ISD::InputArg, 16> Splits;
338 uint32_t Skipped = 0;
340 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
341 const ISD::InputArg &Arg = Ins[i];
343 // First check if it's a PS input addr
344 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
345 !Arg.Flags.isByVal()) {
347 assert((PSInputNum <= 15) && "Too many PS inputs!");
350 // We can savely skip PS inputs
356 Info->PSInputAddr |= 1 << PSInputNum++;
359 // Second split vertices into their elements
360 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
361 ISD::InputArg NewArg = Arg;
362 NewArg.Flags.setSplit();
363 NewArg.VT = Arg.VT.getVectorElementType();
365 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
366 // three or five element vertex only needs three or five registers,
367 // NOT four or eigth.
368 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
369 unsigned NumElements = ParamType->getVectorNumElements();
371 for (unsigned j = 0; j != NumElements; ++j) {
372 Splits.push_back(NewArg);
373 NewArg.PartOffset += NewArg.VT.getStoreSize();
376 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
377 Splits.push_back(Arg);
381 SmallVector<CCValAssign, 16> ArgLocs;
382 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
383 getTargetMachine(), ArgLocs, *DAG.getContext());
385 // At least one interpolation mode must be enabled or else the GPU will hang.
386 if (Info->getShaderType() == ShaderType::PIXEL &&
387 (Info->PSInputAddr & 0x7F) == 0) {
388 Info->PSInputAddr |= 1;
389 CCInfo.AllocateReg(AMDGPU::VGPR0);
390 CCInfo.AllocateReg(AMDGPU::VGPR1);
393 // The pointer to the list of arguments is stored in SGPR0, SGPR1
394 // The pointer to the scratch buffer is stored in SGPR2, SGPR3
395 if (Info->getShaderType() == ShaderType::COMPUTE) {
396 Info->NumUserSGPRs = 4;
397 CCInfo.AllocateReg(AMDGPU::SGPR0);
398 CCInfo.AllocateReg(AMDGPU::SGPR1);
399 CCInfo.AllocateReg(AMDGPU::SGPR2);
400 CCInfo.AllocateReg(AMDGPU::SGPR3);
401 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
402 MF.addLiveIn(AMDGPU::SGPR2_SGPR3, &AMDGPU::SReg_64RegClass);
405 if (Info->getShaderType() == ShaderType::COMPUTE) {
406 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
410 AnalyzeFormalArguments(CCInfo, Splits);
412 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
414 const ISD::InputArg &Arg = Ins[i];
415 if (Skipped & (1 << i)) {
416 InVals.push_back(DAG.getUNDEF(Arg.VT));
420 CCValAssign &VA = ArgLocs[ArgIdx++];
421 EVT VT = VA.getLocVT();
425 EVT MemVT = Splits[i].VT;
426 // The first 36 bytes of the input buffer contains information about
427 // thread group and global sizes.
428 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
429 36 + VA.getLocMemOffset(),
430 Ins[i].Flags.isSExt());
431 InVals.push_back(Arg);
434 assert(VA.isRegLoc() && "Parameter must be in a register!");
436 unsigned Reg = VA.getLocReg();
438 if (VT == MVT::i64) {
439 // For now assume it is a pointer
440 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
441 &AMDGPU::SReg_64RegClass);
442 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
443 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
447 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
449 Reg = MF.addLiveIn(Reg, RC);
450 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
452 if (Arg.VT.isVector()) {
454 // Build a vector from the registers
455 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
456 unsigned NumElements = ParamType->getVectorNumElements();
458 SmallVector<SDValue, 4> Regs;
460 for (unsigned j = 1; j != NumElements; ++j) {
461 Reg = ArgLocs[ArgIdx++].getLocReg();
462 Reg = MF.addLiveIn(Reg, RC);
463 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
466 // Fill up the missing vector elements
467 NumElements = Arg.VT.getVectorNumElements() - NumElements;
468 for (unsigned j = 0; j != NumElements; ++j)
469 Regs.push_back(DAG.getUNDEF(VT));
471 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
475 InVals.push_back(Val);
480 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
481 MachineInstr * MI, MachineBasicBlock * BB) const {
483 MachineBasicBlock::iterator I = *MI;
484 const SIInstrInfo *TII =
485 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
486 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
488 switch (MI->getOpcode()) {
490 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
491 case AMDGPU::BRANCH: return BB;
492 case AMDGPU::SI_ADDR64_RSRC: {
493 unsigned SuperReg = MI->getOperand(0).getReg();
494 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
495 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
496 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
497 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
498 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
499 .addOperand(MI->getOperand(1));
500 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
502 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
503 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
504 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
506 .addImm(AMDGPU::sub0)
508 .addImm(AMDGPU::sub1);
509 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
511 .addImm(AMDGPU::sub0_sub1)
513 .addImm(AMDGPU::sub2_sub3);
514 MI->eraseFromParent();
517 case AMDGPU::SI_BUFFER_RSRC: {
518 unsigned SuperReg = MI->getOperand(0).getReg();
520 for (unsigned i = 0, e = 4; i < e; ++i) {
521 MachineOperand &Arg = MI->getOperand(i + 1);
524 Args[i] = Arg.getReg();
529 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
530 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), Reg)
531 .addImm(Arg.getImm());
534 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE),
537 .addImm(AMDGPU::sub0)
539 .addImm(AMDGPU::sub1)
541 .addImm(AMDGPU::sub2)
543 .addImm(AMDGPU::sub3);
544 MI->eraseFromParent();
547 case AMDGPU::V_SUB_F64: {
548 unsigned DestReg = MI->getOperand(0).getReg();
549 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
550 .addImm(0) // SRC0 modifiers
551 .addReg(MI->getOperand(1).getReg())
552 .addImm(1) // SRC1 modifiers
553 .addReg(MI->getOperand(2).getReg())
554 .addImm(0) // SRC2 modifiers
558 MI->eraseFromParent();
561 case AMDGPU::SI_RegisterStorePseudo: {
562 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
563 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
564 MachineInstrBuilder MIB =
565 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
567 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
568 MIB.addOperand(MI->getOperand(i));
570 MI->eraseFromParent();
573 case AMDGPU::FABS_SI: {
574 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
575 const SIInstrInfo *TII =
576 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
577 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
578 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
581 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
582 MI->getOperand(0).getReg())
583 .addReg(MI->getOperand(1).getReg())
585 MI->eraseFromParent();
588 case AMDGPU::FNEG_SI: {
589 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
590 const SIInstrInfo *TII =
591 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
592 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
593 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
596 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
597 MI->getOperand(0).getReg())
598 .addReg(MI->getOperand(1).getReg())
600 MI->eraseFromParent();
603 case AMDGPU::FCLAMP_SI: {
604 const SIInstrInfo *TII =
605 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
606 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
607 MI->getOperand(0).getReg())
608 .addImm(0) // SRC0 modifiers
609 .addOperand(MI->getOperand(1))
610 .addImm(0) // SRC1 modifiers
614 MI->eraseFromParent();
620 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
621 if (!VT.isVector()) {
624 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
627 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
631 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
632 VT = VT.getScalarType();
637 switch (VT.getSimpleVT().SimpleTy) {
639 return false; /* There is V_MAD_F32 for f32 */
649 //===----------------------------------------------------------------------===//
650 // Custom DAG Lowering Operations
651 //===----------------------------------------------------------------------===//
653 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
654 MachineFunction &MF = DAG.getMachineFunction();
655 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
656 switch (Op.getOpcode()) {
657 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
658 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
659 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
661 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
662 EVT VT = Op.getValueType();
664 // These loads are legal.
665 if (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
666 VT.isVector() && VT.getVectorNumElements() == 2 &&
667 VT.getVectorElementType() == MVT::i32)
670 if (Op.getValueType().isVector() &&
671 (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
672 Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
673 (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
674 Op.getValueType().getVectorNumElements() > 4))) {
675 return SplitVectorLoad(Op, DAG);
677 SDValue Result = LowerLOAD(Op, DAG);
678 assert((!Result.getNode() ||
679 Result.getNode()->getNumValues() == 2) &&
680 "Load should return a value and a chain");
687 return LowerTrig(Op, DAG);
688 case ISD::SELECT: return LowerSELECT(Op, DAG);
689 case ISD::FDIV: return LowerFDIV(Op, DAG);
690 case ISD::STORE: return LowerSTORE(Op, DAG);
691 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
692 case ISD::INTRINSIC_WO_CHAIN: {
693 unsigned IntrinsicID =
694 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
695 EVT VT = Op.getValueType();
697 switch (IntrinsicID) {
698 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
699 case Intrinsic::r600_read_ngroups_x:
700 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
701 case Intrinsic::r600_read_ngroups_y:
702 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
703 case Intrinsic::r600_read_ngroups_z:
704 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
705 case Intrinsic::r600_read_global_size_x:
706 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
707 case Intrinsic::r600_read_global_size_y:
708 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
709 case Intrinsic::r600_read_global_size_z:
710 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
711 case Intrinsic::r600_read_local_size_x:
712 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
713 case Intrinsic::r600_read_local_size_y:
714 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
715 case Intrinsic::r600_read_local_size_z:
716 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
717 case Intrinsic::r600_read_tgid_x:
718 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
719 AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0), VT);
720 case Intrinsic::r600_read_tgid_y:
721 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
722 AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1), VT);
723 case Intrinsic::r600_read_tgid_z:
724 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
725 AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2), VT);
726 case Intrinsic::r600_read_tidig_x:
727 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
729 case Intrinsic::r600_read_tidig_y:
730 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
732 case Intrinsic::r600_read_tidig_z:
733 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
735 case AMDGPUIntrinsic::SI_load_const: {
741 MachineMemOperand *MMO = MF.getMachineMemOperand(
742 MachinePointerInfo(),
743 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
744 VT.getSizeInBits() / 8, 4);
745 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
746 Op->getVTList(), Ops, VT, MMO);
748 case AMDGPUIntrinsic::SI_sample:
749 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
750 case AMDGPUIntrinsic::SI_sampleb:
751 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
752 case AMDGPUIntrinsic::SI_sampled:
753 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
754 case AMDGPUIntrinsic::SI_samplel:
755 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
756 case AMDGPUIntrinsic::SI_vs_load_input:
757 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
764 case ISD::INTRINSIC_VOID:
765 SDValue Chain = Op.getOperand(0);
766 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
768 switch (IntrinsicID) {
769 case AMDGPUIntrinsic::SI_tbuffer_store: {
787 EVT VT = Op.getOperand(3).getValueType();
789 MachineMemOperand *MMO = MF.getMachineMemOperand(
790 MachinePointerInfo(),
791 MachineMemOperand::MOStore,
792 VT.getSizeInBits() / 8, 4);
793 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
794 Op->getVTList(), Ops, VT, MMO);
803 /// \brief Helper function for LowerBRCOND
804 static SDNode *findUser(SDValue Value, unsigned Opcode) {
806 SDNode *Parent = Value.getNode();
807 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
810 if (I.getUse().get() != Value)
813 if (I->getOpcode() == Opcode)
819 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
821 MachineFunction &MF = DAG.getMachineFunction();
822 const SIInstrInfo *TII =
823 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
824 const SIRegisterInfo &TRI = TII->getRegisterInfo();
825 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
826 unsigned FrameIndex = FINode->getIndex();
828 CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
829 TRI.getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET), MVT::i32);
831 return DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
834 /// This transforms the control flow intrinsics to get the branch destination as
835 /// last parameter, also switches branch target with BR if the need arise
836 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
837 SelectionDAG &DAG) const {
841 SDNode *Intr = BRCOND.getOperand(1).getNode();
842 SDValue Target = BRCOND.getOperand(2);
843 SDNode *BR = nullptr;
845 if (Intr->getOpcode() == ISD::SETCC) {
846 // As long as we negate the condition everything is fine
847 SDNode *SetCC = Intr;
848 assert(SetCC->getConstantOperandVal(1) == 1);
849 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
851 Intr = SetCC->getOperand(0).getNode();
854 // Get the target from BR if we don't negate the condition
855 BR = findUser(BRCOND, ISD::BR);
856 Target = BR->getOperand(1);
859 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
861 // Build the result and
862 SmallVector<EVT, 4> Res;
863 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
864 Res.push_back(Intr->getValueType(i));
866 // operands of the new intrinsic call
867 SmallVector<SDValue, 4> Ops;
868 Ops.push_back(BRCOND.getOperand(0));
869 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
870 Ops.push_back(Intr->getOperand(i));
871 Ops.push_back(Target);
873 // build the new intrinsic call
874 SDNode *Result = DAG.getNode(
875 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
876 DAG.getVTList(Res), Ops).getNode();
879 // Give the branch instruction our target
884 DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops);
887 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
889 // Copy the intrinsic results to registers
890 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
891 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
895 Chain = DAG.getCopyToReg(
897 CopyToReg->getOperand(1),
898 SDValue(Result, i - 1),
901 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
904 // Remove the old intrinsic from the chain
905 DAG.ReplaceAllUsesOfValueWith(
906 SDValue(Intr, Intr->getNumValues() - 1),
907 Intr->getOperand(0));
912 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
914 SelectionDAG &DAG) const {
915 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
917 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
918 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
921 const GlobalValue *GV = GSD->getGlobal();
922 MVT PtrVT = getPointerTy(GSD->getAddressSpace());
924 SDValue Ptr = DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT);
925 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
927 SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
928 DAG.getConstant(0, MVT::i32));
929 SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
930 DAG.getConstant(1, MVT::i32));
932 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
934 SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue),
935 PtrHi, DAG.getConstant(0, MVT::i32),
936 SDValue(Lo.getNode(), 1));
937 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
940 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
942 LoadSDNode *Load = cast<LoadSDNode>(Op);
943 // Vector private memory loads have already been split, and
944 // all the rest of private memory loads are legal.
945 if (Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
948 SDValue Lowered = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
949 if (Lowered.getNode())
952 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
956 EVT MemVT = Load->getMemoryVT();
958 assert(!MemVT.isVector() && "Private loads should be scalarized");
959 assert(!MemVT.isFloatingPoint() && "FP loads should be promoted to int");
961 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
962 DAG.getConstant(2, MVT::i32));
964 // FIXME: REGISTER_LOAD should probably have a chain result.
965 SDValue Chain = Load->getChain();
966 SDValue LoLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
968 DAG.getTargetConstant(0, MVT::i32),
971 SDValue Ret = LoLoad.getValue(0);
972 if (MemVT.getSizeInBits() == 64) {
973 // TODO: This needs a test to make sure the right thing is happening with
974 // the chain. That is hard without general function support.
976 SDValue IncPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
977 DAG.getConstant(1, MVT::i32));
979 SDValue HiLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
981 DAG.getTargetConstant(0, MVT::i32),
984 Ret = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, LoLoad, HiLoad);
985 // Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
986 // LoLoad.getValue(1), HiLoad.getValue(1));
994 return DAG.getMergeValues(Ops, DL);
997 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
999 SelectionDAG &DAG) const {
1000 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
1006 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1007 if (Op.getValueType() != MVT::i64)
1011 SDValue Cond = Op.getOperand(0);
1013 SDValue Zero = DAG.getConstant(0, MVT::i32);
1014 SDValue One = DAG.getConstant(1, MVT::i32);
1016 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1017 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1019 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1020 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1022 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1024 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1025 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1027 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1029 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1030 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1033 // Catch division cases where we can use shortcuts with rcp and rsq
1035 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1037 SDValue LHS = Op.getOperand(0);
1038 SDValue RHS = Op.getOperand(1);
1039 EVT VT = Op.getValueType();
1040 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1042 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1043 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1044 CLHS->isExactlyValue(1.0)) {
1045 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1046 // the CI documentation has a worst case error of 1 ulp.
1047 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1048 // use it as long as we aren't trying to use denormals.
1050 // 1.0 / sqrt(x) -> rsq(x)
1052 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1053 // error seems really high at 2^29 ULP.
1054 if (RHS.getOpcode() == ISD::FSQRT)
1055 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1057 // 1.0 / x -> rcp(x)
1058 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1063 // Turn into multiply by the reciprocal.
1064 // x / y -> x * (1.0 / y)
1065 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1066 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip);
1072 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1073 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1074 if (FastLowered.getNode())
1077 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1078 // selection error for now rather than do something incorrect.
1079 if (Subtarget->hasFP32Denormals())
1083 SDValue LHS = Op.getOperand(0);
1084 SDValue RHS = Op.getOperand(1);
1086 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1088 const APFloat K0Val(BitsToFloat(0x6f800000));
1089 const SDValue K0 = DAG.getConstantFP(K0Val, MVT::f32);
1091 const APFloat K1Val(BitsToFloat(0x2f800000));
1092 const SDValue K1 = DAG.getConstantFP(K1Val, MVT::f32);
1094 const SDValue One = DAG.getTargetConstantFP(1.0, MVT::f32);
1096 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
1098 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1100 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1102 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1104 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1106 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1108 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1111 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1115 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1116 EVT VT = Op.getValueType();
1119 return LowerFDIV32(Op, DAG);
1122 return LowerFDIV64(Op, DAG);
1124 llvm_unreachable("Unexpected type for fdiv");
1127 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1129 StoreSDNode *Store = cast<StoreSDNode>(Op);
1130 EVT VT = Store->getMemoryVT();
1132 // These stores are legal.
1133 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
1134 VT.isVector() && VT.getVectorNumElements() == 2 &&
1135 VT.getVectorElementType() == MVT::i32)
1138 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1139 if (VT.isVector() && VT.getVectorNumElements() > 4)
1140 return SplitVectorStore(Op, DAG);
1144 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1148 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1149 return SplitVectorStore(Op, DAG);
1152 return DAG.getTruncStore(Store->getChain(), DL,
1153 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1154 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1156 if (Store->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
1159 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Store->getBasePtr(),
1160 DAG.getConstant(2, MVT::i32));
1161 SDValue Chain = Store->getChain();
1162 SmallVector<SDValue, 8> Values;
1164 if (Store->isTruncatingStore()) {
1166 if (Store->getMemoryVT() == MVT::i8) {
1168 } else if (Store->getMemoryVT() == MVT::i16) {
1171 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1172 Chain, Store->getBasePtr(),
1173 DAG.getConstant(0, MVT::i32));
1174 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getBasePtr(),
1175 DAG.getConstant(0x3, MVT::i32));
1176 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1177 DAG.getConstant(3, MVT::i32));
1178 SDValue MaskedValue = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getValue(),
1179 DAG.getConstant(Mask, MVT::i32));
1180 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1181 MaskedValue, ShiftAmt);
1182 SDValue RotrAmt = DAG.getNode(ISD::SUB, DL, MVT::i32,
1183 DAG.getConstant(32, MVT::i32), ShiftAmt);
1184 SDValue DstMask = DAG.getNode(ISD::ROTR, DL, MVT::i32,
1185 DAG.getConstant(Mask, MVT::i32),
1187 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1188 Dst = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1190 Values.push_back(Dst);
1191 } else if (VT == MVT::i64) {
1192 for (unsigned i = 0; i < 2; ++i) {
1193 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
1194 Store->getValue(), DAG.getConstant(i, MVT::i32)));
1196 } else if (VT == MVT::i128) {
1197 for (unsigned i = 0; i < 2; ++i) {
1198 for (unsigned j = 0; j < 2; ++j) {
1199 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
1200 DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64,
1201 Store->getValue(), DAG.getConstant(i, MVT::i32)),
1202 DAG.getConstant(j, MVT::i32)));
1206 Values.push_back(Store->getValue());
1209 for (unsigned i = 0; i < Values.size(); ++i) {
1210 SDValue PartPtr = DAG.getNode(ISD::ADD, DL, MVT::i32,
1211 Ptr, DAG.getConstant(i, MVT::i32));
1212 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1213 Chain, Values[i], PartPtr,
1214 DAG.getTargetConstant(0, MVT::i32));
1219 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1220 EVT VT = Op.getValueType();
1221 SDValue Arg = Op.getOperand(0);
1222 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
1223 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
1224 DAG.getConstantFP(0.5 / M_PI, VT)));
1226 switch (Op.getOpcode()) {
1228 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1230 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1232 llvm_unreachable("Wrong trig opcode");
1236 //===----------------------------------------------------------------------===//
1237 // Custom DAG optimizations
1238 //===----------------------------------------------------------------------===//
1240 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1241 DAGCombinerInfo &DCI) {
1242 EVT VT = N->getValueType(0);
1243 EVT ScalarVT = VT.getScalarType();
1244 if (ScalarVT != MVT::f32)
1247 SelectionDAG &DAG = DCI.DAG;
1250 SDValue Src = N->getOperand(0);
1251 EVT SrcVT = Src.getValueType();
1253 // TODO: We could try to match extracting the higher bytes, which would be
1254 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1255 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1256 // about in practice.
1257 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1258 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1259 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1260 DCI.AddToWorklist(Cvt.getNode());
1265 // We are primarily trying to catch operations on illegal vector types
1266 // before they are expanded.
1267 // For scalars, we can use the more flexible method of checking masked bits
1268 // after legalization.
1269 if (!DCI.isBeforeLegalize() ||
1270 !SrcVT.isVector() ||
1271 SrcVT.getVectorElementType() != MVT::i8) {
1275 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1277 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1279 unsigned NElts = SrcVT.getVectorNumElements();
1280 if (!SrcVT.isSimple() && NElts != 3)
1283 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1284 // prevent a mess from expanding to v4i32 and repacking.
1285 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1286 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1287 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1288 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1290 LoadSDNode *Load = cast<LoadSDNode>(Src);
1291 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1295 Load->getMemOperand());
1297 // Make sure successors of the original load stay after it by updating
1298 // them to use the new Chain.
1299 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1301 SmallVector<SDValue, 4> Elts;
1302 if (RegVT.isVector())
1303 DAG.ExtractVectorElements(NewLoad, Elts);
1305 Elts.push_back(NewLoad);
1307 SmallVector<SDValue, 4> Ops;
1309 unsigned EltIdx = 0;
1310 for (SDValue Elt : Elts) {
1311 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1312 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1313 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1314 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1315 DCI.AddToWorklist(Cvt.getNode());
1322 assert(Ops.size() == NElts);
1324 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1330 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1331 DAGCombinerInfo &DCI) const {
1332 SelectionDAG &DAG = DCI.DAG;
1334 EVT VT = N->getValueType(0);
1336 switch (N->getOpcode()) {
1337 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1339 SDValue Arg0 = N->getOperand(0);
1340 SDValue Arg1 = N->getOperand(1);
1341 SDValue CC = N->getOperand(2);
1342 ConstantSDNode * C = nullptr;
1343 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1345 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1347 && Arg0.getOpcode() == ISD::SIGN_EXTEND
1348 && Arg0.getOperand(0).getValueType() == MVT::i1
1349 && (C = dyn_cast<ConstantSDNode>(Arg1))
1351 && CCOp == ISD::SETNE) {
1352 return SimplifySetCC(VT, Arg0.getOperand(0),
1353 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1358 case AMDGPUISD::CVT_F32_UBYTE0:
1359 case AMDGPUISD::CVT_F32_UBYTE1:
1360 case AMDGPUISD::CVT_F32_UBYTE2:
1361 case AMDGPUISD::CVT_F32_UBYTE3: {
1362 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1364 SDValue Src = N->getOperand(0);
1365 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1367 APInt KnownZero, KnownOne;
1368 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1369 !DCI.isBeforeLegalizeOps());
1370 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1371 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1372 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1373 DCI.CommitTargetLoweringOpt(TLO);
1379 case ISD::UINT_TO_FP: {
1380 return performUCharToFloatCombine(N, DCI);
1384 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1387 /// \brief Test if RegClass is one of the VSrc classes
1388 static bool isVSrc(unsigned RegClass) {
1389 return AMDGPU::VSrc_32RegClassID == RegClass ||
1390 AMDGPU::VSrc_64RegClassID == RegClass;
1393 /// \brief Test if RegClass is one of the SSrc classes
1394 static bool isSSrc(unsigned RegClass) {
1395 return AMDGPU::SSrc_32RegClassID == RegClass ||
1396 AMDGPU::SSrc_64RegClassID == RegClass;
1399 /// \brief Analyze the possible immediate value Op
1401 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1402 /// and the immediate value if it's a literal immediate
1403 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1410 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1411 if (Node->getZExtValue() >> 32) {
1414 Imm.I = Node->getSExtValue();
1415 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1416 if (N->getValueType(0) != MVT::f32)
1418 Imm.F = Node->getValueAPF().convertToFloat();
1420 return -1; // It isn't an immediate
1422 if ((Imm.I >= -16 && Imm.I <= 64) ||
1423 Imm.F == 0.5f || Imm.F == -0.5f ||
1424 Imm.F == 1.0f || Imm.F == -1.0f ||
1425 Imm.F == 2.0f || Imm.F == -2.0f ||
1426 Imm.F == 4.0f || Imm.F == -4.0f)
1427 return 0; // It's an inline immediate
1429 return Imm.I; // It's a literal immediate
1432 /// \brief Try to fold an immediate directly into an instruction
1433 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1434 bool &ScalarSlotUsed) const {
1436 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1437 const SIInstrInfo *TII =
1438 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1439 if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1442 const SDValue &Op = Mov->getOperand(0);
1443 int32_t Value = analyzeImmediate(Op.getNode());
1445 // Not an immediate at all
1448 } else if (Value == 0) {
1449 // Inline immediates can always be fold
1453 } else if (Value == Immediate) {
1454 // Already fold literal immediate
1458 } else if (!ScalarSlotUsed && !Immediate) {
1459 // Fold this literal immediate
1460 ScalarSlotUsed = true;
1470 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1471 SelectionDAG &DAG, const SDValue &Op) const {
1472 const SIInstrInfo *TII =
1473 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1474 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1476 if (!Op->isMachineOpcode()) {
1477 switch(Op->getOpcode()) {
1478 case ISD::CopyFromReg: {
1479 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1480 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1481 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1482 return MRI.getRegClass(Reg);
1484 return TRI.getPhysRegClass(Reg);
1486 default: return nullptr;
1489 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1490 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1491 if (OpClassID != -1) {
1492 return TRI.getRegClass(OpClassID);
1494 switch(Op.getMachineOpcode()) {
1495 case AMDGPU::COPY_TO_REGCLASS:
1496 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1497 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1499 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1500 // class, then the register class for the value could be either a
1501 // VReg or and SReg. In order to get a more accurate
1502 if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1503 OpClassID == AMDGPU::VSrc_64RegClassID) {
1504 return getRegClassForNode(DAG, Op.getOperand(0));
1506 return TRI.getRegClass(OpClassID);
1507 case AMDGPU::EXTRACT_SUBREG: {
1508 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1509 const TargetRegisterClass *SuperClass =
1510 getRegClassForNode(DAG, Op.getOperand(0));
1511 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1513 case AMDGPU::REG_SEQUENCE:
1514 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1515 return TRI.getRegClass(
1516 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1518 return getRegClassFor(Op.getSimpleValueType());
1522 /// \brief Does "Op" fit into register class "RegClass" ?
1523 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1524 unsigned RegClass) const {
1525 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1526 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1530 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1533 /// \brief Make sure that we don't exeed the number of allowed scalars
1534 void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
1536 bool &ScalarSlotUsed) const {
1538 // First map the operands register class to a destination class
1539 if (RegClass == AMDGPU::VSrc_32RegClassID)
1540 RegClass = AMDGPU::VReg_32RegClassID;
1541 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1542 RegClass = AMDGPU::VReg_64RegClassID;
1546 // Nothing to do if they fit naturally
1547 if (fitsRegClass(DAG, Operand, RegClass))
1550 // If the scalar slot isn't used yet use it now
1551 if (!ScalarSlotUsed) {
1552 ScalarSlotUsed = true;
1556 // This is a conservative aproach. It is possible that we can't determine the
1557 // correct register class and copy too often, but better safe than sorry.
1560 // We can't use COPY_TO_REGCLASS with FrameIndex arguments.
1561 if (isa<FrameIndexSDNode>(Operand)) {
1562 unsigned Opcode = Operand.getValueType() == MVT::i32 ?
1563 AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
1564 Node = DAG.getMachineNode(Opcode, SDLoc(), Operand.getValueType(),
1567 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1568 Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
1569 Operand.getValueType(), Operand, RC);
1571 Operand = SDValue(Node, 0);
1574 /// \returns true if \p Node's operands are different from the SDValue list
1576 static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1577 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1578 if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1585 /// \brief Try to fold the Nodes operands into the Node
1586 SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
1587 SelectionDAG &DAG) const {
1589 // Original encoding (either e32 or e64)
1590 int Opcode = Node->getMachineOpcode();
1591 const SIInstrInfo *TII =
1592 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1593 const MCInstrDesc *Desc = &TII->get(Opcode);
1595 unsigned NumDefs = Desc->getNumDefs();
1596 unsigned NumOps = Desc->getNumOperands();
1598 // Commuted opcode if available
1599 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1600 const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1602 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1603 assert(!DescRev || DescRev->getNumOperands() == NumOps);
1605 // e64 version if available, -1 otherwise
1606 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1607 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
1608 int InputModifiers[3] = {0};
1610 assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
1612 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1613 bool HaveVSrc = false, HaveSSrc = false;
1615 // First figure out what we already have in this instruction.
1616 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1617 i != e && Op < NumOps; ++i, ++Op) {
1619 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1620 if (isVSrc(RegClass))
1622 else if (isSSrc(RegClass))
1627 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1628 if (Imm != -1 && Imm != 0) {
1629 // Literal immediate
1634 // If we neither have VSrc nor SSrc, it makes no sense to continue.
1635 if (!HaveVSrc && !HaveSSrc)
1638 // No scalar allowed when we have both VSrc and SSrc
1639 bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1641 // Second go over the operands and try to fold them
1642 std::vector<SDValue> Ops;
1643 bool Promote2e64 = false;
1644 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1645 i != e && Op < NumOps; ++i, ++Op) {
1647 const SDValue &Operand = Node->getOperand(i);
1648 Ops.push_back(Operand);
1650 // Already folded immediate?
1651 if (isa<ConstantSDNode>(Operand.getNode()) ||
1652 isa<ConstantFPSDNode>(Operand.getNode()))
1655 // Is this a VSrc or SSrc operand?
1656 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1657 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1658 // Try to fold the immediates
1659 if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
1660 // Folding didn't work, make sure we don't hit the SReg limit.
1661 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1665 // If it's not a VSrc or SSrc operand check if we have a GlobalAddress.
1666 // These will be lowered to immediates, so we will need to insert a MOV.
1667 if (isa<GlobalAddressSDNode>(Ops[i])) {
1668 SDNode *Node = DAG.getMachineNode(AMDGPU::V_MOV_B32_e32, SDLoc(),
1669 Operand.getValueType(), Operand);
1670 Ops[i] = SDValue(Node, 0);
1674 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1676 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1677 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1679 // Test if it makes sense to swap operands
1680 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1681 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1682 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1684 // Swap commutable operands
1685 std::swap(Ops[0], Ops[1]);
1697 // Test if it makes sense to switch to e64 encoding
1698 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1699 if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
1702 int32_t TmpImm = -1;
1703 if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
1704 (!fitsRegClass(DAG, Ops[i], RegClass) &&
1705 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1707 // Switch to e64 encoding
1715 if (!DescE64 && !Promote2e64)
1717 if (!Operand.isMachineOpcode())
1719 if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) {
1721 Ops.push_back(Operand.getOperand(0));
1722 InputModifiers[i] = 1;
1729 else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) {
1731 Ops.push_back(Operand.getOperand(0));
1732 InputModifiers[i] = 2;
1742 std::vector<SDValue> OldOps(Ops);
1744 for (unsigned i = 0; i < OldOps.size(); ++i) {
1746 Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
1747 Ops.push_back(OldOps[i]);
1749 // Add the modifier flags while promoting
1750 for (unsigned i = 0; i < 2; ++i)
1751 Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
1754 // Add optional chain and glue
1755 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1756 Ops.push_back(Node->getOperand(i));
1758 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1759 // this case a brand new node is always be created, even if the operands
1760 // are the same as before. So, manually check if anything has been changed.
1761 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1765 // Create a complete new instruction
1766 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1769 /// \brief Helper function for adjustWritemask
1770 static unsigned SubIdx2Lane(unsigned Idx) {
1773 case AMDGPU::sub0: return 0;
1774 case AMDGPU::sub1: return 1;
1775 case AMDGPU::sub2: return 2;
1776 case AMDGPU::sub3: return 3;
1780 /// \brief Adjust the writemask of MIMG instructions
1781 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1782 SelectionDAG &DAG) const {
1783 SDNode *Users[4] = { };
1785 unsigned OldDmask = Node->getConstantOperandVal(0);
1786 unsigned NewDmask = 0;
1788 // Try to figure out the used register components
1789 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1792 // Abort if we can't understand the usage
1793 if (!I->isMachineOpcode() ||
1794 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1797 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1798 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1799 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1801 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1803 // Set which texture component corresponds to the lane.
1805 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1807 Comp = countTrailingZeros(Dmask);
1808 Dmask &= ~(1 << Comp);
1811 // Abort if we have more than one user per component
1816 NewDmask |= 1 << Comp;
1819 // Abort if there's no change
1820 if (NewDmask == OldDmask)
1823 // Adjust the writemask in the node
1824 std::vector<SDValue> Ops;
1825 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1826 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1827 Ops.push_back(Node->getOperand(i));
1828 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1830 // If we only got one lane, replace it with a copy
1831 // (if NewDmask has only one bit set...)
1832 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1833 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1834 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1835 SDLoc(), Users[Lane]->getValueType(0),
1836 SDValue(Node, 0), RC);
1837 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1841 // Update the users of the node with the new indices
1842 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1844 SDNode *User = Users[i];
1848 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1849 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1853 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1854 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1855 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1860 /// \brief Fold the instructions after selecting them.
1861 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1862 SelectionDAG &DAG) const {
1863 const SIInstrInfo *TII =
1864 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1865 Node = AdjustRegClass(Node, DAG);
1867 if (TII->isMIMG(Node->getMachineOpcode()))
1868 adjustWritemask(Node, DAG);
1870 return foldOperands(Node, DAG);
1873 /// \brief Assign the register class depending on the number of
1874 /// bits set in the writemask
1875 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1876 SDNode *Node) const {
1877 const SIInstrInfo *TII =
1878 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1879 if (!TII->isMIMG(MI->getOpcode()))
1882 unsigned VReg = MI->getOperand(0).getReg();
1883 unsigned Writemask = MI->getOperand(1).getImm();
1884 unsigned BitsSet = 0;
1885 for (unsigned i = 0; i < 4; ++i)
1886 BitsSet += Writemask & (1 << i) ? 1 : 0;
1888 const TargetRegisterClass *RC;
1891 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1892 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1893 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1896 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1897 MI->setDesc(TII->get(NewOpcode));
1898 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1899 MRI.setRegClass(VReg, RC);
1902 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1903 SelectionDAG &DAG) const {
1906 unsigned NewOpcode = N->getMachineOpcode();
1908 switch (N->getMachineOpcode()) {
1910 case AMDGPU::S_LOAD_DWORD_IMM:
1911 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1913 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1914 if (NewOpcode == N->getMachineOpcode()) {
1915 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1918 case AMDGPU::S_LOAD_DWORDX4_IMM:
1919 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1920 if (NewOpcode == N->getMachineOpcode()) {
1921 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1923 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1926 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
1928 SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
1929 DAG.getConstant(0, MVT::i64)), 0),
1931 DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
1933 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
1938 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1939 const TargetRegisterClass *RC,
1940 unsigned Reg, EVT VT) const {
1941 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1943 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1944 cast<RegisterSDNode>(VReg)->getReg(), VT);