1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUIntrinsicInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAG.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/ADT/SmallString.h"
37 SITargetLowering::SITargetLowering(TargetMachine &TM) :
38 AMDGPUTargetLowering(TM) {
39 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
40 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
42 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
43 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
45 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
46 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
48 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
49 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
50 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
52 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
53 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
55 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
56 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
58 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
59 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
61 computeRegisterProperties();
64 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
65 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
66 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
67 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
68 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
69 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
71 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
72 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
73 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
74 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
75 setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
76 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
78 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
79 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
80 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
81 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
83 setOperationAction(ISD::ADD, MVT::i32, Legal);
84 setOperationAction(ISD::ADDC, MVT::i32, Legal);
85 setOperationAction(ISD::ADDE, MVT::i32, Legal);
86 setOperationAction(ISD::SUBC, MVT::i32, Legal);
87 setOperationAction(ISD::SUBE, MVT::i32, Legal);
89 setOperationAction(ISD::FSIN, MVT::f32, Custom);
90 setOperationAction(ISD::FCOS, MVT::f32, Custom);
92 // We need to custom lower vector stores from local memory
93 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
94 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
95 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
97 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
98 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
100 setOperationAction(ISD::STORE, MVT::i1, Custom);
101 setOperationAction(ISD::STORE, MVT::i32, Custom);
102 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
103 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
105 setOperationAction(ISD::SELECT, MVT::f32, Promote);
106 AddPromotedToType(ISD::SELECT, MVT::f32, MVT::i32);
107 setOperationAction(ISD::SELECT, MVT::i64, Custom);
108 setOperationAction(ISD::SELECT, MVT::f64, Promote);
109 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
111 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
113 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
114 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
116 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
117 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
128 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
133 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
135 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
136 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
137 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
138 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
140 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
141 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
143 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
145 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
146 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
147 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
148 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
152 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
153 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
155 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
156 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
157 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
158 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
159 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
161 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
162 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
163 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
164 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
165 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
166 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
168 setOperationAction(ISD::LOAD, MVT::i1, Custom);
170 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
171 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
173 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
174 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
175 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
177 // These should use UDIVREM, so set them to expand
178 setOperationAction(ISD::UDIV, MVT::i64, Expand);
179 setOperationAction(ISD::UREM, MVT::i64, Expand);
181 // We only support LOAD/STORE and vector manipulation ops for vectors
182 // with > 4 elements.
184 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
187 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
188 setOperationAction(ISD::SELECT, MVT::i1, Promote);
190 for (MVT VT : VecTypes) {
191 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
195 case ISD::BUILD_VECTOR:
197 case ISD::EXTRACT_VECTOR_ELT:
198 case ISD::INSERT_VECTOR_ELT:
199 case ISD::CONCAT_VECTORS:
200 case ISD::INSERT_SUBVECTOR:
201 case ISD::EXTRACT_SUBVECTOR:
204 setOperationAction(Op, VT, Expand);
210 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
211 MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
212 setOperationAction(ISD::FTRUNC, VT, Expand);
213 setOperationAction(ISD::FCEIL, VT, Expand);
214 setOperationAction(ISD::FFLOOR, VT, Expand);
217 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
218 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
219 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
220 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
221 setOperationAction(ISD::FRINT, MVT::f64, Legal);
224 // FIXME: These should be removed and handled the same was as f32 fneg. Source
225 // modifiers also work for the double instructions.
226 setOperationAction(ISD::FNEG, MVT::f64, Expand);
227 setOperationAction(ISD::FABS, MVT::f64, Expand);
229 setOperationAction(ISD::FDIV, MVT::f32, Custom);
231 setTargetDAGCombine(ISD::SELECT_CC);
232 setTargetDAGCombine(ISD::SETCC);
234 setTargetDAGCombine(ISD::UINT_TO_FP);
236 setSchedulingPreference(Sched::RegPressure);
239 //===----------------------------------------------------------------------===//
240 // TargetLowering queries
241 //===----------------------------------------------------------------------===//
243 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
246 bool *IsFast) const {
250 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
251 // which isn't a simple VT.
252 if (!VT.isSimple() || VT == MVT::Other)
255 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
256 // see what for specifically. The wording everywhere else seems to be the
259 // XXX - The only mention I see of this in the ISA manual is for LDS direct
260 // reads the "byte address and must be dword aligned". Is it also true for the
261 // normal loads and stores?
262 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
263 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
264 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
265 // with adjacent offsets.
266 return Align % 4 == 0;
269 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
270 // byte-address are ignored, thus forcing Dword alignment.
271 // This applies to private, global, and constant memory.
274 return VT.bitsGT(MVT::i32);
277 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
278 unsigned SrcAlign, bool IsMemset,
281 MachineFunction &MF) const {
282 // FIXME: Should account for address space here.
284 // The default fallback uses the private pointer size as a guess for a type to
285 // use. Make sure we switch these to 64-bit accesses.
287 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
290 if (Size >= 8 && DstAlign >= 4)
297 TargetLoweringBase::LegalizeTypeAction
298 SITargetLowering::getPreferredVectorAction(EVT VT) const {
299 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
300 return TypeSplitVector;
302 return TargetLoweringBase::getPreferredVectorAction(VT);
305 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
307 const SIInstrInfo *TII =
308 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
309 return TII->isInlineConstant(Imm);
312 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
313 SDLoc SL, SDValue Chain,
314 unsigned Offset, bool Signed) const {
315 const DataLayout *DL = getDataLayout();
317 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
319 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
320 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
321 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
322 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
323 SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
324 DAG.getConstant(Offset, MVT::i64));
325 SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
326 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
328 return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD,
329 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
331 true, // isNonTemporal
333 DL->getABITypeAlignment(Ty)); // Alignment
336 SDValue SITargetLowering::LowerFormalArguments(
338 CallingConv::ID CallConv,
340 const SmallVectorImpl<ISD::InputArg> &Ins,
341 SDLoc DL, SelectionDAG &DAG,
342 SmallVectorImpl<SDValue> &InVals) const {
344 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
346 MachineFunction &MF = DAG.getMachineFunction();
347 FunctionType *FType = MF.getFunction()->getFunctionType();
348 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
350 assert(CallConv == CallingConv::C);
352 SmallVector<ISD::InputArg, 16> Splits;
353 uint32_t Skipped = 0;
355 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
356 const ISD::InputArg &Arg = Ins[i];
358 // First check if it's a PS input addr
359 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
360 !Arg.Flags.isByVal()) {
362 assert((PSInputNum <= 15) && "Too many PS inputs!");
365 // We can savely skip PS inputs
371 Info->PSInputAddr |= 1 << PSInputNum++;
374 // Second split vertices into their elements
375 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
376 ISD::InputArg NewArg = Arg;
377 NewArg.Flags.setSplit();
378 NewArg.VT = Arg.VT.getVectorElementType();
380 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
381 // three or five element vertex only needs three or five registers,
382 // NOT four or eigth.
383 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
384 unsigned NumElements = ParamType->getVectorNumElements();
386 for (unsigned j = 0; j != NumElements; ++j) {
387 Splits.push_back(NewArg);
388 NewArg.PartOffset += NewArg.VT.getStoreSize();
391 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
392 Splits.push_back(Arg);
396 SmallVector<CCValAssign, 16> ArgLocs;
397 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
398 getTargetMachine(), ArgLocs, *DAG.getContext());
400 // At least one interpolation mode must be enabled or else the GPU will hang.
401 if (Info->getShaderType() == ShaderType::PIXEL &&
402 (Info->PSInputAddr & 0x7F) == 0) {
403 Info->PSInputAddr |= 1;
404 CCInfo.AllocateReg(AMDGPU::VGPR0);
405 CCInfo.AllocateReg(AMDGPU::VGPR1);
408 // The pointer to the list of arguments is stored in SGPR0, SGPR1
409 // The pointer to the scratch buffer is stored in SGPR2, SGPR3
410 if (Info->getShaderType() == ShaderType::COMPUTE) {
411 Info->NumUserSGPRs = 4;
412 CCInfo.AllocateReg(AMDGPU::SGPR0);
413 CCInfo.AllocateReg(AMDGPU::SGPR1);
414 CCInfo.AllocateReg(AMDGPU::SGPR2);
415 CCInfo.AllocateReg(AMDGPU::SGPR3);
416 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
417 MF.addLiveIn(AMDGPU::SGPR2_SGPR3, &AMDGPU::SReg_64RegClass);
420 if (Info->getShaderType() == ShaderType::COMPUTE) {
421 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
425 AnalyzeFormalArguments(CCInfo, Splits);
427 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
429 const ISD::InputArg &Arg = Ins[i];
430 if (Skipped & (1 << i)) {
431 InVals.push_back(DAG.getUNDEF(Arg.VT));
435 CCValAssign &VA = ArgLocs[ArgIdx++];
436 EVT VT = VA.getLocVT();
440 EVT MemVT = Splits[i].VT;
441 // The first 36 bytes of the input buffer contains information about
442 // thread group and global sizes.
443 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
444 36 + VA.getLocMemOffset(),
445 Ins[i].Flags.isSExt());
446 InVals.push_back(Arg);
449 assert(VA.isRegLoc() && "Parameter must be in a register!");
451 unsigned Reg = VA.getLocReg();
453 if (VT == MVT::i64) {
454 // For now assume it is a pointer
455 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
456 &AMDGPU::SReg_64RegClass);
457 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
458 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
462 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
464 Reg = MF.addLiveIn(Reg, RC);
465 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
467 if (Arg.VT.isVector()) {
469 // Build a vector from the registers
470 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
471 unsigned NumElements = ParamType->getVectorNumElements();
473 SmallVector<SDValue, 4> Regs;
475 for (unsigned j = 1; j != NumElements; ++j) {
476 Reg = ArgLocs[ArgIdx++].getLocReg();
477 Reg = MF.addLiveIn(Reg, RC);
478 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
481 // Fill up the missing vector elements
482 NumElements = Arg.VT.getVectorNumElements() - NumElements;
483 for (unsigned j = 0; j != NumElements; ++j)
484 Regs.push_back(DAG.getUNDEF(VT));
486 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
490 InVals.push_back(Val);
495 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
496 MachineInstr * MI, MachineBasicBlock * BB) const {
498 MachineBasicBlock::iterator I = *MI;
499 const SIInstrInfo *TII =
500 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
501 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
503 switch (MI->getOpcode()) {
505 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
506 case AMDGPU::BRANCH: return BB;
507 case AMDGPU::SI_ADDR64_RSRC: {
508 unsigned SuperReg = MI->getOperand(0).getReg();
509 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
510 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
511 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
512 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
513 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
514 .addOperand(MI->getOperand(1));
515 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
517 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
518 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
519 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
521 .addImm(AMDGPU::sub0)
523 .addImm(AMDGPU::sub1);
524 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
526 .addImm(AMDGPU::sub0_sub1)
528 .addImm(AMDGPU::sub2_sub3);
529 MI->eraseFromParent();
532 case AMDGPU::SI_BUFFER_RSRC: {
533 unsigned SuperReg = MI->getOperand(0).getReg();
535 for (unsigned i = 0, e = 4; i < e; ++i) {
536 MachineOperand &Arg = MI->getOperand(i + 1);
539 Args[i] = Arg.getReg();
544 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
545 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), Reg)
546 .addImm(Arg.getImm());
549 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE),
552 .addImm(AMDGPU::sub0)
554 .addImm(AMDGPU::sub1)
556 .addImm(AMDGPU::sub2)
558 .addImm(AMDGPU::sub3);
559 MI->eraseFromParent();
562 case AMDGPU::V_SUB_F64: {
563 unsigned DestReg = MI->getOperand(0).getReg();
564 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
565 .addImm(0) // SRC0 modifiers
566 .addReg(MI->getOperand(1).getReg())
567 .addImm(1) // SRC1 modifiers
568 .addReg(MI->getOperand(2).getReg())
571 MI->eraseFromParent();
574 case AMDGPU::SI_RegisterStorePseudo: {
575 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
576 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
577 MachineInstrBuilder MIB =
578 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
580 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
581 MIB.addOperand(MI->getOperand(i));
583 MI->eraseFromParent();
586 case AMDGPU::FABS_SI: {
587 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
588 const SIInstrInfo *TII =
589 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
591 DebugLoc DL = MI->getDebugLoc();
592 unsigned DestReg = MI->getOperand(0).getReg();
593 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
595 BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
597 BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), DestReg)
598 .addReg(MI->getOperand(1).getReg())
600 MI->eraseFromParent();
603 case AMDGPU::FNEG_SI: {
604 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
605 const SIInstrInfo *TII =
606 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
608 DebugLoc DL = MI->getDebugLoc();
609 unsigned DestReg = MI->getOperand(0).getReg();
610 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
612 BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
614 BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg)
615 .addReg(MI->getOperand(1).getReg())
617 MI->eraseFromParent();
620 case AMDGPU::FCLAMP_SI: {
621 const SIInstrInfo *TII =
622 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
624 DebugLoc DL = MI->getDebugLoc();
625 unsigned DestReg = MI->getOperand(0).getReg();
626 BuildMI(*BB, I, DL, TII->get(AMDGPU::V_ADD_F32_e64), DestReg)
627 .addImm(0) // SRC0 modifiers
628 .addOperand(MI->getOperand(1))
629 .addImm(0) // SRC1 modifiers
633 MI->eraseFromParent();
639 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
640 if (!VT.isVector()) {
643 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
646 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
650 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
651 VT = VT.getScalarType();
656 switch (VT.getSimpleVT().SimpleTy) {
658 return false; /* There is V_MAD_F32 for f32 */
668 //===----------------------------------------------------------------------===//
669 // Custom DAG Lowering Operations
670 //===----------------------------------------------------------------------===//
672 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
673 switch (Op.getOpcode()) {
674 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
675 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
676 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
678 SDValue Result = LowerLOAD(Op, DAG);
679 assert((!Result.getNode() ||
680 Result.getNode()->getNumValues() == 2) &&
681 "Load should return a value and a chain");
687 return LowerTrig(Op, DAG);
688 case ISD::SELECT: return LowerSELECT(Op, DAG);
689 case ISD::FDIV: return LowerFDIV(Op, DAG);
690 case ISD::STORE: return LowerSTORE(Op, DAG);
691 case ISD::GlobalAddress: {
692 MachineFunction &MF = DAG.getMachineFunction();
693 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
694 return LowerGlobalAddress(MFI, Op, DAG);
696 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
697 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
702 /// \brief Helper function for LowerBRCOND
703 static SDNode *findUser(SDValue Value, unsigned Opcode) {
705 SDNode *Parent = Value.getNode();
706 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
709 if (I.getUse().get() != Value)
712 if (I->getOpcode() == Opcode)
718 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
720 MachineFunction &MF = DAG.getMachineFunction();
721 const SIInstrInfo *TII =
722 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
723 const SIRegisterInfo &TRI = TII->getRegisterInfo();
724 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
725 unsigned FrameIndex = FINode->getIndex();
727 CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
728 TRI.getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET), MVT::i32);
730 return DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
733 /// This transforms the control flow intrinsics to get the branch destination as
734 /// last parameter, also switches branch target with BR if the need arise
735 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
736 SelectionDAG &DAG) const {
740 SDNode *Intr = BRCOND.getOperand(1).getNode();
741 SDValue Target = BRCOND.getOperand(2);
742 SDNode *BR = nullptr;
744 if (Intr->getOpcode() == ISD::SETCC) {
745 // As long as we negate the condition everything is fine
746 SDNode *SetCC = Intr;
747 assert(SetCC->getConstantOperandVal(1) == 1);
748 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
750 Intr = SetCC->getOperand(0).getNode();
753 // Get the target from BR if we don't negate the condition
754 BR = findUser(BRCOND, ISD::BR);
755 Target = BR->getOperand(1);
758 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
760 // Build the result and
761 SmallVector<EVT, 4> Res;
762 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
763 Res.push_back(Intr->getValueType(i));
765 // operands of the new intrinsic call
766 SmallVector<SDValue, 4> Ops;
767 Ops.push_back(BRCOND.getOperand(0));
768 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
769 Ops.push_back(Intr->getOperand(i));
770 Ops.push_back(Target);
772 // build the new intrinsic call
773 SDNode *Result = DAG.getNode(
774 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
775 DAG.getVTList(Res), Ops).getNode();
778 // Give the branch instruction our target
783 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
784 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
785 BR = NewBR.getNode();
788 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
790 // Copy the intrinsic results to registers
791 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
792 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
796 Chain = DAG.getCopyToReg(
798 CopyToReg->getOperand(1),
799 SDValue(Result, i - 1),
802 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
805 // Remove the old intrinsic from the chain
806 DAG.ReplaceAllUsesOfValueWith(
807 SDValue(Intr, Intr->getNumValues() - 1),
808 Intr->getOperand(0));
813 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
815 SelectionDAG &DAG) const {
816 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
818 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
819 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
822 const GlobalValue *GV = GSD->getGlobal();
823 MVT PtrVT = getPointerTy(GSD->getAddressSpace());
825 SDValue Ptr = DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT);
826 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
828 SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
829 DAG.getConstant(0, MVT::i32));
830 SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
831 DAG.getConstant(1, MVT::i32));
833 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
835 SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue),
836 PtrHi, DAG.getConstant(0, MVT::i32),
837 SDValue(Lo.getNode(), 1));
838 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
841 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
842 SelectionDAG &DAG) const {
843 MachineFunction &MF = DAG.getMachineFunction();
844 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
846 EVT VT = Op.getValueType();
848 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
850 switch (IntrinsicID) {
851 case Intrinsic::r600_read_ngroups_x:
852 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
853 case Intrinsic::r600_read_ngroups_y:
854 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
855 case Intrinsic::r600_read_ngroups_z:
856 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
857 case Intrinsic::r600_read_global_size_x:
858 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
859 case Intrinsic::r600_read_global_size_y:
860 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
861 case Intrinsic::r600_read_global_size_z:
862 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
863 case Intrinsic::r600_read_local_size_x:
864 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
865 case Intrinsic::r600_read_local_size_y:
866 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
867 case Intrinsic::r600_read_local_size_z:
868 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
869 case Intrinsic::r600_read_tgid_x:
870 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
871 AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0), VT);
872 case Intrinsic::r600_read_tgid_y:
873 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
874 AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1), VT);
875 case Intrinsic::r600_read_tgid_z:
876 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
877 AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2), VT);
878 case Intrinsic::r600_read_tidig_x:
879 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
881 case Intrinsic::r600_read_tidig_y:
882 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
884 case Intrinsic::r600_read_tidig_z:
885 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
887 case AMDGPUIntrinsic::SI_load_const: {
893 MachineMemOperand *MMO = MF.getMachineMemOperand(
894 MachinePointerInfo(),
895 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
896 VT.getStoreSize(), 4);
897 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
898 Op->getVTList(), Ops, VT, MMO);
900 case AMDGPUIntrinsic::SI_sample:
901 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
902 case AMDGPUIntrinsic::SI_sampleb:
903 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
904 case AMDGPUIntrinsic::SI_sampled:
905 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
906 case AMDGPUIntrinsic::SI_samplel:
907 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
908 case AMDGPUIntrinsic::SI_vs_load_input:
909 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
914 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
918 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
919 SelectionDAG &DAG) const {
920 MachineFunction &MF = DAG.getMachineFunction();
921 SDValue Chain = Op.getOperand(0);
922 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
924 switch (IntrinsicID) {
925 case AMDGPUIntrinsic::SI_tbuffer_store: {
944 EVT VT = Op.getOperand(3).getValueType();
946 MachineMemOperand *MMO = MF.getMachineMemOperand(
947 MachinePointerInfo(),
948 MachineMemOperand::MOStore,
949 VT.getStoreSize(), 4);
950 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
951 Op->getVTList(), Ops, VT, MMO);
958 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
960 LoadSDNode *Load = cast<LoadSDNode>(Op);
962 if (Op.getValueType().isVector()) {
963 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
964 "Custom lowering for non-i32 vectors hasn't been implemented.");
965 unsigned NumElements = Op.getValueType().getVectorNumElements();
966 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
967 switch (Load->getAddressSpace()) {
969 case AMDGPUAS::GLOBAL_ADDRESS:
970 case AMDGPUAS::PRIVATE_ADDRESS:
971 // v4 loads are supported for private and global memory.
972 if (NumElements <= 4)
975 case AMDGPUAS::LOCAL_ADDRESS:
976 return ScalarizeVectorLoad(Op, DAG);
980 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
983 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
985 SelectionDAG &DAG) const {
986 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
992 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
993 if (Op.getValueType() != MVT::i64)
997 SDValue Cond = Op.getOperand(0);
999 SDValue Zero = DAG.getConstant(0, MVT::i32);
1000 SDValue One = DAG.getConstant(1, MVT::i32);
1002 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1003 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1005 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1006 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1008 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1010 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1011 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1013 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1015 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1016 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1019 // Catch division cases where we can use shortcuts with rcp and rsq
1021 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1023 SDValue LHS = Op.getOperand(0);
1024 SDValue RHS = Op.getOperand(1);
1025 EVT VT = Op.getValueType();
1026 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1028 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1029 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1030 CLHS->isExactlyValue(1.0)) {
1031 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1032 // the CI documentation has a worst case error of 1 ulp.
1033 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1034 // use it as long as we aren't trying to use denormals.
1036 // 1.0 / sqrt(x) -> rsq(x)
1038 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1039 // error seems really high at 2^29 ULP.
1040 if (RHS.getOpcode() == ISD::FSQRT)
1041 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1043 // 1.0 / x -> rcp(x)
1044 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1049 // Turn into multiply by the reciprocal.
1050 // x / y -> x * (1.0 / y)
1051 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1052 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip);
1058 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1059 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1060 if (FastLowered.getNode())
1063 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1064 // selection error for now rather than do something incorrect.
1065 if (Subtarget->hasFP32Denormals())
1069 SDValue LHS = Op.getOperand(0);
1070 SDValue RHS = Op.getOperand(1);
1072 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1074 const APFloat K0Val(BitsToFloat(0x6f800000));
1075 const SDValue K0 = DAG.getConstantFP(K0Val, MVT::f32);
1077 const APFloat K1Val(BitsToFloat(0x2f800000));
1078 const SDValue K1 = DAG.getConstantFP(K1Val, MVT::f32);
1080 const SDValue One = DAG.getTargetConstantFP(1.0, MVT::f32);
1082 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
1084 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1086 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1088 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1090 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1092 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1094 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1097 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1101 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1102 EVT VT = Op.getValueType();
1105 return LowerFDIV32(Op, DAG);
1108 return LowerFDIV64(Op, DAG);
1110 llvm_unreachable("Unexpected type for fdiv");
1113 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1115 StoreSDNode *Store = cast<StoreSDNode>(Op);
1116 EVT VT = Store->getMemoryVT();
1118 // These stores are legal.
1119 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
1120 VT.isVector() && VT.getVectorNumElements() == 2 &&
1121 VT.getVectorElementType() == MVT::i32)
1124 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1125 if (VT.isVector() && VT.getVectorNumElements() > 4)
1126 return ScalarizeVectorStore(Op, DAG);
1130 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1134 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1135 return ScalarizeVectorStore(Op, DAG);
1138 return DAG.getTruncStore(Store->getChain(), DL,
1139 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1140 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1145 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1146 EVT VT = Op.getValueType();
1147 SDValue Arg = Op.getOperand(0);
1148 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
1149 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
1150 DAG.getConstantFP(0.5 / M_PI, VT)));
1152 switch (Op.getOpcode()) {
1154 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1156 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1158 llvm_unreachable("Wrong trig opcode");
1162 //===----------------------------------------------------------------------===//
1163 // Custom DAG optimizations
1164 //===----------------------------------------------------------------------===//
1166 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1167 DAGCombinerInfo &DCI) {
1168 EVT VT = N->getValueType(0);
1169 EVT ScalarVT = VT.getScalarType();
1170 if (ScalarVT != MVT::f32)
1173 SelectionDAG &DAG = DCI.DAG;
1176 SDValue Src = N->getOperand(0);
1177 EVT SrcVT = Src.getValueType();
1179 // TODO: We could try to match extracting the higher bytes, which would be
1180 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1181 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1182 // about in practice.
1183 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1184 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1185 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1186 DCI.AddToWorklist(Cvt.getNode());
1191 // We are primarily trying to catch operations on illegal vector types
1192 // before they are expanded.
1193 // For scalars, we can use the more flexible method of checking masked bits
1194 // after legalization.
1195 if (!DCI.isBeforeLegalize() ||
1196 !SrcVT.isVector() ||
1197 SrcVT.getVectorElementType() != MVT::i8) {
1201 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1203 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1205 unsigned NElts = SrcVT.getVectorNumElements();
1206 if (!SrcVT.isSimple() && NElts != 3)
1209 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1210 // prevent a mess from expanding to v4i32 and repacking.
1211 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1212 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1213 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1214 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1216 LoadSDNode *Load = cast<LoadSDNode>(Src);
1217 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1221 Load->getMemOperand());
1223 // Make sure successors of the original load stay after it by updating
1224 // them to use the new Chain.
1225 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1227 SmallVector<SDValue, 4> Elts;
1228 if (RegVT.isVector())
1229 DAG.ExtractVectorElements(NewLoad, Elts);
1231 Elts.push_back(NewLoad);
1233 SmallVector<SDValue, 4> Ops;
1235 unsigned EltIdx = 0;
1236 for (SDValue Elt : Elts) {
1237 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1238 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1239 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1240 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1241 DCI.AddToWorklist(Cvt.getNode());
1248 assert(Ops.size() == NElts);
1250 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1256 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1257 DAGCombinerInfo &DCI) const {
1258 SelectionDAG &DAG = DCI.DAG;
1260 EVT VT = N->getValueType(0);
1262 switch (N->getOpcode()) {
1263 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1265 SDValue Arg0 = N->getOperand(0);
1266 SDValue Arg1 = N->getOperand(1);
1267 SDValue CC = N->getOperand(2);
1268 ConstantSDNode * C = nullptr;
1269 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1271 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1273 && Arg0.getOpcode() == ISD::SIGN_EXTEND
1274 && Arg0.getOperand(0).getValueType() == MVT::i1
1275 && (C = dyn_cast<ConstantSDNode>(Arg1))
1277 && CCOp == ISD::SETNE) {
1278 return SimplifySetCC(VT, Arg0.getOperand(0),
1279 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1284 case AMDGPUISD::CVT_F32_UBYTE0:
1285 case AMDGPUISD::CVT_F32_UBYTE1:
1286 case AMDGPUISD::CVT_F32_UBYTE2:
1287 case AMDGPUISD::CVT_F32_UBYTE3: {
1288 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1290 SDValue Src = N->getOperand(0);
1291 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1293 APInt KnownZero, KnownOne;
1294 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1295 !DCI.isBeforeLegalizeOps());
1296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1297 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1298 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1299 DCI.CommitTargetLoweringOpt(TLO);
1305 case ISD::UINT_TO_FP: {
1306 return performUCharToFloatCombine(N, DCI);
1310 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1313 /// \brief Test if RegClass is one of the VSrc classes
1314 static bool isVSrc(unsigned RegClass) {
1315 return AMDGPU::VSrc_32RegClassID == RegClass ||
1316 AMDGPU::VSrc_64RegClassID == RegClass;
1319 /// \brief Test if RegClass is one of the SSrc classes
1320 static bool isSSrc(unsigned RegClass) {
1321 return AMDGPU::SSrc_32RegClassID == RegClass ||
1322 AMDGPU::SSrc_64RegClassID == RegClass;
1325 /// \brief Analyze the possible immediate value Op
1327 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1328 /// and the immediate value if it's a literal immediate
1329 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1336 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1337 if (Node->getZExtValue() >> 32) {
1340 Imm.I = Node->getSExtValue();
1341 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1342 if (N->getValueType(0) != MVT::f32)
1344 Imm.F = Node->getValueAPF().convertToFloat();
1346 return -1; // It isn't an immediate
1348 if ((Imm.I >= -16 && Imm.I <= 64) ||
1349 Imm.F == 0.5f || Imm.F == -0.5f ||
1350 Imm.F == 1.0f || Imm.F == -1.0f ||
1351 Imm.F == 2.0f || Imm.F == -2.0f ||
1352 Imm.F == 4.0f || Imm.F == -4.0f)
1353 return 0; // It's an inline immediate
1355 return Imm.I; // It's a literal immediate
1358 /// \brief Try to fold an immediate directly into an instruction
1359 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1360 bool &ScalarSlotUsed) const {
1362 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1363 const SIInstrInfo *TII =
1364 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1365 if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1368 const SDValue &Op = Mov->getOperand(0);
1369 int32_t Value = analyzeImmediate(Op.getNode());
1371 // Not an immediate at all
1374 } else if (Value == 0) {
1375 // Inline immediates can always be fold
1379 } else if (Value == Immediate) {
1380 // Already fold literal immediate
1384 } else if (!ScalarSlotUsed && !Immediate) {
1385 // Fold this literal immediate
1386 ScalarSlotUsed = true;
1396 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1397 SelectionDAG &DAG, const SDValue &Op) const {
1398 const SIInstrInfo *TII =
1399 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1400 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1402 if (!Op->isMachineOpcode()) {
1403 switch(Op->getOpcode()) {
1404 case ISD::CopyFromReg: {
1405 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1406 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1407 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1408 return MRI.getRegClass(Reg);
1410 return TRI.getPhysRegClass(Reg);
1412 default: return nullptr;
1415 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1416 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1417 if (OpClassID != -1) {
1418 return TRI.getRegClass(OpClassID);
1420 switch(Op.getMachineOpcode()) {
1421 case AMDGPU::COPY_TO_REGCLASS:
1422 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1423 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1425 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1426 // class, then the register class for the value could be either a
1427 // VReg or and SReg. In order to get a more accurate
1428 if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1429 OpClassID == AMDGPU::VSrc_64RegClassID) {
1430 return getRegClassForNode(DAG, Op.getOperand(0));
1432 return TRI.getRegClass(OpClassID);
1433 case AMDGPU::EXTRACT_SUBREG: {
1434 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1435 const TargetRegisterClass *SuperClass =
1436 getRegClassForNode(DAG, Op.getOperand(0));
1437 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1439 case AMDGPU::REG_SEQUENCE:
1440 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1441 return TRI.getRegClass(
1442 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1444 return getRegClassFor(Op.getSimpleValueType());
1448 /// \brief Does "Op" fit into register class "RegClass" ?
1449 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1450 unsigned RegClass) const {
1451 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1452 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1456 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1459 /// \brief Make sure that we don't exeed the number of allowed scalars
1460 void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
1462 bool &ScalarSlotUsed) const {
1464 // First map the operands register class to a destination class
1465 if (RegClass == AMDGPU::VSrc_32RegClassID)
1466 RegClass = AMDGPU::VReg_32RegClassID;
1467 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1468 RegClass = AMDGPU::VReg_64RegClassID;
1472 // Nothing to do if they fit naturally
1473 if (fitsRegClass(DAG, Operand, RegClass))
1476 // If the scalar slot isn't used yet use it now
1477 if (!ScalarSlotUsed) {
1478 ScalarSlotUsed = true;
1482 // This is a conservative aproach. It is possible that we can't determine the
1483 // correct register class and copy too often, but better safe than sorry.
1486 // We can't use COPY_TO_REGCLASS with FrameIndex arguments.
1487 if (isa<FrameIndexSDNode>(Operand)) {
1488 unsigned Opcode = Operand.getValueType() == MVT::i32 ?
1489 AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
1490 Node = DAG.getMachineNode(Opcode, SDLoc(), Operand.getValueType(),
1493 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1494 Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
1495 Operand.getValueType(), Operand, RC);
1497 Operand = SDValue(Node, 0);
1500 /// \returns true if \p Node's operands are different from the SDValue list
1502 static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1503 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1504 if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1511 /// \brief Try to fold the Nodes operands into the Node
1512 SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
1513 SelectionDAG &DAG) const {
1515 // Original encoding (either e32 or e64)
1516 int Opcode = Node->getMachineOpcode();
1517 const SIInstrInfo *TII =
1518 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1519 const MCInstrDesc *Desc = &TII->get(Opcode);
1521 unsigned NumDefs = Desc->getNumDefs();
1522 unsigned NumOps = Desc->getNumOperands();
1524 // Commuted opcode if available
1525 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1526 const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1528 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1529 assert(!DescRev || DescRev->getNumOperands() == NumOps);
1531 // e64 version if available, -1 otherwise
1532 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1533 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
1534 int InputModifiers[3] = {0};
1536 assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
1538 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1539 bool HaveVSrc = false, HaveSSrc = false;
1541 // First figure out what we already have in this instruction.
1542 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1543 i != e && Op < NumOps; ++i, ++Op) {
1545 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1546 if (isVSrc(RegClass))
1548 else if (isSSrc(RegClass))
1553 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1554 if (Imm != -1 && Imm != 0) {
1555 // Literal immediate
1560 // If we neither have VSrc nor SSrc, it makes no sense to continue.
1561 if (!HaveVSrc && !HaveSSrc)
1564 // No scalar allowed when we have both VSrc and SSrc
1565 bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1567 // Second go over the operands and try to fold them
1568 std::vector<SDValue> Ops;
1569 bool Promote2e64 = false;
1570 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1571 i != e && Op < NumOps; ++i, ++Op) {
1573 const SDValue &Operand = Node->getOperand(i);
1574 Ops.push_back(Operand);
1576 // Already folded immediate?
1577 if (isa<ConstantSDNode>(Operand.getNode()) ||
1578 isa<ConstantFPSDNode>(Operand.getNode()))
1581 // Is this a VSrc or SSrc operand?
1582 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1583 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1584 // Try to fold the immediates
1585 if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
1586 // Folding didn't work, make sure we don't hit the SReg limit.
1587 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1591 // If it's not a VSrc or SSrc operand check if we have a GlobalAddress.
1592 // These will be lowered to immediates, so we will need to insert a MOV.
1593 if (isa<GlobalAddressSDNode>(Ops[i])) {
1594 SDNode *Node = DAG.getMachineNode(AMDGPU::V_MOV_B32_e32, SDLoc(),
1595 Operand.getValueType(), Operand);
1596 Ops[i] = SDValue(Node, 0);
1600 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1602 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1603 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1605 // Test if it makes sense to swap operands
1606 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1607 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1608 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1610 // Swap commutable operands
1611 std::swap(Ops[0], Ops[1]);
1623 // Test if it makes sense to switch to e64 encoding
1624 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1625 if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
1628 int32_t TmpImm = -1;
1629 if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
1630 (!fitsRegClass(DAG, Ops[i], RegClass) &&
1631 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1633 // Switch to e64 encoding
1641 if (!DescE64 && !Promote2e64)
1643 if (!Operand.isMachineOpcode())
1648 std::vector<SDValue> OldOps(Ops);
1650 bool HasModifiers = TII->hasModifiers(Desc->Opcode);
1651 for (unsigned i = 0; i < OldOps.size(); ++i) {
1654 Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
1655 Ops.push_back(OldOps[i]);
1657 // Add the modifier flags while promoting
1659 for (unsigned i = 0; i < 2; ++i)
1660 Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
1664 // Add optional chain and glue
1665 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1666 Ops.push_back(Node->getOperand(i));
1668 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1669 // this case a brand new node is always be created, even if the operands
1670 // are the same as before. So, manually check if anything has been changed.
1671 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1675 // Create a complete new instruction
1676 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1679 /// \brief Helper function for adjustWritemask
1680 static unsigned SubIdx2Lane(unsigned Idx) {
1683 case AMDGPU::sub0: return 0;
1684 case AMDGPU::sub1: return 1;
1685 case AMDGPU::sub2: return 2;
1686 case AMDGPU::sub3: return 3;
1690 /// \brief Adjust the writemask of MIMG instructions
1691 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1692 SelectionDAG &DAG) const {
1693 SDNode *Users[4] = { };
1695 unsigned OldDmask = Node->getConstantOperandVal(0);
1696 unsigned NewDmask = 0;
1698 // Try to figure out the used register components
1699 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1702 // Abort if we can't understand the usage
1703 if (!I->isMachineOpcode() ||
1704 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1707 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1708 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1709 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1711 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1713 // Set which texture component corresponds to the lane.
1715 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1717 Comp = countTrailingZeros(Dmask);
1718 Dmask &= ~(1 << Comp);
1721 // Abort if we have more than one user per component
1726 NewDmask |= 1 << Comp;
1729 // Abort if there's no change
1730 if (NewDmask == OldDmask)
1733 // Adjust the writemask in the node
1734 std::vector<SDValue> Ops;
1735 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1736 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1737 Ops.push_back(Node->getOperand(i));
1738 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1740 // If we only got one lane, replace it with a copy
1741 // (if NewDmask has only one bit set...)
1742 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1743 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1744 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1745 SDLoc(), Users[Lane]->getValueType(0),
1746 SDValue(Node, 0), RC);
1747 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1751 // Update the users of the node with the new indices
1752 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1754 SDNode *User = Users[i];
1758 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1759 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1763 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1764 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1765 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1770 /// \brief Fold the instructions after selecting them.
1771 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1772 SelectionDAG &DAG) const {
1773 const SIInstrInfo *TII =
1774 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1775 Node = AdjustRegClass(Node, DAG);
1777 if (TII->isMIMG(Node->getMachineOpcode()))
1778 adjustWritemask(Node, DAG);
1780 return foldOperands(Node, DAG);
1783 /// \brief Assign the register class depending on the number of
1784 /// bits set in the writemask
1785 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1786 SDNode *Node) const {
1787 const SIInstrInfo *TII =
1788 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1789 if (!TII->isMIMG(MI->getOpcode()))
1792 unsigned VReg = MI->getOperand(0).getReg();
1793 unsigned Writemask = MI->getOperand(1).getImm();
1794 unsigned BitsSet = 0;
1795 for (unsigned i = 0; i < 4; ++i)
1796 BitsSet += Writemask & (1 << i) ? 1 : 0;
1798 const TargetRegisterClass *RC;
1801 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1802 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1803 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1806 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1807 MI->setDesc(TII->get(NewOpcode));
1808 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1809 MRI.setRegClass(VReg, RC);
1812 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1813 SelectionDAG &DAG) const {
1816 unsigned NewOpcode = N->getMachineOpcode();
1818 switch (N->getMachineOpcode()) {
1820 case AMDGPU::S_LOAD_DWORD_IMM:
1821 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1823 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1824 if (NewOpcode == N->getMachineOpcode()) {
1825 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1828 case AMDGPU::S_LOAD_DWORDX4_IMM:
1829 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1830 if (NewOpcode == N->getMachineOpcode()) {
1831 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1833 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1836 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
1838 SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
1839 DAG.getConstant(0, MVT::i64)), 0),
1841 DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
1843 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
1848 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1849 const TargetRegisterClass *RC,
1850 unsigned Reg, EVT VT) const {
1851 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1853 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1854 cast<RegisterSDNode>(VReg)->getReg(), VT);