1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_R600_SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering : public AMDGPUTargetLowering {
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset, bool Signed) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
29 SelectionDAG &DAG) const override;
31 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
40 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
41 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
42 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
43 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
45 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
46 const SDValue &Op) const;
47 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
48 unsigned RegClass) const;
50 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
51 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
53 SDValue performUCharToFloatCombine(SDNode *N,
54 DAGCombinerInfo &DCI) const;
55 SDValue performSHLPtrCombine(SDNode *N,
57 DAGCombinerInfo &DCI) const;
58 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
59 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
60 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
62 SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
63 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
66 SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI);
68 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
69 EVT /*VT*/) const override;
71 bool isLegalAddressingMode(const AddrMode &AM,
72 Type *Ty) const override;
74 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
76 bool *IsFast) const override;
78 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
79 unsigned SrcAlign, bool IsMemset,
82 MachineFunction &MF) const override;
84 TargetLoweringBase::LegalizeTypeAction
85 getPreferredVectorAction(EVT VT) const override;
87 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
88 Type *Ty) const override;
90 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
92 const SmallVectorImpl<ISD::InputArg> &Ins,
93 SDLoc DL, SelectionDAG &DAG,
94 SmallVectorImpl<SDValue> &InVals) const override;
96 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
97 MachineBasicBlock * BB) const override;
98 bool enableAggressiveFMAFusion(EVT VT) const override;
99 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
100 MVT getScalarShiftAmountTy(EVT VT) const override;
101 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
102 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
103 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
104 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
105 void AdjustInstrPostInstrSelection(MachineInstr *MI,
106 SDNode *Node) const override;
108 int32_t analyzeImmediate(const SDNode *N) const;
109 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
110 unsigned Reg, EVT VT) const override;
111 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
113 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const;
114 MachineSDNode *buildRSRC(SelectionDAG &DAG,
118 uint64_t RsrcDword2And3) const;
119 MachineSDNode *buildScratchRSRC(SelectionDAG &DAG,
124 } // End namespace llvm