1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_R600_SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering : public AMDGPUTargetLowering {
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset, bool Signed) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
29 SelectionDAG &DAG) const override;
31 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
40 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
41 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
42 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
43 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
45 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
47 SDValue performUCharToFloatCombine(SDNode *N,
48 DAGCombinerInfo &DCI) const;
49 SDValue performSHLPtrCombine(SDNode *N,
51 DAGCombinerInfo &DCI) const;
52 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
53 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
54 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
56 SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
57 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
60 SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI);
62 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
63 EVT /*VT*/) const override;
65 bool isLegalAddressingMode(const AddrMode &AM,
66 Type *Ty) const override;
68 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
70 bool *IsFast) const override;
72 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
73 unsigned SrcAlign, bool IsMemset,
76 MachineFunction &MF) const override;
78 TargetLoweringBase::LegalizeTypeAction
79 getPreferredVectorAction(EVT VT) const override;
81 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
82 Type *Ty) const override;
84 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
86 const SmallVectorImpl<ISD::InputArg> &Ins,
87 SDLoc DL, SelectionDAG &DAG,
88 SmallVectorImpl<SDValue> &InVals) const override;
90 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
91 MachineBasicBlock * BB) const override;
92 bool enableAggressiveFMAFusion(EVT VT) const override;
93 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
94 MVT getScalarShiftAmountTy(EVT VT) const override;
95 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
96 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
97 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
98 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
99 void AdjustInstrPostInstrSelection(MachineInstr *MI,
100 SDNode *Node) const override;
102 int32_t analyzeImmediate(const SDNode *N) const;
103 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
104 unsigned Reg, EVT VT) const override;
105 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
107 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const;
108 MachineSDNode *buildRSRC(SelectionDAG &DAG,
112 uint64_t RsrcDword2And3) const;
113 MachineSDNode *buildScratchRSRC(SelectionDAG &DAG,
118 } // End namespace llvm