1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef SIISELLOWERING_H
16 #define SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering : public AMDGPUTargetLowering {
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset, bool Signed) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
28 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
29 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
30 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
31 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
36 bool foldImm(SDValue &Operand, int32_t &Immediate,
37 bool &ScalarSlotUsed) const;
38 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
39 const SDValue &Op) const;
40 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
41 unsigned RegClass) const;
42 void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
43 unsigned RegClass, bool &ScalarSlotUsed) const;
45 SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
46 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
47 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
50 SITargetLowering(TargetMachine &tm);
51 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
52 bool *IsFast) const override;
53 bool shouldSplitVectorType(EVT VT) const override;
55 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
56 Type *Ty) const override;
58 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
60 const SmallVectorImpl<ISD::InputArg> &Ins,
61 SDLoc DL, SelectionDAG &DAG,
62 SmallVectorImpl<SDValue> &InVals) const override;
64 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
65 MachineBasicBlock * BB) const override;
66 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
67 MVT getScalarShiftAmountTy(EVT VT) const override;
68 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
69 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
70 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
71 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
72 void AdjustInstrPostInstrSelection(MachineInstr *MI,
73 SDNode *Node) const override;
75 int32_t analyzeImmediate(const SDNode *N) const;
76 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
77 unsigned Reg, EVT VT) const override;
80 } // End namespace llvm
82 #endif //SIISELLOWERING_H