1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef SIISELLOWERING_H
16 #define SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering : public AMDGPUTargetLowering {
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset, bool Signed) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
29 SelectionDAG &DAG) const override;
30 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
31 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
40 bool foldImm(SDValue &Operand, int32_t &Immediate,
41 bool &ScalarSlotUsed) const;
42 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
43 const SDValue &Op) const;
44 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
45 unsigned RegClass) const;
46 void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
47 unsigned RegClass, bool &ScalarSlotUsed) const;
49 SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
50 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
51 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
53 static SDValue performUCharToFloatCombine(SDNode *N,
54 DAGCombinerInfo &DCI);
57 SITargetLowering(TargetMachine &tm);
58 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
59 bool *IsFast) const override;
61 TargetLoweringBase::LegalizeTypeAction
62 getPreferredVectorAction(EVT VT) const override;
64 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
65 Type *Ty) const override;
67 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
69 const SmallVectorImpl<ISD::InputArg> &Ins,
70 SDLoc DL, SelectionDAG &DAG,
71 SmallVectorImpl<SDValue> &InVals) const override;
73 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
74 MachineBasicBlock * BB) const override;
75 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
76 MVT getScalarShiftAmountTy(EVT VT) const override;
77 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
78 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
79 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
80 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
81 void AdjustInstrPostInstrSelection(MachineInstr *MI,
82 SDNode *Node) const override;
84 int32_t analyzeImmediate(const SDNode *N) const;
85 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
86 unsigned Reg, EVT VT) const override;
89 } // End namespace llvm
91 #endif //SIISELLOWERING_H