1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef SIISELLOWERING_H
16 #define SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering : public AMDGPUTargetLowering {
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
28 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
29 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
30 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
31 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
36 SDValue ResourceDescriptorToi128(SDValue Op, SelectionDAG &DAG) const;
37 bool foldImm(SDValue &Operand, int32_t &Immediate,
38 bool &ScalarSlotUsed) const;
39 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
40 const SDValue &Op) const;
41 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
42 unsigned RegClass) const;
43 void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
44 unsigned RegClass, bool &ScalarSlotUsed) const;
46 SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
47 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
48 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
51 SITargetLowering(TargetMachine &tm);
52 bool allowsUnalignedMemoryAccesses(EVT VT, bool *IsFast) const;
53 virtual bool shouldSplitVectorElementType(EVT VT) const;
55 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
57 const SmallVectorImpl<ISD::InputArg> &Ins,
58 SDLoc DL, SelectionDAG &DAG,
59 SmallVectorImpl<SDValue> &InVals) const;
61 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
62 MachineBasicBlock * BB) const;
63 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
64 virtual MVT getScalarShiftAmountTy(EVT VT) const;
65 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
66 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
67 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
69 virtual void AdjustInstrPostInstrSelection(MachineInstr *MI,
72 int32_t analyzeImmediate(const SDNode *N) const;
73 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
74 unsigned Reg, EVT VT) const;
77 } // End namespace llvm
79 #endif //SIISELLOWERING_H