1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Insert wait instructions for memory reads and writes.
13 /// Memory reads and writes are issued asynchronously, so we need to insert
14 /// S_WAITCNT instructions when we want to access any of their results or
15 /// overwrite any register that's used asynchronously.
17 //===----------------------------------------------------------------------===//
20 #include "AMDGPUSubtarget.h"
21 #include "SIInstrInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 /// \brief One variable for each of the hardware counters
43 typedef Counters RegCounters[512];
44 typedef std::pair<unsigned, unsigned> RegInterval;
46 class SIInsertWaits : public MachineFunctionPass {
50 const SIInstrInfo *TII;
51 const SIRegisterInfo *TRI;
52 const MachineRegisterInfo *MRI;
54 /// \brief Constant hardware limits
55 static const Counters WaitCounts;
57 /// \brief Constant zero value
58 static const Counters ZeroCounts;
60 /// \brief Counter values we have already waited on.
63 /// \brief Counter values for last instruction issued.
66 /// \brief Registers used by async instructions.
69 /// \brief Registers defined by async instructions.
70 RegCounters DefinedRegs;
72 /// \brief Different export instruction types seen since last wait.
73 unsigned ExpInstrTypesSeen;
75 /// \brief Get increment/decrement amount for this instruction.
76 Counters getHwCounts(MachineInstr &MI);
78 /// \brief Is operand relevant for async execution?
79 bool isOpRelevant(MachineOperand &Op);
81 /// \brief Get register interval an operand affects.
82 RegInterval getRegInterval(MachineOperand &Op);
84 /// \brief Handle instructions async components
85 void pushInstruction(MachineInstr &MI);
87 /// \brief Insert the actual wait instruction
88 bool insertWait(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator I,
90 const Counters &Counts);
92 /// \brief Do we need def2def checks?
93 bool unorderedDefines(MachineInstr &MI);
95 /// \brief Resolve all operand dependencies to counter requirements
96 Counters handleOperands(MachineInstr &MI);
99 SIInsertWaits(TargetMachine &tm) :
100 MachineFunctionPass(ID),
103 ExpInstrTypesSeen(0) { }
105 bool runOnMachineFunction(MachineFunction &MF) override;
107 const char *getPassName() const override {
108 return "SI insert wait instructions";
113 } // End anonymous namespace
115 char SIInsertWaits::ID = 0;
117 const Counters SIInsertWaits::WaitCounts = { { 15, 7, 7 } };
118 const Counters SIInsertWaits::ZeroCounts = { { 0, 0, 0 } };
120 FunctionPass *llvm::createSIInsertWaits(TargetMachine &tm) {
121 return new SIInsertWaits(tm);
124 Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
126 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
129 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
131 // Only consider stores or EXP for EXP_CNT
132 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
133 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
135 // LGKM may uses larger values
136 if (TSFlags & SIInstrFlags::LGKM_CNT) {
138 if (TII->isSMRD(MI.getOpcode())) {
140 MachineOperand &Op = MI.getOperand(0);
141 assert(Op.isReg() && "First LGKM operand must be a register!");
143 unsigned Reg = Op.getReg();
144 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
145 Result.Named.LGKM = Size > 4 ? 2 : 1;
149 Result.Named.LGKM = 1;
153 Result.Named.LGKM = 0;
159 bool SIInsertWaits::isOpRelevant(MachineOperand &Op) {
161 // Constants are always irrelevant
165 // Defines are always relevant
169 // For exports all registers are relevant
170 MachineInstr &MI = *Op.getParent();
171 if (MI.getOpcode() == AMDGPU::EXP)
174 // For stores the stored value is also relevant
175 if (!MI.getDesc().mayStore())
178 for (MachineInstr::mop_iterator I = MI.operands_begin(),
179 E = MI.operands_end(); I != E; ++I) {
181 if (I->isReg() && I->isUse())
182 return Op.isIdenticalTo(*I);
188 RegInterval SIInsertWaits::getRegInterval(MachineOperand &Op) {
190 if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg()))
191 return std::make_pair(0, 0);
193 unsigned Reg = Op.getReg();
194 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
199 Result.first = TRI->getEncodingValue(Reg);
200 Result.second = Result.first + Size / 4;
205 void SIInsertWaits::pushInstruction(MachineInstr &MI) {
207 // Get the hardware counter increments and sum them up
208 Counters Increment = getHwCounts(MI);
211 for (unsigned i = 0; i < 3; ++i) {
212 LastIssued.Array[i] += Increment.Array[i];
213 Sum += Increment.Array[i];
216 // If we don't increase anything then that's it
220 // Remember which export instructions we have seen
221 if (Increment.Named.EXP) {
222 ExpInstrTypesSeen |= MI.getOpcode() == AMDGPU::EXP ? 1 : 2;
225 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
227 MachineOperand &Op = MI.getOperand(i);
228 if (!isOpRelevant(Op))
231 RegInterval Interval = getRegInterval(Op);
232 for (unsigned j = Interval.first; j < Interval.second; ++j) {
234 // Remember which registers we define
236 DefinedRegs[j] = LastIssued;
238 // and which one we are using
240 UsedRegs[j] = LastIssued;
245 bool SIInsertWaits::insertWait(MachineBasicBlock &MBB,
246 MachineBasicBlock::iterator I,
247 const Counters &Required) {
249 // End of program? No need to wait on anything
250 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
253 // Figure out if the async instructions execute in order
256 // VM_CNT is always ordered
259 // EXP_CNT is unordered if we have both EXP & VM-writes
260 Ordered[1] = ExpInstrTypesSeen == 3;
262 // LGKM_CNT is handled as always unordered. TODO: Handle LDS and GDS
265 // The values we are going to put into the S_WAITCNT instruction
266 Counters Counts = WaitCounts;
268 // Do we really need to wait?
269 bool NeedWait = false;
271 for (unsigned i = 0; i < 3; ++i) {
273 if (Required.Array[i] <= WaitedOn.Array[i])
279 unsigned Value = LastIssued.Array[i] - Required.Array[i];
281 // Adjust the value to the real hardware possibilities.
282 Counts.Array[i] = std::min(Value, WaitCounts.Array[i]);
287 // Remember on what we have waited on.
288 WaitedOn.Array[i] = LastIssued.Array[i] - Counts.Array[i];
294 // Reset EXP_CNT instruction types
295 if (Counts.Named.EXP == 0)
296 ExpInstrTypesSeen = 0;
298 // Build the wait instruction
299 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
300 .addImm((Counts.Named.VM & 0xF) |
301 ((Counts.Named.EXP & 0x7) << 4) |
302 ((Counts.Named.LGKM & 0x7) << 8));
307 /// \brief helper function for handleOperands
308 static void increaseCounters(Counters &Dst, const Counters &Src) {
310 for (unsigned i = 0; i < 3; ++i)
311 Dst.Array[i] = std::max(Dst.Array[i], Src.Array[i]);
314 Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
316 Counters Result = ZeroCounts;
318 // S_SENDMSG implicitly waits for all outstanding LGKM transfers to finish,
319 // but we also want to wait for any other outstanding transfers before
320 // signalling other hardware blocks
321 if (MI.getOpcode() == AMDGPU::S_SENDMSG)
324 // For each register affected by this
325 // instruction increase the result sequence
326 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
328 MachineOperand &Op = MI.getOperand(i);
329 RegInterval Interval = getRegInterval(Op);
330 for (unsigned j = Interval.first; j < Interval.second; ++j) {
333 increaseCounters(Result, UsedRegs[j]);
334 increaseCounters(Result, DefinedRegs[j]);
338 increaseCounters(Result, DefinedRegs[j]);
345 // FIXME: Insert waits listed in Table 4.2 "Required User-Inserted Wait States"
346 // around other non-memory instructions.
347 bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
348 bool Changes = false;
350 TII = static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
352 static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
354 MRI = &MF.getRegInfo();
356 WaitedOn = ZeroCounts;
357 LastIssued = ZeroCounts;
359 memset(&UsedRegs, 0, sizeof(UsedRegs));
360 memset(&DefinedRegs, 0, sizeof(DefinedRegs));
362 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
365 MachineBasicBlock &MBB = *BI;
366 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
369 Changes |= insertWait(MBB, I, handleOperands(*I));
373 // Wait for everything at the end of the MBB
374 Changes |= insertWait(MBB, MBB.getFirstTerminator(), LastIssued);