1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Insert wait instructions for memory reads and writes.
13 /// Memory reads and writes are issued asynchronously, so we need to insert
14 /// S_WAITCNT instructions when we want to access any of their results or
15 /// overwrite any register that's used asynchronously.
17 //===----------------------------------------------------------------------===//
20 #include "SIInstrInfo.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 /// \brief One variable for each of the hardware counters
42 typedef Counters RegCounters[512];
43 typedef std::pair<unsigned, unsigned> RegInterval;
45 class SIInsertWaits : public MachineFunctionPass {
49 const SIInstrInfo *TII;
50 const SIRegisterInfo *TRI;
51 const MachineRegisterInfo *MRI;
53 /// \brief Constant hardware limits
54 static const Counters WaitCounts;
56 /// \brief Constant zero value
57 static const Counters ZeroCounts;
59 /// \brief Counter values we have already waited on.
62 /// \brief Counter values for last instruction issued.
65 /// \brief Registers used by async instructions.
68 /// \brief Registers defined by async instructions.
69 RegCounters DefinedRegs;
71 /// \brief Different export instruction types seen since last wait.
72 unsigned ExpInstrTypesSeen;
74 /// \brief Get increment/decrement amount for this instruction.
75 Counters getHwCounts(MachineInstr &MI);
77 /// \brief Is operand relevant for async execution?
78 bool isOpRelevant(MachineOperand &Op);
80 /// \brief Get register interval an operand affects.
81 RegInterval getRegInterval(MachineOperand &Op);
83 /// \brief Handle instructions async components
84 void pushInstruction(MachineInstr &MI);
86 /// \brief Insert the actual wait instruction
87 bool insertWait(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator I,
89 const Counters &Counts);
91 /// \brief Do we need def2def checks?
92 bool unorderedDefines(MachineInstr &MI);
94 /// \brief Resolve all operand dependencies to counter requirements
95 Counters handleOperands(MachineInstr &MI);
98 SIInsertWaits(TargetMachine &tm) :
99 MachineFunctionPass(ID),
102 ExpInstrTypesSeen(0) { }
104 bool runOnMachineFunction(MachineFunction &MF) override;
106 const char *getPassName() const override {
107 return "SI insert wait instructions";
112 } // End anonymous namespace
114 char SIInsertWaits::ID = 0;
116 const Counters SIInsertWaits::WaitCounts = { { 15, 7, 7 } };
117 const Counters SIInsertWaits::ZeroCounts = { { 0, 0, 0 } };
119 FunctionPass *llvm::createSIInsertWaits(TargetMachine &tm) {
120 return new SIInsertWaits(tm);
123 Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
125 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
128 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
130 // Only consider stores or EXP for EXP_CNT
131 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
132 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
134 // LGKM may uses larger values
135 if (TSFlags & SIInstrFlags::LGKM_CNT) {
137 if (TII->isSMRD(MI.getOpcode())) {
139 MachineOperand &Op = MI.getOperand(0);
140 assert(Op.isReg() && "First LGKM operand must be a register!");
142 unsigned Reg = Op.getReg();
143 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
144 Result.Named.LGKM = Size > 4 ? 2 : 1;
148 Result.Named.LGKM = 1;
152 Result.Named.LGKM = 0;
158 bool SIInsertWaits::isOpRelevant(MachineOperand &Op) {
160 // Constants are always irrelevant
164 // Defines are always relevant
168 // For exports all registers are relevant
169 MachineInstr &MI = *Op.getParent();
170 if (MI.getOpcode() == AMDGPU::EXP)
173 // For stores the stored value is also relevant
174 if (!MI.getDesc().mayStore())
177 for (MachineInstr::mop_iterator I = MI.operands_begin(),
178 E = MI.operands_end(); I != E; ++I) {
180 if (I->isReg() && I->isUse())
181 return Op.isIdenticalTo(*I);
187 RegInterval SIInsertWaits::getRegInterval(MachineOperand &Op) {
189 if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg()))
190 return std::make_pair(0, 0);
192 unsigned Reg = Op.getReg();
193 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
198 Result.first = TRI->getEncodingValue(Reg);
199 Result.second = Result.first + Size / 4;
204 void SIInsertWaits::pushInstruction(MachineInstr &MI) {
206 // Get the hardware counter increments and sum them up
207 Counters Increment = getHwCounts(MI);
210 for (unsigned i = 0; i < 3; ++i) {
211 LastIssued.Array[i] += Increment.Array[i];
212 Sum += Increment.Array[i];
215 // If we don't increase anything then that's it
219 // Remember which export instructions we have seen
220 if (Increment.Named.EXP) {
221 ExpInstrTypesSeen |= MI.getOpcode() == AMDGPU::EXP ? 1 : 2;
224 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
226 MachineOperand &Op = MI.getOperand(i);
227 if (!isOpRelevant(Op))
230 RegInterval Interval = getRegInterval(Op);
231 for (unsigned j = Interval.first; j < Interval.second; ++j) {
233 // Remember which registers we define
235 DefinedRegs[j] = LastIssued;
237 // and which one we are using
239 UsedRegs[j] = LastIssued;
244 bool SIInsertWaits::insertWait(MachineBasicBlock &MBB,
245 MachineBasicBlock::iterator I,
246 const Counters &Required) {
248 // End of program? No need to wait on anything
249 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
252 // Figure out if the async instructions execute in order
255 // VM_CNT is always ordered
258 // EXP_CNT is unordered if we have both EXP & VM-writes
259 Ordered[1] = ExpInstrTypesSeen == 3;
261 // LGKM_CNT is handled as always unordered. TODO: Handle LDS and GDS
264 // The values we are going to put into the S_WAITCNT instruction
265 Counters Counts = WaitCounts;
267 // Do we really need to wait?
268 bool NeedWait = false;
270 for (unsigned i = 0; i < 3; ++i) {
272 if (Required.Array[i] <= WaitedOn.Array[i])
278 unsigned Value = LastIssued.Array[i] - Required.Array[i];
280 // adjust the value to the real hardware posibilities
281 Counts.Array[i] = std::min(Value, WaitCounts.Array[i]);
286 // Remember on what we have waited on
287 WaitedOn.Array[i] = LastIssued.Array[i] - Counts.Array[i];
293 // Reset EXP_CNT instruction types
294 if (Counts.Named.EXP == 0)
295 ExpInstrTypesSeen = 0;
297 // Build the wait instruction
298 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
299 .addImm((Counts.Named.VM & 0xF) |
300 ((Counts.Named.EXP & 0x7) << 4) |
301 ((Counts.Named.LGKM & 0x7) << 8));
306 /// \brief helper function for handleOperands
307 static void increaseCounters(Counters &Dst, const Counters &Src) {
309 for (unsigned i = 0; i < 3; ++i)
310 Dst.Array[i] = std::max(Dst.Array[i], Src.Array[i]);
313 Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
315 Counters Result = ZeroCounts;
317 // S_SENDMSG implicitly waits for all outstanding LGKM transfers to finish,
318 // but we also want to wait for any other outstanding transfers before
319 // signalling other hardware blocks
320 if (MI.getOpcode() == AMDGPU::S_SENDMSG)
323 // For each register affected by this
324 // instruction increase the result sequence
325 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
327 MachineOperand &Op = MI.getOperand(i);
328 RegInterval Interval = getRegInterval(Op);
329 for (unsigned j = Interval.first; j < Interval.second; ++j) {
332 increaseCounters(Result, UsedRegs[j]);
333 increaseCounters(Result, DefinedRegs[j]);
337 increaseCounters(Result, DefinedRegs[j]);
344 bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
345 bool Changes = false;
347 TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
348 TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo());
350 MRI = &MF.getRegInfo();
352 WaitedOn = ZeroCounts;
353 LastIssued = ZeroCounts;
355 memset(&UsedRegs, 0, sizeof(UsedRegs));
356 memset(&DefinedRegs, 0, sizeof(DefinedRegs));
358 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
361 MachineBasicBlock &MBB = *BI;
362 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
365 Changes |= insertWait(MBB, I, handleOperands(*I));
369 // Wait for everything at the end of the MBB
370 Changes |= insertWait(MBB, MBB.getFirstTerminator(), LastIssued);