1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Insert wait instructions for memory reads and writes.
13 /// Memory reads and writes are issued asynchronously, so we need to insert
14 /// S_WAITCNT instructions when we want to access any of their results or
15 /// overwrite any register that's used asynchronously.
17 //===----------------------------------------------------------------------===//
20 #include "SIInstrInfo.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 /// \brief One variable for each of the hardware counters
42 typedef Counters RegCounters[512];
43 typedef std::pair<unsigned, unsigned> RegInterval;
45 class SIInsertWaits : public MachineFunctionPass {
49 const SIInstrInfo *TII;
50 const SIRegisterInfo *TRI;
51 const MachineRegisterInfo *MRI;
53 /// \brief Constant hardware limits
54 static const Counters WaitCounts;
56 /// \brief Constant zero value
57 static const Counters ZeroCounts;
59 /// \brief Counter values we have already waited on.
62 /// \brief Counter values for last instruction issued.
65 /// \brief Registers used by async instructions.
68 /// \brief Registers defined by async instructions.
69 RegCounters DefinedRegs;
71 /// \brief Different export instruction types seen since last wait.
72 unsigned ExpInstrTypesSeen;
74 /// \brief Get increment/decrement amount for this instruction.
75 Counters getHwCounts(MachineInstr &MI);
77 /// \brief Is operand relevant for async execution?
78 bool isOpRelevant(MachineOperand &Op);
80 /// \brief Get register interval an operand affects.
81 RegInterval getRegInterval(MachineOperand &Op);
83 /// \brief Handle instructions async components
84 void pushInstruction(MachineInstr &MI);
86 /// \brief Insert the actual wait instruction
87 bool insertWait(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator I,
89 const Counters &Counts);
91 /// \brief Do we need def2def checks?
92 bool unorderedDefines(MachineInstr &MI);
94 /// \brief Resolve all operand dependencies to counter requirements
95 Counters handleOperands(MachineInstr &MI);
98 SIInsertWaits(TargetMachine &tm) :
99 MachineFunctionPass(ID),
103 virtual bool runOnMachineFunction(MachineFunction &MF);
105 const char *getPassName() const {
106 return "SI insert wait instructions";
111 } // End anonymous namespace
113 char SIInsertWaits::ID = 0;
115 const Counters SIInsertWaits::WaitCounts = { { 15, 7, 7 } };
116 const Counters SIInsertWaits::ZeroCounts = { { 0, 0, 0 } };
118 FunctionPass *llvm::createSIInsertWaits(TargetMachine &tm) {
119 return new SIInsertWaits(tm);
122 Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
124 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
127 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
129 // Only consider stores or EXP for EXP_CNT
130 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
131 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
133 // LGKM may uses larger values
134 if (TSFlags & SIInstrFlags::LGKM_CNT) {
136 MachineOperand &Op = MI.getOperand(0);
138 Op = MI.getOperand(1);
139 assert(Op.isReg() && "First LGKM operand must be a register!");
141 unsigned Reg = Op.getReg();
142 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
143 Result.Named.LGKM = Size > 4 ? 2 : 1;
146 Result.Named.LGKM = 0;
152 bool SIInsertWaits::isOpRelevant(MachineOperand &Op) {
154 // Constants are always irrelevant
158 // Defines are always relevant
162 // For exports all registers are relevant
163 MachineInstr &MI = *Op.getParent();
164 if (MI.getOpcode() == AMDGPU::EXP)
167 // For stores the stored value is also relevant
168 if (!MI.getDesc().mayStore())
171 for (MachineInstr::mop_iterator I = MI.operands_begin(),
172 E = MI.operands_end(); I != E; ++I) {
174 if (I->isReg() && I->isUse())
175 return Op.isIdenticalTo(*I);
181 RegInterval SIInsertWaits::getRegInterval(MachineOperand &Op) {
184 return std::make_pair(0, 0);
186 unsigned Reg = Op.getReg();
187 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
192 Result.first = TRI->getEncodingValue(Reg);
193 Result.second = Result.first + Size / 4;
198 void SIInsertWaits::pushInstruction(MachineInstr &MI) {
200 // Get the hardware counter increments and sum them up
201 Counters Increment = getHwCounts(MI);
204 for (unsigned i = 0; i < 3; ++i) {
205 LastIssued.Array[i] += Increment.Array[i];
206 Sum += Increment.Array[i];
209 // If we don't increase anything then that's it
213 // Remember which export instructions we have seen
214 if (Increment.Named.EXP) {
215 ExpInstrTypesSeen |= MI.getOpcode() == AMDGPU::EXP ? 1 : 2;
218 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
220 MachineOperand &Op = MI.getOperand(i);
221 if (!isOpRelevant(Op))
224 RegInterval Interval = getRegInterval(Op);
225 for (unsigned j = Interval.first; j < Interval.second; ++j) {
227 // Remember which registers we define
229 DefinedRegs[j] = LastIssued;
231 // and which one we are using
233 UsedRegs[j] = LastIssued;
238 bool SIInsertWaits::insertWait(MachineBasicBlock &MBB,
239 MachineBasicBlock::iterator I,
240 const Counters &Required) {
242 // End of program? No need to wait on anything
243 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
246 // Figure out if the async instructions execute in order
249 // VM_CNT is always ordered
252 // EXP_CNT is unordered if we have both EXP & VM-writes
253 Ordered[1] = ExpInstrTypesSeen == 3;
255 // LGKM_CNT is handled as always unordered. TODO: Handle LDS and GDS
258 // The values we are going to put into the S_WAITCNT instruction
259 Counters Counts = WaitCounts;
261 // Do we really need to wait?
262 bool NeedWait = false;
264 for (unsigned i = 0; i < 3; ++i) {
266 if (Required.Array[i] <= WaitedOn.Array[i])
272 unsigned Value = LastIssued.Array[i] - Required.Array[i];
274 // adjust the value to the real hardware posibilities
275 Counts.Array[i] = std::min(Value, WaitCounts.Array[i]);
280 // Remember on what we have waited on
281 WaitedOn.Array[i] = LastIssued.Array[i] - Counts.Array[i];
287 // Reset EXP_CNT instruction types
288 if (Counts.Named.EXP == 0)
289 ExpInstrTypesSeen = 0;
291 // Build the wait instruction
292 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
293 .addImm((Counts.Named.VM & 0xF) |
294 ((Counts.Named.EXP & 0x7) << 4) |
295 ((Counts.Named.LGKM & 0x7) << 8));
300 /// \brief helper function for handleOperands
301 static void increaseCounters(Counters &Dst, const Counters &Src) {
303 for (unsigned i = 0; i < 3; ++i)
304 Dst.Array[i] = std::max(Dst.Array[i], Src.Array[i]);
307 Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
309 Counters Result = ZeroCounts;
311 // For each register affected by this
312 // instruction increase the result sequence
313 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
315 MachineOperand &Op = MI.getOperand(i);
316 RegInterval Interval = getRegInterval(Op);
317 for (unsigned j = Interval.first; j < Interval.second; ++j) {
320 increaseCounters(Result, UsedRegs[j]);
321 increaseCounters(Result, DefinedRegs[j]);
325 increaseCounters(Result, DefinedRegs[j]);
332 bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
333 bool Changes = false;
335 TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
336 TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo());
338 MRI = &MF.getRegInfo();
340 WaitedOn = ZeroCounts;
341 LastIssued = ZeroCounts;
343 memset(&UsedRegs, 0, sizeof(UsedRegs));
344 memset(&DefinedRegs, 0, sizeof(DefinedRegs));
346 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
349 MachineBasicBlock &MBB = *BI;
350 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
353 Changes |= insertWait(MBB, I, handleOperands(*I));
357 // Wait for everything at the end of the MBB
358 Changes |= insertWait(MBB, MBB.getFirstTerminator(), LastIssued);