1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
21 field bits<1> SALU = 0;
22 field bits<1> VALU = 0;
24 field bits<1> SOP1 = 0;
25 field bits<1> SOP2 = 0;
26 field bits<1> SOPC = 0;
27 field bits<1> SOPK = 0;
28 field bits<1> SOPP = 0;
30 field bits<1> VOP1 = 0;
31 field bits<1> VOP2 = 0;
32 field bits<1> VOP3 = 0;
33 field bits<1> VOPC = 0;
35 field bits<1> MUBUF = 0;
36 field bits<1> MTBUF = 0;
37 field bits<1> SMRD = 0;
39 field bits<1> MIMG = 0;
40 field bits<1> FLAT = 0;
41 field bits<1> WQM = 0;
43 // These need to be kept in sync with the enum in SIInstrFlags.
44 let TSFlags{0} = VM_CNT;
45 let TSFlags{1} = EXP_CNT;
46 let TSFlags{2} = LGKM_CNT;
48 let TSFlags{3} = SALU;
49 let TSFlags{4} = VALU;
51 let TSFlags{5} = SOP1;
52 let TSFlags{6} = SOP2;
53 let TSFlags{7} = SOPC;
54 let TSFlags{8} = SOPK;
55 let TSFlags{9} = SOPP;
57 let TSFlags{10} = VOP1;
58 let TSFlags{11} = VOP2;
59 let TSFlags{12} = VOP3;
60 let TSFlags{13} = VOPC;
62 let TSFlags{14} = MUBUF;
63 let TSFlags{15} = MTBUF;
64 let TSFlags{16} = SMRD;
66 let TSFlags{18} = MIMG;
67 let TSFlags{19} = FLAT;
68 let TSFlags{20} = WQM;
70 // Most instructions require adjustments after selection to satisfy
71 // operand requirements.
72 let hasPostISelHook = 1;
73 let SchedRW = [Write32Bit];
88 let Uses = [EXEC] in {
90 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
91 InstSI <outs, ins, asm, pattern> {
95 let hasSideEffects = 0;
96 let UseNamedOperandTable = 1;
100 class VOPCCommon <dag ins, string asm, list<dag> pattern> :
101 VOPAnyCommon <(outs VCCReg:$dst), ins, asm, pattern> {
103 let DisableEncoding = "$dst";
108 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
109 VOPAnyCommon <outs, ins, asm, pattern> {
115 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
116 VOPAnyCommon <outs, ins, asm, pattern> {
122 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
123 VOPAnyCommon <outs, ins, asm, pattern> {
125 // Using complex patterns gives VOP3 patterns a very high complexity rating,
126 // but standalone patterns are almost always prefered, so we need to adjust the
127 // priority lower. The goal is to use a high number to reduce complexity to
128 // zero (or less than zero).
129 let AddedComplexity = -1000;
135 } // End Uses = [EXEC]
137 //===----------------------------------------------------------------------===//
139 //===----------------------------------------------------------------------===//
141 class SOP1e <bits<8> op> : Enc32 {
146 let Inst{7-0} = SSRC0;
148 let Inst{22-16} = SDST;
149 let Inst{31-23} = 0x17d; //encoding;
152 class SOP2e <bits<7> op> : Enc32 {
158 let Inst{7-0} = SSRC0;
159 let Inst{15-8} = SSRC1;
160 let Inst{22-16} = SDST;
161 let Inst{29-23} = op;
162 let Inst{31-30} = 0x2; // encoding
165 class SOPCe <bits<7> op> : Enc32 {
170 let Inst{7-0} = SSRC0;
171 let Inst{15-8} = SSRC1;
172 let Inst{22-16} = op;
173 let Inst{31-23} = 0x17e;
176 class SOPKe <bits<5> op> : Enc32 {
181 let Inst{15-0} = SIMM16;
182 let Inst{22-16} = SDST;
183 let Inst{27-23} = op;
184 let Inst{31-28} = 0xb; //encoding
187 class SOPPe <bits<7> op> : Enc32 {
191 let Inst{15-0} = simm16;
192 let Inst{22-16} = op;
193 let Inst{31-23} = 0x17f; // encoding
196 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
202 let Inst{7-0} = OFFSET;
204 let Inst{14-9} = SBASE{6-1};
205 let Inst{21-15} = SDST;
206 let Inst{26-22} = op;
207 let Inst{31-27} = 0x18; //encoding
210 let SchedRW = [WriteSALU] in {
211 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
212 InstSI<outs, ins, asm, pattern> {
215 let hasSideEffects = 0;
220 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
221 InstSI <outs, ins, asm, pattern> {
225 let hasSideEffects = 0;
229 let UseNamedOperandTable = 1;
232 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
233 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
235 let DisableEncoding = "$dst";
238 let hasSideEffects = 0;
242 let UseNamedOperandTable = 1;
245 class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
246 InstSI <outs, ins , asm, pattern> {
250 let hasSideEffects = 0;
254 let UseNamedOperandTable = 1;
257 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
258 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
262 let hasSideEffects = 0;
263 let isCodeGenOnly = 0;
267 let UseNamedOperandTable = 1;
270 } // let SchedRW = [WriteSALU]
272 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
273 InstSI<outs, ins, asm, pattern> {
279 let hasSideEffects = 0;
280 let UseNamedOperandTable = 1;
281 let SchedRW = [WriteSMEM];
284 //===----------------------------------------------------------------------===//
285 // Vector ALU operations
286 //===----------------------------------------------------------------------===//
288 class VOP1e <bits<8> op> : Enc32 {
293 let Inst{8-0} = SRC0;
295 let Inst{24-17} = VDST;
296 let Inst{31-25} = 0x3f; //encoding
299 class VOP2e <bits<6> op> : Enc32 {
305 let Inst{8-0} = SRC0;
306 let Inst{16-9} = VSRC1;
307 let Inst{24-17} = VDST;
308 let Inst{30-25} = op;
309 let Inst{31} = 0x0; //encoding
312 class VOP3e <bits<9> op> : Enc64 {
315 bits<2> src0_modifiers;
317 bits<2> src1_modifiers;
319 bits<2> src2_modifiers;
325 let Inst{8} = src0_modifiers{1};
326 let Inst{9} = src1_modifiers{1};
327 let Inst{10} = src2_modifiers{1};
328 let Inst{11} = clamp;
329 let Inst{25-17} = op;
330 let Inst{31-26} = 0x34; //encoding
331 let Inst{40-32} = src0;
332 let Inst{49-41} = src1;
333 let Inst{58-50} = src2;
334 let Inst{60-59} = omod;
335 let Inst{61} = src0_modifiers{0};
336 let Inst{62} = src1_modifiers{0};
337 let Inst{63} = src2_modifiers{0};
340 class VOP3be <bits<9> op> : Enc64 {
343 bits<2> src0_modifiers;
345 bits<2> src1_modifiers;
347 bits<2> src2_modifiers;
352 let Inst{7-0} = vdst;
353 let Inst{14-8} = sdst;
354 let Inst{25-17} = op;
355 let Inst{31-26} = 0x34; //encoding
356 let Inst{40-32} = src0;
357 let Inst{49-41} = src1;
358 let Inst{58-50} = src2;
359 let Inst{60-59} = omod;
360 let Inst{61} = src0_modifiers{0};
361 let Inst{62} = src1_modifiers{0};
362 let Inst{63} = src2_modifiers{0};
365 class VOPCe <bits<8> op> : Enc32 {
370 let Inst{8-0} = SRC0;
371 let Inst{16-9} = VSRC1;
372 let Inst{24-17} = op;
373 let Inst{31-25} = 0x3e;
376 class VINTRPe <bits<2> op> : Enc32 {
383 let Inst{7-0} = VSRC;
384 let Inst{9-8} = ATTRCHAN;
385 let Inst{15-10} = ATTR;
386 let Inst{17-16} = op;
387 let Inst{25-18} = VDST;
388 let Inst{31-26} = 0x32; // encoding
391 class DSe <bits<8> op> : Enc64 {
401 let Inst{7-0} = offset0;
402 let Inst{15-8} = offset1;
404 let Inst{25-18} = op;
405 let Inst{31-26} = 0x36; //encoding
406 let Inst{39-32} = addr;
407 let Inst{47-40} = data0;
408 let Inst{55-48} = data1;
409 let Inst{63-56} = vdst;
412 class MUBUFe <bits<7> op> : Enc64 {
427 let Inst{11-0} = offset;
428 let Inst{12} = offen;
429 let Inst{13} = idxen;
431 let Inst{15} = addr64;
433 let Inst{24-18} = op;
434 let Inst{31-26} = 0x38; //encoding
435 let Inst{39-32} = vaddr;
436 let Inst{47-40} = vdata;
437 let Inst{52-48} = srsrc{6-2};
440 let Inst{63-56} = soffset;
443 class MTBUFe <bits<3> op> : Enc64 {
459 let Inst{11-0} = OFFSET;
460 let Inst{12} = OFFEN;
461 let Inst{13} = IDXEN;
463 let Inst{15} = ADDR64;
464 let Inst{18-16} = op;
465 let Inst{22-19} = DFMT;
466 let Inst{25-23} = NFMT;
467 let Inst{31-26} = 0x3a; //encoding
468 let Inst{39-32} = VADDR;
469 let Inst{47-40} = VDATA;
470 let Inst{52-48} = SRSRC{6-2};
473 let Inst{63-56} = SOFFSET;
476 class MIMGe <bits<7> op> : Enc64 {
491 let Inst{11-8} = DMASK;
492 let Inst{12} = UNORM;
498 let Inst{24-18} = op;
500 let Inst{31-26} = 0x3c;
501 let Inst{39-32} = VADDR;
502 let Inst{47-40} = VDATA;
503 let Inst{52-48} = SRSRC{6-2};
504 let Inst{57-53} = SSAMP{6-2};
507 class FLATe<bits<7> op> : Enc64 {
518 let Inst{24-18} = op;
519 let Inst{31-26} = 0x37; // Encoding.
520 let Inst{39-32} = addr;
521 let Inst{47-40} = data;
522 // 54-48 is reserved.
524 let Inst{63-56} = vdst;
540 let Inst{10} = COMPR;
543 let Inst{31-26} = 0x3e;
544 let Inst{39-32} = VSRC0;
545 let Inst{47-40} = VSRC1;
546 let Inst{55-48} = VSRC2;
547 let Inst{63-56} = VSRC3;
550 let Uses = [EXEC] in {
552 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
553 VOP1Common <outs, ins, asm, pattern>,
556 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
557 VOP2Common <outs, ins, asm, pattern>, VOP2e<op>;
559 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
560 VOPCCommon <ins, asm, pattern>, VOPCe <op>;
562 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
563 InstSI <outs, ins, asm, pattern> {
566 let hasSideEffects = 0;
569 } // End Uses = [EXEC]
571 //===----------------------------------------------------------------------===//
572 // Vector I/O operations
573 //===----------------------------------------------------------------------===//
575 let Uses = [EXEC] in {
577 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
578 InstSI <outs, ins, asm, pattern> {
582 let UseNamedOperandTable = 1;
583 let DisableEncoding = "$m0";
584 let SchedRW = [WriteLDS];
587 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
588 InstSI<outs, ins, asm, pattern> {
594 let hasSideEffects = 0;
595 let UseNamedOperandTable = 1;
596 let SchedRW = [WriteVMEM];
599 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
600 InstSI<outs, ins, asm, pattern> {
606 let hasSideEffects = 0;
607 let UseNamedOperandTable = 1;
608 let SchedRW = [WriteVMEM];
611 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
612 InstSI<outs, ins, asm, pattern>, FLATe <op> {
614 // Internally, FLAT instruction are executed as both an LDS and a
615 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
616 // and are not considered done until both have been decremented.
620 let Uses = [EXEC, FLAT_SCR]; // M0
622 let UseNamedOperandTable = 1;
623 let hasSideEffects = 0;
626 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
627 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
633 let hasSideEffects = 0; // XXX ????
637 } // End Uses = [EXEC]