1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
20 field bits<1> MIMG = 0;
21 field bits<1> SMRD = 0;
22 field bits<1> VOP1 = 0;
23 field bits<1> VOP2 = 0;
24 field bits<1> VOP3 = 0;
25 field bits<1> VOPC = 0;
26 field bits<1> SALU = 0;
28 let TSFlags{0} = VM_CNT;
29 let TSFlags{1} = EXP_CNT;
30 let TSFlags{2} = LGKM_CNT;
31 let TSFlags{3} = MIMG;
32 let TSFlags{4} = SMRD;
33 let TSFlags{5} = VOP1;
34 let TSFlags{6} = VOP2;
35 let TSFlags{7} = VOP3;
36 let TSFlags{8} = VOPC;
37 let TSFlags{9} = SALU;
40 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
41 InstSI <outs, ins, asm, pattern> {
47 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
48 InstSI <outs, ins, asm, pattern> {
54 //===----------------------------------------------------------------------===//
56 //===----------------------------------------------------------------------===//
58 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
59 Enc32<outs, ins, asm, pattern> {
64 let Inst{7-0} = SSRC0;
66 let Inst{22-16} = SDST;
67 let Inst{31-23} = 0x17d; //encoding;
71 let hasSideEffects = 0;
75 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
76 Enc32 <outs, ins, asm, pattern> {
82 let Inst{7-0} = SSRC0;
83 let Inst{15-8} = SSRC1;
84 let Inst{22-16} = SDST;
86 let Inst{31-30} = 0x2; // encoding
90 let hasSideEffects = 0;
94 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
95 Enc32<outs, ins, asm, pattern> {
100 let Inst{7-0} = SSRC0;
101 let Inst{15-8} = SSRC1;
102 let Inst{22-16} = op;
103 let Inst{31-23} = 0x17e;
105 let DisableEncoding = "$dst";
108 let hasSideEffects = 0;
112 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
113 Enc32 <outs, ins , asm, pattern> {
118 let Inst{15-0} = SIMM16;
119 let Inst{22-16} = SDST;
120 let Inst{27-23} = op;
121 let Inst{31-28} = 0xb; //encoding
125 let hasSideEffects = 0;
129 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
137 let Inst{15-0} = SIMM16;
138 let Inst{22-16} = op;
139 let Inst{31-23} = 0x17f; // encoding
143 let hasSideEffects = 0;
147 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
148 list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
154 let Inst{7-0} = OFFSET;
156 let Inst{14-9} = SBASE{6-1};
157 let Inst{21-15} = SDST;
158 let Inst{26-22} = op;
159 let Inst{31-27} = 0x18; //encoding
165 //===----------------------------------------------------------------------===//
166 // Vector ALU operations
167 //===----------------------------------------------------------------------===//
169 let Uses = [EXEC] in {
171 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
172 Enc32 <outs, ins, asm, pattern> {
177 let Inst{8-0} = SRC0;
179 let Inst{24-17} = VDST;
180 let Inst{31-25} = 0x3f; //encoding
184 let hasSideEffects = 0;
185 let UseNamedOperandTable = 1;
189 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
190 Enc32 <outs, ins, asm, pattern> {
196 let Inst{8-0} = SRC0;
197 let Inst{16-9} = VSRC1;
198 let Inst{24-17} = VDST;
199 let Inst{30-25} = op;
200 let Inst{31} = 0x0; //encoding
204 let hasSideEffects = 0;
205 let UseNamedOperandTable = 1;
209 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
210 Enc64 <outs, ins, asm, pattern> {
213 bits<2> src0_modifiers;
215 bits<2> src1_modifiers;
217 bits<2> src2_modifiers;
223 let Inst{8} = src0_modifiers{1};
224 let Inst{9} = src1_modifiers{1};
225 let Inst{10} = src2_modifiers{1};
226 let Inst{11} = clamp;
227 let Inst{25-17} = op;
228 let Inst{31-26} = 0x34; //encoding
229 let Inst{40-32} = src0;
230 let Inst{49-41} = src1;
231 let Inst{58-50} = src2;
232 let Inst{60-59} = omod;
233 let Inst{61} = src0_modifiers{0};
234 let Inst{62} = src1_modifiers{0};
235 let Inst{63} = src2_modifiers{0};
239 let hasSideEffects = 0;
240 let UseNamedOperandTable = 1;
244 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
245 Enc64 <outs, ins, asm, pattern> {
248 bits<2> src0_modifiers;
250 bits<2> src1_modifiers;
252 bits<2> src2_modifiers;
258 let Inst{14-8} = sdst;
259 let Inst{25-17} = op;
260 let Inst{31-26} = 0x34; //encoding
261 let Inst{40-32} = src0;
262 let Inst{49-41} = src1;
263 let Inst{58-50} = src2;
264 let Inst{60-59} = omod;
265 let Inst{61} = src0_modifiers{0};
266 let Inst{62} = src1_modifiers{0};
267 let Inst{63} = src2_modifiers{0};
271 let hasSideEffects = 0;
272 let UseNamedOperandTable = 1;
276 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
277 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
282 let Inst{8-0} = SRC0;
283 let Inst{16-9} = VSRC1;
284 let Inst{24-17} = op;
285 let Inst{31-25} = 0x3e;
287 let DisableEncoding = "$dst";
290 let hasSideEffects = 0;
294 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
295 Enc32 <outs, ins, asm, pattern> {
302 let Inst{7-0} = VSRC;
303 let Inst{9-8} = ATTRCHAN;
304 let Inst{15-10} = ATTR;
305 let Inst{17-16} = op;
306 let Inst{25-18} = VDST;
307 let Inst{31-26} = 0x32; // encoding
309 let neverHasSideEffects = 1;
314 } // End Uses = [EXEC]
316 //===----------------------------------------------------------------------===//
317 // Vector I/O operations
318 //===----------------------------------------------------------------------===//
320 let Uses = [EXEC] in {
322 class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
323 Enc64 <outs, ins, asm, pattern> {
333 let Inst{7-0} = offset0;
334 let Inst{15-8} = offset1;
336 let Inst{25-18} = op;
337 let Inst{31-26} = 0x36; //encoding
338 let Inst{39-32} = addr;
339 let Inst{47-40} = data0;
340 let Inst{55-48} = data1;
341 let Inst{63-56} = vdst;
346 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
347 Enc64<outs, ins, asm, pattern> {
362 let Inst{11-0} = offset;
363 let Inst{12} = offen;
364 let Inst{13} = idxen;
366 let Inst{15} = addr64;
368 let Inst{24-18} = op;
369 let Inst{31-26} = 0x38; //encoding
370 let Inst{39-32} = vaddr;
371 let Inst{47-40} = vdata;
372 let Inst{52-48} = srsrc{6-2};
375 let Inst{63-56} = soffset;
380 let neverHasSideEffects = 1;
381 let UseNamedOperandTable = 1;
384 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
385 Enc64<outs, ins, asm, pattern> {
401 let Inst{11-0} = OFFSET;
402 let Inst{12} = OFFEN;
403 let Inst{13} = IDXEN;
405 let Inst{15} = ADDR64;
406 let Inst{18-16} = op;
407 let Inst{22-19} = DFMT;
408 let Inst{25-23} = NFMT;
409 let Inst{31-26} = 0x3a; //encoding
410 let Inst{39-32} = VADDR;
411 let Inst{47-40} = VDATA;
412 let Inst{52-48} = SRSRC{6-2};
415 let Inst{63-56} = SOFFSET;
420 let neverHasSideEffects = 1;
423 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
424 Enc64 <outs, ins, asm, pattern> {
439 let Inst{11-8} = DMASK;
440 let Inst{12} = UNORM;
446 let Inst{24-18} = op;
448 let Inst{31-26} = 0x3c;
449 let Inst{39-32} = VADDR;
450 let Inst{47-40} = VDATA;
451 let Inst{52-48} = SRSRC{6-2};
452 let Inst{57-53} = SSAMP{6-2};
461 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
462 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
463 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
478 let Inst{10} = COMPR;
481 let Inst{31-26} = 0x3e;
482 let Inst{39-32} = VSRC0;
483 let Inst{47-40} = VSRC1;
484 let Inst{55-48} = VSRC2;
485 let Inst{63-56} = VSRC3;
490 } // End Uses = [EXEC]