1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
20 field bits<1> MIMG = 0;
21 field bits<1> SMRD = 0;
22 field bits<1> VOP1 = 0;
23 field bits<1> VOP2 = 0;
24 field bits<1> VOP3 = 0;
25 field bits<1> VOPC = 0;
26 field bits<1> SALU = 0;
27 field bits<1> MUBUF = 0;
28 field bits<1> MTBUF = 0;
29 field bits<1> FLAT = 0;
31 // These need to be kept in sync with the enum in SIInstrFlags.
32 let TSFlags{0} = VM_CNT;
33 let TSFlags{1} = EXP_CNT;
34 let TSFlags{2} = LGKM_CNT;
35 let TSFlags{3} = MIMG;
36 let TSFlags{4} = SMRD;
37 let TSFlags{5} = VOP1;
38 let TSFlags{6} = VOP2;
39 let TSFlags{7} = VOP3;
40 let TSFlags{8} = VOPC;
41 let TSFlags{9} = SALU;
42 let TSFlags{10} = MUBUF;
43 let TSFlags{11} = MTBUF;
44 let TSFlags{12} = FLAT;
46 // Most instructions require adjustments after selection to satisfy
47 // operand requirements.
48 let hasPostISelHook = 1;
63 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
64 InstSI <outs, ins, asm, pattern> {
67 let hasSideEffects = 0;
68 let UseNamedOperandTable = 1;
72 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
73 InstSI <outs, ins, asm, pattern> {
77 let hasSideEffects = 0;
78 let UseNamedOperandTable = 1;
79 // Using complex patterns gives VOP3 patterns a very high complexity rating,
80 // but standalone patterns are almost always prefered, so we need to adjust the
81 // priority lower. The goal is to use a high number to reduce complexity to
82 // zero (or less than zero).
83 let AddedComplexity = -1000;
91 //===----------------------------------------------------------------------===//
93 //===----------------------------------------------------------------------===//
95 class SOP1e <bits<8> op> : Enc32 {
100 let Inst{7-0} = SSRC0;
102 let Inst{22-16} = SDST;
103 let Inst{31-23} = 0x17d; //encoding;
106 class SOP2e <bits<7> op> : Enc32 {
112 let Inst{7-0} = SSRC0;
113 let Inst{15-8} = SSRC1;
114 let Inst{22-16} = SDST;
115 let Inst{29-23} = op;
116 let Inst{31-30} = 0x2; // encoding
119 class SOPCe <bits<7> op> : Enc32 {
124 let Inst{7-0} = SSRC0;
125 let Inst{15-8} = SSRC1;
126 let Inst{22-16} = op;
127 let Inst{31-23} = 0x17e;
130 class SOPKe <bits<5> op> : Enc32 {
135 let Inst{15-0} = SIMM16;
136 let Inst{22-16} = SDST;
137 let Inst{27-23} = op;
138 let Inst{31-28} = 0xb; //encoding
141 class SOPPe <bits<7> op> : Enc32 {
145 let Inst{15-0} = simm16;
146 let Inst{22-16} = op;
147 let Inst{31-23} = 0x17f; // encoding
150 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
156 let Inst{7-0} = OFFSET;
158 let Inst{14-9} = SBASE{6-1};
159 let Inst{21-15} = SDST;
160 let Inst{26-22} = op;
161 let Inst{31-27} = 0x18; //encoding
164 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
165 InstSI<outs, ins, asm, pattern>, SOP1e <op> {
169 let hasSideEffects = 0;
173 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
174 InstSI <outs, ins, asm, pattern>, SOP2e<op> {
178 let hasSideEffects = 0;
181 let UseNamedOperandTable = 1;
184 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
185 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
187 let DisableEncoding = "$dst";
190 let hasSideEffects = 0;
193 let UseNamedOperandTable = 1;
196 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
197 InstSI <outs, ins , asm, pattern>, SOPKe<op> {
201 let hasSideEffects = 0;
204 let UseNamedOperandTable = 1;
207 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
208 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
212 let hasSideEffects = 0;
215 let UseNamedOperandTable = 1;
218 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
219 InstSI<outs, ins, asm, pattern> {
225 let UseNamedOperandTable = 1;
228 //===----------------------------------------------------------------------===//
229 // Vector ALU operations
230 //===----------------------------------------------------------------------===//
232 class VOP1e <bits<8> op> : Enc32 {
237 let Inst{8-0} = SRC0;
239 let Inst{24-17} = VDST;
240 let Inst{31-25} = 0x3f; //encoding
243 class VOP2e <bits<6> op> : Enc32 {
249 let Inst{8-0} = SRC0;
250 let Inst{16-9} = VSRC1;
251 let Inst{24-17} = VDST;
252 let Inst{30-25} = op;
253 let Inst{31} = 0x0; //encoding
256 class VOP3e <bits<9> op> : Enc64 {
259 bits<2> src0_modifiers;
261 bits<2> src1_modifiers;
263 bits<2> src2_modifiers;
269 let Inst{8} = src0_modifiers{1};
270 let Inst{9} = src1_modifiers{1};
271 let Inst{10} = src2_modifiers{1};
272 let Inst{11} = clamp;
273 let Inst{25-17} = op;
274 let Inst{31-26} = 0x34; //encoding
275 let Inst{40-32} = src0;
276 let Inst{49-41} = src1;
277 let Inst{58-50} = src2;
278 let Inst{60-59} = omod;
279 let Inst{61} = src0_modifiers{0};
280 let Inst{62} = src1_modifiers{0};
281 let Inst{63} = src2_modifiers{0};
284 class VOP3be <bits<9> op> : Enc64 {
287 bits<2> src0_modifiers;
289 bits<2> src1_modifiers;
291 bits<2> src2_modifiers;
297 let Inst{14-8} = sdst;
298 let Inst{25-17} = op;
299 let Inst{31-26} = 0x34; //encoding
300 let Inst{40-32} = src0;
301 let Inst{49-41} = src1;
302 let Inst{58-50} = src2;
303 let Inst{60-59} = omod;
304 let Inst{61} = src0_modifiers{0};
305 let Inst{62} = src1_modifiers{0};
306 let Inst{63} = src2_modifiers{0};
309 class VOPCe <bits<8> op> : Enc32 {
314 let Inst{8-0} = SRC0;
315 let Inst{16-9} = VSRC1;
316 let Inst{24-17} = op;
317 let Inst{31-25} = 0x3e;
320 class VINTRPe <bits<2> op> : Enc32 {
327 let Inst{7-0} = VSRC;
328 let Inst{9-8} = ATTRCHAN;
329 let Inst{15-10} = ATTR;
330 let Inst{17-16} = op;
331 let Inst{25-18} = VDST;
332 let Inst{31-26} = 0x32; // encoding
335 class DSe <bits<8> op> : Enc64 {
345 let Inst{7-0} = offset0;
346 let Inst{15-8} = offset1;
348 let Inst{25-18} = op;
349 let Inst{31-26} = 0x36; //encoding
350 let Inst{39-32} = addr;
351 let Inst{47-40} = data0;
352 let Inst{55-48} = data1;
353 let Inst{63-56} = vdst;
356 class MUBUFe <bits<7> op> : Enc64 {
371 let Inst{11-0} = offset;
372 let Inst{12} = offen;
373 let Inst{13} = idxen;
375 let Inst{15} = addr64;
377 let Inst{24-18} = op;
378 let Inst{31-26} = 0x38; //encoding
379 let Inst{39-32} = vaddr;
380 let Inst{47-40} = vdata;
381 let Inst{52-48} = srsrc{6-2};
384 let Inst{63-56} = soffset;
387 class MTBUFe <bits<3> op> : Enc64 {
403 let Inst{11-0} = OFFSET;
404 let Inst{12} = OFFEN;
405 let Inst{13} = IDXEN;
407 let Inst{15} = ADDR64;
408 let Inst{18-16} = op;
409 let Inst{22-19} = DFMT;
410 let Inst{25-23} = NFMT;
411 let Inst{31-26} = 0x3a; //encoding
412 let Inst{39-32} = VADDR;
413 let Inst{47-40} = VDATA;
414 let Inst{52-48} = SRSRC{6-2};
417 let Inst{63-56} = SOFFSET;
420 class MIMGe <bits<7> op> : Enc64 {
435 let Inst{11-8} = DMASK;
436 let Inst{12} = UNORM;
442 let Inst{24-18} = op;
444 let Inst{31-26} = 0x3c;
445 let Inst{39-32} = VADDR;
446 let Inst{47-40} = VDATA;
447 let Inst{52-48} = SRSRC{6-2};
448 let Inst{57-53} = SSAMP{6-2};
451 class FLATe<bits<7> op> : Enc64 {
462 let Inst{24-18} = op;
463 let Inst{31-26} = 0x37; // Encoding.
464 let Inst{39-32} = addr;
465 let Inst{47-40} = data;
466 // 54-48 is reserved.
468 let Inst{63-56} = vdst;
484 let Inst{10} = COMPR;
487 let Inst{31-26} = 0x3e;
488 let Inst{39-32} = VSRC0;
489 let Inst{47-40} = VSRC1;
490 let Inst{55-48} = VSRC2;
491 let Inst{63-56} = VSRC3;
494 let Uses = [EXEC] in {
496 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
497 VOP1Common <outs, ins, asm, pattern>,
500 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
501 InstSI <outs, ins, asm, pattern>, VOP2e<op> {
505 let hasSideEffects = 0;
506 let UseNamedOperandTable = 1;
510 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
511 VOP3Common <outs, ins, asm, pattern>, VOP3e<op>;
513 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
514 VOP3Common <outs, ins, asm, pattern>, VOP3be<op>;
516 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
517 InstSI <(outs VCCReg:$dst), ins, asm, pattern>, VOPCe <op> {
519 let DisableEncoding = "$dst";
522 let hasSideEffects = 0;
523 let UseNamedOperandTable = 1;
527 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
528 InstSI <outs, ins, asm, pattern>, VINTRPe<op> {
530 let neverHasSideEffects = 1;
535 } // End Uses = [EXEC]
537 //===----------------------------------------------------------------------===//
538 // Vector I/O operations
539 //===----------------------------------------------------------------------===//
541 let Uses = [EXEC] in {
543 class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
544 InstSI <outs, ins, asm, pattern> , DSe<op> {
547 let UseNamedOperandTable = 1;
550 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
551 InstSI<outs, ins, asm, pattern>, MUBUFe <op> {
557 let neverHasSideEffects = 1;
558 let UseNamedOperandTable = 1;
561 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
562 InstSI<outs, ins, asm, pattern> {
568 let neverHasSideEffects = 1;
569 let UseNamedOperandTable = 1;
572 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
573 InstSI<outs, ins, asm, pattern>, FLATe <op> {
575 // Internally, FLAT instruction are executed as both an LDS and a
576 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
577 // and are not considered done until both have been decremented.
581 let Uses = [EXEC, FLAT_SCR]; // M0
583 let UseNamedOperandTable = 1;
584 let hasSideEffects = 0;
587 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
588 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
597 } // End Uses = [EXEC]