1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
21 field bits<1> SALU = 0;
22 field bits<1> VALU = 0;
24 field bits<1> SOP1 = 0;
25 field bits<1> SOP2 = 0;
26 field bits<1> SOPC = 0;
27 field bits<1> SOPK = 0;
28 field bits<1> SOPP = 0;
30 field bits<1> VOP1 = 0;
31 field bits<1> VOP2 = 0;
32 field bits<1> VOP3 = 0;
33 field bits<1> VOPC = 0;
35 field bits<1> MUBUF = 0;
36 field bits<1> MTBUF = 0;
37 field bits<1> SMRD = 0;
39 field bits<1> MIMG = 0;
40 field bits<1> FLAT = 0;
41 field bits<1> WQM = 0;
43 // These need to be kept in sync with the enum in SIInstrFlags.
44 let TSFlags{0} = VM_CNT;
45 let TSFlags{1} = EXP_CNT;
46 let TSFlags{2} = LGKM_CNT;
48 let TSFlags{3} = SALU;
49 let TSFlags{4} = VALU;
51 let TSFlags{5} = SOP1;
52 let TSFlags{6} = SOP2;
53 let TSFlags{7} = SOPC;
54 let TSFlags{8} = SOPK;
55 let TSFlags{9} = SOPP;
57 let TSFlags{10} = VOP1;
58 let TSFlags{11} = VOP2;
59 let TSFlags{12} = VOP3;
60 let TSFlags{13} = VOPC;
62 let TSFlags{14} = MUBUF;
63 let TSFlags{15} = MTBUF;
64 let TSFlags{16} = SMRD;
66 let TSFlags{18} = MIMG;
67 let TSFlags{19} = FLAT;
68 let TSFlags{20} = WQM;
70 // Most instructions require adjustments after selection to satisfy
71 // operand requirements.
72 let hasPostISelHook = 1;
73 let SchedRW = [Write32Bit];
86 let Uses = [EXEC] in {
88 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
89 InstSI <outs, ins, asm, pattern> {
93 let hasSideEffects = 0;
94 let UseNamedOperandTable = 1;
98 class VOPCCommon <dag ins, string asm, list<dag> pattern> :
99 VOPAnyCommon <(outs VCCReg:$dst), ins, asm, pattern> {
101 let DisableEncoding = "$dst";
106 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
107 VOPAnyCommon <outs, ins, asm, pattern> {
113 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
114 VOPAnyCommon <outs, ins, asm, pattern> {
120 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
121 VOPAnyCommon <outs, ins, asm, pattern> {
123 // Using complex patterns gives VOP3 patterns a very high complexity rating,
124 // but standalone patterns are almost always prefered, so we need to adjust the
125 // priority lower. The goal is to use a high number to reduce complexity to
126 // zero (or less than zero).
127 let AddedComplexity = -1000;
133 } // End Uses = [EXEC]
135 //===----------------------------------------------------------------------===//
137 //===----------------------------------------------------------------------===//
139 class SOP1e <bits<8> op> : Enc32 {
143 let Inst{7-0} = ssrc0;
145 let Inst{22-16} = sdst;
146 let Inst{31-23} = 0x17d; //encoding;
149 class SOP2e <bits<7> op> : Enc32 {
154 let Inst{7-0} = ssrc0;
155 let Inst{15-8} = ssrc1;
156 let Inst{22-16} = sdst;
157 let Inst{29-23} = op;
158 let Inst{31-30} = 0x2; // encoding
161 class SOPCe <bits<7> op> : Enc32 {
165 let Inst{7-0} = ssrc0;
166 let Inst{15-8} = ssrc1;
167 let Inst{22-16} = op;
168 let Inst{31-23} = 0x17e;
171 class SOPKe <bits<5> op> : Enc32 {
175 let Inst{15-0} = simm16;
176 let Inst{22-16} = sdst;
177 let Inst{27-23} = op;
178 let Inst{31-28} = 0xb; //encoding
181 class SOPPe <bits<7> op> : Enc32 {
184 let Inst{15-0} = simm16;
185 let Inst{22-16} = op;
186 let Inst{31-23} = 0x17f; // encoding
189 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
194 let Inst{7-0} = offset;
196 let Inst{14-9} = sbase{6-1};
197 let Inst{21-15} = sdst;
198 let Inst{26-22} = op;
199 let Inst{31-27} = 0x18; //encoding
202 let SchedRW = [WriteSALU] in {
203 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
204 InstSI<outs, ins, asm, pattern> {
207 let hasSideEffects = 0;
212 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
213 InstSI <outs, ins, asm, pattern> {
217 let hasSideEffects = 0;
221 let UseNamedOperandTable = 1;
224 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
225 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
227 let DisableEncoding = "$dst";
230 let hasSideEffects = 0;
234 let UseNamedOperandTable = 1;
237 class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
238 InstSI <outs, ins , asm, pattern> {
242 let hasSideEffects = 0;
246 let UseNamedOperandTable = 1;
249 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
250 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
254 let hasSideEffects = 0;
255 let isCodeGenOnly = 0;
259 let UseNamedOperandTable = 1;
262 } // let SchedRW = [WriteSALU]
264 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
265 InstSI<outs, ins, asm, pattern> {
271 let hasSideEffects = 0;
272 let UseNamedOperandTable = 1;
273 let SchedRW = [WriteSMEM];
276 //===----------------------------------------------------------------------===//
277 // Vector ALU operations
278 //===----------------------------------------------------------------------===//
280 class VOP1e <bits<8> op> : Enc32 {
284 let Inst{8-0} = src0;
286 let Inst{24-17} = vdst;
287 let Inst{31-25} = 0x3f; //encoding
290 class VOP2e <bits<6> op> : Enc32 {
295 let Inst{8-0} = src0;
296 let Inst{16-9} = vsrc1;
297 let Inst{24-17} = vdst;
298 let Inst{30-25} = op;
299 let Inst{31} = 0x0; //encoding
302 class VOP3e <bits<9> op> : Enc64 {
304 bits<2> src0_modifiers;
306 bits<2> src1_modifiers;
308 bits<2> src2_modifiers;
313 let Inst{7-0} = vdst;
314 let Inst{8} = src0_modifiers{1};
315 let Inst{9} = src1_modifiers{1};
316 let Inst{10} = src2_modifiers{1};
317 let Inst{11} = clamp;
318 let Inst{25-17} = op;
319 let Inst{31-26} = 0x34; //encoding
320 let Inst{40-32} = src0;
321 let Inst{49-41} = src1;
322 let Inst{58-50} = src2;
323 let Inst{60-59} = omod;
324 let Inst{61} = src0_modifiers{0};
325 let Inst{62} = src1_modifiers{0};
326 let Inst{63} = src2_modifiers{0};
329 class VOP3be <bits<9> op> : Enc64 {
331 bits<2> src0_modifiers;
333 bits<2> src1_modifiers;
335 bits<2> src2_modifiers;
340 let Inst{7-0} = vdst;
341 let Inst{14-8} = sdst;
342 let Inst{25-17} = op;
343 let Inst{31-26} = 0x34; //encoding
344 let Inst{40-32} = src0;
345 let Inst{49-41} = src1;
346 let Inst{58-50} = src2;
347 let Inst{60-59} = omod;
348 let Inst{61} = src0_modifiers{0};
349 let Inst{62} = src1_modifiers{0};
350 let Inst{63} = src2_modifiers{0};
353 class VOPCe <bits<8> op> : Enc32 {
357 let Inst{8-0} = src0;
358 let Inst{16-9} = vsrc1;
359 let Inst{24-17} = op;
360 let Inst{31-25} = 0x3e;
363 class VINTRPe <bits<2> op> : Enc32 {
369 let Inst{7-0} = vsrc;
370 let Inst{9-8} = attrchan;
371 let Inst{15-10} = attr;
372 let Inst{17-16} = op;
373 let Inst{25-18} = vdst;
374 let Inst{31-26} = 0x32; // encoding
377 class DSe <bits<8> op> : Enc64 {
386 let Inst{7-0} = offset0;
387 let Inst{15-8} = offset1;
389 let Inst{25-18} = op;
390 let Inst{31-26} = 0x36; //encoding
391 let Inst{39-32} = addr;
392 let Inst{47-40} = data0;
393 let Inst{55-48} = data1;
394 let Inst{63-56} = vdst;
397 class MUBUFe <bits<7> op> : Enc64 {
411 let Inst{11-0} = offset;
412 let Inst{12} = offen;
413 let Inst{13} = idxen;
415 let Inst{15} = addr64;
417 let Inst{24-18} = op;
418 let Inst{31-26} = 0x38; //encoding
419 let Inst{39-32} = vaddr;
420 let Inst{47-40} = vdata;
421 let Inst{52-48} = srsrc{6-2};
424 let Inst{63-56} = soffset;
427 class MTBUFe <bits<3> op> : Enc64 {
442 let Inst{11-0} = offset;
443 let Inst{12} = offen;
444 let Inst{13} = idxen;
446 let Inst{15} = addr64;
447 let Inst{18-16} = op;
448 let Inst{22-19} = dfmt;
449 let Inst{25-23} = nfmt;
450 let Inst{31-26} = 0x3a; //encoding
451 let Inst{39-32} = vaddr;
452 let Inst{47-40} = vdata;
453 let Inst{52-48} = srsrc{6-2};
456 let Inst{63-56} = soffset;
459 class MIMGe <bits<7> op> : Enc64 {
473 let Inst{11-8} = dmask;
474 let Inst{12} = unorm;
480 let Inst{24-18} = op;
482 let Inst{31-26} = 0x3c;
483 let Inst{39-32} = vaddr;
484 let Inst{47-40} = vdata;
485 let Inst{52-48} = srsrc{6-2};
486 let Inst{57-53} = ssamp{6-2};
489 class FLATe<bits<7> op> : Enc64 {
500 let Inst{24-18} = op;
501 let Inst{31-26} = 0x37; // Encoding.
502 let Inst{39-32} = addr;
503 let Inst{47-40} = data;
504 // 54-48 is reserved.
506 let Inst{63-56} = vdst;
522 let Inst{10} = compr;
525 let Inst{31-26} = 0x3e;
526 let Inst{39-32} = vsrc0;
527 let Inst{47-40} = vsrc1;
528 let Inst{55-48} = vsrc2;
529 let Inst{63-56} = vsrc3;
532 let Uses = [EXEC] in {
534 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
535 VOP1Common <outs, ins, asm, pattern>,
538 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
539 VOP2Common <outs, ins, asm, pattern>, VOP2e<op>;
541 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
542 VOPCCommon <ins, asm, pattern>, VOPCe <op>;
544 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
545 InstSI <outs, ins, asm, pattern> {
548 let hasSideEffects = 0;
551 } // End Uses = [EXEC]
553 //===----------------------------------------------------------------------===//
554 // Vector I/O operations
555 //===----------------------------------------------------------------------===//
557 let Uses = [EXEC] in {
559 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
560 InstSI <outs, ins, asm, pattern> {
564 let UseNamedOperandTable = 1;
565 let DisableEncoding = "$m0";
566 let SchedRW = [WriteLDS];
569 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
570 InstSI<outs, ins, asm, pattern> {
576 let hasSideEffects = 0;
577 let UseNamedOperandTable = 1;
578 let SchedRW = [WriteVMEM];
581 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
582 InstSI<outs, ins, asm, pattern> {
588 let hasSideEffects = 0;
589 let UseNamedOperandTable = 1;
590 let SchedRW = [WriteVMEM];
593 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
594 InstSI<outs, ins, asm, pattern>, FLATe <op> {
596 // Internally, FLAT instruction are executed as both an LDS and a
597 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
598 // and are not considered done until both have been decremented.
602 let Uses = [EXEC, FLAT_SCR]; // M0
604 let UseNamedOperandTable = 1;
605 let hasSideEffects = 0;
608 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
609 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
615 let hasSideEffects = 0; // XXX ????
619 } // End Uses = [EXEC]