1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
20 field bits<1> MIMG = 0;
21 field bits<1> SMRD = 0;
22 field bits<1> VOP1 = 0;
23 field bits<1> VOP2 = 0;
24 field bits<1> VOP3 = 0;
25 field bits<1> VOPC = 0;
26 field bits<1> SALU = 0;
27 field bits<1> MUBUF = 0;
28 field bits<1> MTBUF = 0;
29 field bits<1> FLAT = 0;
31 // These need to be kept in sync with the enum in SIInstrFlags.
32 let TSFlags{0} = VM_CNT;
33 let TSFlags{1} = EXP_CNT;
34 let TSFlags{2} = LGKM_CNT;
35 let TSFlags{3} = MIMG;
36 let TSFlags{4} = SMRD;
37 let TSFlags{5} = VOP1;
38 let TSFlags{6} = VOP2;
39 let TSFlags{7} = VOP3;
40 let TSFlags{8} = VOPC;
41 let TSFlags{9} = SALU;
42 let TSFlags{10} = MUBUF;
43 let TSFlags{11} = MTBUF;
44 let TSFlags{12} = FLAT;
59 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
60 InstSI <outs, ins, asm, pattern> {
64 let hasSideEffects = 0;
65 let UseNamedOperandTable = 1;
66 // Using complex patterns gives VOP3 patterns a very high complexity rating,
67 // but standalone patterns are almost always prefered, so we need to adjust the
68 // priority lower. The goal is to use a high number to reduce complexity to
69 // zero (or less than zero).
70 let AddedComplexity = -1000;
78 //===----------------------------------------------------------------------===//
80 //===----------------------------------------------------------------------===//
82 class SOP1e <bits<8> op> : Enc32 {
87 let Inst{7-0} = SSRC0;
89 let Inst{22-16} = SDST;
90 let Inst{31-23} = 0x17d; //encoding;
93 class SOP2e <bits<7> op> : Enc32 {
99 let Inst{7-0} = SSRC0;
100 let Inst{15-8} = SSRC1;
101 let Inst{22-16} = SDST;
102 let Inst{29-23} = op;
103 let Inst{31-30} = 0x2; // encoding
106 class SOPCe <bits<7> op> : Enc32 {
111 let Inst{7-0} = SSRC0;
112 let Inst{15-8} = SSRC1;
113 let Inst{22-16} = op;
114 let Inst{31-23} = 0x17e;
117 class SOPKe <bits<5> op> : Enc32 {
122 let Inst{15-0} = SIMM16;
123 let Inst{22-16} = SDST;
124 let Inst{27-23} = op;
125 let Inst{31-28} = 0xb; //encoding
128 class SOPPe <bits<7> op> : Enc32 {
132 let Inst{15-0} = simm16;
133 let Inst{22-16} = op;
134 let Inst{31-23} = 0x17f; // encoding
137 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
143 let Inst{7-0} = OFFSET;
145 let Inst{14-9} = SBASE{6-1};
146 let Inst{21-15} = SDST;
147 let Inst{26-22} = op;
148 let Inst{31-27} = 0x18; //encoding
151 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
152 InstSI<outs, ins, asm, pattern>, SOP1e <op> {
156 let hasSideEffects = 0;
160 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
161 InstSI <outs, ins, asm, pattern>, SOP2e<op> {
165 let hasSideEffects = 0;
169 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
170 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
172 let DisableEncoding = "$dst";
175 let hasSideEffects = 0;
179 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
180 InstSI <outs, ins , asm, pattern>, SOPKe<op> {
184 let hasSideEffects = 0;
188 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
189 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
193 let hasSideEffects = 0;
197 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
198 list<dag> pattern> : InstSI<outs, ins, asm, pattern>, SMRDe<op, imm> {
204 let UseNamedOperandTable = 1;
207 //===----------------------------------------------------------------------===//
208 // Vector ALU operations
209 //===----------------------------------------------------------------------===//
211 class VOP1e <bits<8> op> : Enc32 {
216 let Inst{8-0} = SRC0;
218 let Inst{24-17} = VDST;
219 let Inst{31-25} = 0x3f; //encoding
222 class VOP2e <bits<6> op> : Enc32 {
228 let Inst{8-0} = SRC0;
229 let Inst{16-9} = VSRC1;
230 let Inst{24-17} = VDST;
231 let Inst{30-25} = op;
232 let Inst{31} = 0x0; //encoding
235 class VOP3e <bits<9> op> : Enc64 {
238 bits<2> src0_modifiers;
240 bits<2> src1_modifiers;
242 bits<2> src2_modifiers;
248 let Inst{8} = src0_modifiers{1};
249 let Inst{9} = src1_modifiers{1};
250 let Inst{10} = src2_modifiers{1};
251 let Inst{11} = clamp;
252 let Inst{25-17} = op;
253 let Inst{31-26} = 0x34; //encoding
254 let Inst{40-32} = src0;
255 let Inst{49-41} = src1;
256 let Inst{58-50} = src2;
257 let Inst{60-59} = omod;
258 let Inst{61} = src0_modifiers{0};
259 let Inst{62} = src1_modifiers{0};
260 let Inst{63} = src2_modifiers{0};
263 class VOP3be <bits<9> op> : Enc64 {
266 bits<2> src0_modifiers;
268 bits<2> src1_modifiers;
270 bits<2> src2_modifiers;
276 let Inst{14-8} = sdst;
277 let Inst{25-17} = op;
278 let Inst{31-26} = 0x34; //encoding
279 let Inst{40-32} = src0;
280 let Inst{49-41} = src1;
281 let Inst{58-50} = src2;
282 let Inst{60-59} = omod;
283 let Inst{61} = src0_modifiers{0};
284 let Inst{62} = src1_modifiers{0};
285 let Inst{63} = src2_modifiers{0};
288 class VOPCe <bits<8> op> : Enc32 {
293 let Inst{8-0} = SRC0;
294 let Inst{16-9} = VSRC1;
295 let Inst{24-17} = op;
296 let Inst{31-25} = 0x3e;
299 class VINTRPe <bits<2> op> : Enc32 {
306 let Inst{7-0} = VSRC;
307 let Inst{9-8} = ATTRCHAN;
308 let Inst{15-10} = ATTR;
309 let Inst{17-16} = op;
310 let Inst{25-18} = VDST;
311 let Inst{31-26} = 0x32; // encoding
314 class DSe <bits<8> op> : Enc64 {
324 let Inst{7-0} = offset0;
325 let Inst{15-8} = offset1;
327 let Inst{25-18} = op;
328 let Inst{31-26} = 0x36; //encoding
329 let Inst{39-32} = addr;
330 let Inst{47-40} = data0;
331 let Inst{55-48} = data1;
332 let Inst{63-56} = vdst;
335 class MUBUFe <bits<7> op> : Enc64 {
350 let Inst{11-0} = offset;
351 let Inst{12} = offen;
352 let Inst{13} = idxen;
354 let Inst{15} = addr64;
356 let Inst{24-18} = op;
357 let Inst{31-26} = 0x38; //encoding
358 let Inst{39-32} = vaddr;
359 let Inst{47-40} = vdata;
360 let Inst{52-48} = srsrc{6-2};
363 let Inst{63-56} = soffset;
366 class MTBUFe <bits<3> op> : Enc64 {
382 let Inst{11-0} = OFFSET;
383 let Inst{12} = OFFEN;
384 let Inst{13} = IDXEN;
386 let Inst{15} = ADDR64;
387 let Inst{18-16} = op;
388 let Inst{22-19} = DFMT;
389 let Inst{25-23} = NFMT;
390 let Inst{31-26} = 0x3a; //encoding
391 let Inst{39-32} = VADDR;
392 let Inst{47-40} = VDATA;
393 let Inst{52-48} = SRSRC{6-2};
396 let Inst{63-56} = SOFFSET;
399 class MIMGe <bits<7> op> : Enc64 {
414 let Inst{11-8} = DMASK;
415 let Inst{12} = UNORM;
421 let Inst{24-18} = op;
423 let Inst{31-26} = 0x3c;
424 let Inst{39-32} = VADDR;
425 let Inst{47-40} = VDATA;
426 let Inst{52-48} = SRSRC{6-2};
427 let Inst{57-53} = SSAMP{6-2};
430 class FLATe<bits<7> op> : Enc64 {
441 let Inst{24-18} = op;
442 let Inst{31-26} = 0x37; // Encoding.
443 let Inst{39-32} = addr;
444 let Inst{47-40} = data;
445 // 54-48 is reserved.
447 let Inst{63-56} = vdst;
463 let Inst{10} = COMPR;
466 let Inst{31-26} = 0x3e;
467 let Inst{39-32} = VSRC0;
468 let Inst{47-40} = VSRC1;
469 let Inst{55-48} = VSRC2;
470 let Inst{63-56} = VSRC3;
473 let Uses = [EXEC] in {
475 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
476 InstSI <outs, ins, asm, pattern>, VOP1e<op> {
480 let hasSideEffects = 0;
481 let UseNamedOperandTable = 1;
485 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
486 InstSI <outs, ins, asm, pattern>, VOP2e<op> {
490 let hasSideEffects = 0;
491 let UseNamedOperandTable = 1;
495 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
496 VOP3Common <outs, ins, asm, pattern>, VOP3e<op>;
498 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
499 VOP3Common <outs, ins, asm, pattern>, VOP3be<op>;
501 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
502 InstSI <(outs VCCReg:$dst), ins, asm, pattern>, VOPCe <op> {
504 let DisableEncoding = "$dst";
507 let hasSideEffects = 0;
508 let UseNamedOperandTable = 1;
512 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
513 InstSI <outs, ins, asm, pattern>, VINTRPe<op> {
515 let neverHasSideEffects = 1;
520 } // End Uses = [EXEC]
522 //===----------------------------------------------------------------------===//
523 // Vector I/O operations
524 //===----------------------------------------------------------------------===//
526 let Uses = [EXEC] in {
528 class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
529 InstSI <outs, ins, asm, pattern> , DSe<op> {
532 let UseNamedOperandTable = 1;
535 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
536 InstSI<outs, ins, asm, pattern>, MUBUFe <op> {
542 let neverHasSideEffects = 1;
543 let UseNamedOperandTable = 1;
546 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
547 InstSI<outs, ins, asm, pattern>, MTBUFe <op> {
553 let neverHasSideEffects = 1;
554 let UseNamedOperandTable = 1;
557 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
558 InstSI<outs, ins, asm, pattern>, FLATe <op> {
560 // Internally, FLAT instruction are executed as both an LDS and a
561 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
562 // and are not considered done until both have been decremented.
566 let Uses = [EXEC, FLAT_SCR]; // M0
568 let UseNamedOperandTable = 1;
569 let hasSideEffects = 0;
572 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
573 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
582 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
583 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
584 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
590 } // End Uses = [EXEC]