1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern> {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
21 let TSFlags{0} = VM_CNT;
22 let TSFlags{1} = EXP_CNT;
23 let TSFlags{2} = LGKM_CNT;
26 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
27 InstSI <outs, ins, asm, pattern> {
33 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
34 InstSI <outs, ins, asm, pattern> {
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
44 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
45 Enc32<outs, ins, asm, pattern> {
50 let Inst{7-0} = SSRC0;
52 let Inst{22-16} = SDST;
53 let Inst{31-23} = 0x17d; //encoding;
57 let hasSideEffects = 0;
60 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
61 Enc32 <outs, ins, asm, pattern> {
67 let Inst{7-0} = SSRC0;
68 let Inst{15-8} = SSRC1;
69 let Inst{22-16} = SDST;
71 let Inst{31-30} = 0x2; // encoding
75 let hasSideEffects = 0;
78 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
79 Enc32<outs, ins, asm, pattern> {
84 let Inst{7-0} = SSRC0;
85 let Inst{15-8} = SSRC1;
87 let Inst{31-23} = 0x17e;
89 let DisableEncoding = "$dst";
92 let hasSideEffects = 0;
95 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
96 Enc32 <outs, ins , asm, pattern> {
101 let Inst{15-0} = SIMM16;
102 let Inst{22-16} = SDST;
103 let Inst{27-23} = op;
104 let Inst{31-28} = 0xb; //encoding
108 let hasSideEffects = 0;
111 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
119 let Inst{15-0} = SIMM16;
120 let Inst{22-16} = op;
121 let Inst{31-23} = 0x17f; // encoding
125 let hasSideEffects = 0;
128 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
129 list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
135 let Inst{7-0} = OFFSET;
137 let Inst{14-9} = SBASE{6-1};
138 let Inst{21-15} = SDST;
139 let Inst{26-22} = op;
140 let Inst{31-27} = 0x18; //encoding
145 //===----------------------------------------------------------------------===//
146 // Vector ALU operations
147 //===----------------------------------------------------------------------===//
149 let Uses = [EXEC] in {
151 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
152 Enc32 <outs, ins, asm, pattern> {
157 let Inst{8-0} = SRC0;
159 let Inst{24-17} = VDST;
160 let Inst{31-25} = 0x3f; //encoding
164 let hasSideEffects = 0;
167 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
168 Enc32 <outs, ins, asm, pattern> {
174 let Inst{8-0} = SRC0;
175 let Inst{16-9} = VSRC1;
176 let Inst{24-17} = VDST;
177 let Inst{30-25} = op;
178 let Inst{31} = 0x0; //encoding
182 let hasSideEffects = 0;
185 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
186 Enc64 <outs, ins, asm, pattern> {
197 let Inst{7-0} = VDST;
198 let Inst{10-8} = ABS;
199 let Inst{11} = CLAMP;
200 let Inst{25-17} = op;
201 let Inst{31-26} = 0x34; //encoding
202 let Inst{40-32} = SRC0;
203 let Inst{49-41} = SRC1;
204 let Inst{58-50} = SRC2;
205 let Inst{60-59} = OMOD;
206 let Inst{63-61} = NEG;
210 let hasSideEffects = 0;
213 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
214 Enc64 <outs, ins, asm, pattern> {
224 let Inst{7-0} = VDST;
225 let Inst{14-8} = SDST;
226 let Inst{25-17} = op;
227 let Inst{31-26} = 0x34; //encoding
228 let Inst{40-32} = SRC0;
229 let Inst{49-41} = SRC1;
230 let Inst{58-50} = SRC2;
231 let Inst{60-59} = OMOD;
232 let Inst{63-61} = NEG;
236 let hasSideEffects = 0;
239 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
240 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
245 let Inst{8-0} = SRC0;
246 let Inst{16-9} = VSRC1;
247 let Inst{24-17} = op;
248 let Inst{31-25} = 0x3e;
250 let DisableEncoding = "$dst";
253 let hasSideEffects = 0;
256 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
257 Enc32 <outs, ins, asm, pattern> {
264 let Inst{7-0} = VSRC;
265 let Inst{9-8} = ATTRCHAN;
266 let Inst{15-10} = ATTR;
267 let Inst{17-16} = op;
268 let Inst{25-18} = VDST;
269 let Inst{31-26} = 0x32; // encoding
271 let neverHasSideEffects = 1;
276 } // End Uses = [EXEC]
278 //===----------------------------------------------------------------------===//
279 // Vector I/O operations
280 //===----------------------------------------------------------------------===//
282 let Uses = [EXEC] in {
284 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
285 Enc64<outs, ins, asm, pattern> {
300 let Inst{11-0} = OFFSET;
301 let Inst{12} = OFFEN;
302 let Inst{13} = IDXEN;
304 let Inst{15} = ADDR64;
306 let Inst{24-18} = op;
307 let Inst{31-26} = 0x38; //encoding
308 let Inst{39-32} = VADDR;
309 let Inst{47-40} = VDATA;
310 let Inst{52-48} = SRSRC{6-2};
313 let Inst{63-56} = SOFFSET;
318 let neverHasSideEffects = 1;
321 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
322 Enc64<outs, ins, asm, pattern> {
338 let Inst{11-0} = OFFSET;
339 let Inst{12} = OFFEN;
340 let Inst{13} = IDXEN;
342 let Inst{15} = ADDR64;
343 let Inst{18-16} = op;
344 let Inst{22-19} = DFMT;
345 let Inst{25-23} = NFMT;
346 let Inst{31-26} = 0x3a; //encoding
347 let Inst{39-32} = VADDR;
348 let Inst{47-40} = VDATA;
349 let Inst{52-48} = SRSRC{6-2};
352 let Inst{63-56} = SOFFSET;
357 let neverHasSideEffects = 1;
360 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
361 Enc64 <outs, ins, asm, pattern> {
376 let Inst{11-8} = DMASK;
377 let Inst{12} = UNORM;
383 let Inst{24-18} = op;
385 let Inst{31-26} = 0x3c;
386 let Inst{39-32} = VADDR;
387 let Inst{47-40} = VDATA;
388 let Inst{52-48} = SRSRC{6-2};
389 let Inst{57-53} = SSAMP{6-2};
397 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
398 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
399 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
414 let Inst{10} = COMPR;
417 let Inst{31-26} = 0x3e;
418 let Inst{39-32} = VSRC0;
419 let Inst{47-40} = VSRC1;
420 let Inst{55-48} = VSRC2;
421 let Inst{63-56} = VSRC3;
426 } // End Uses = [EXEC]