1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
21 field bits<1> SALU = 0;
22 field bits<1> VALU = 0;
24 field bits<1> SOP1 = 0;
25 field bits<1> SOP2 = 0;
26 field bits<1> SOPC = 0;
27 field bits<1> SOPK = 0;
28 field bits<1> SOPP = 0;
30 field bits<1> VOP1 = 0;
31 field bits<1> VOP2 = 0;
32 field bits<1> VOP3 = 0;
33 field bits<1> VOPC = 0;
35 field bits<1> MUBUF = 0;
36 field bits<1> MTBUF = 0;
37 field bits<1> SMRD = 0;
39 field bits<1> MIMG = 0;
40 field bits<1> FLAT = 0;
41 field bits<1> WQM = 0;
43 // These need to be kept in sync with the enum in SIInstrFlags.
44 let TSFlags{0} = VM_CNT;
45 let TSFlags{1} = EXP_CNT;
46 let TSFlags{2} = LGKM_CNT;
48 let TSFlags{3} = SALU;
49 let TSFlags{4} = VALU;
51 let TSFlags{5} = SOP1;
52 let TSFlags{6} = SOP2;
53 let TSFlags{7} = SOPC;
54 let TSFlags{8} = SOPK;
55 let TSFlags{9} = SOPP;
57 let TSFlags{10} = VOP1;
58 let TSFlags{11} = VOP2;
59 let TSFlags{12} = VOP3;
60 let TSFlags{13} = VOPC;
62 let TSFlags{14} = MUBUF;
63 let TSFlags{15} = MTBUF;
64 let TSFlags{16} = SMRD;
66 let TSFlags{18} = MIMG;
67 let TSFlags{19} = FLAT;
68 let TSFlags{20} = WQM;
70 // Most instructions require adjustments after selection to satisfy
71 // operand requirements.
72 let hasPostISelHook = 1;
73 let SchedRW = [Write32Bit];
86 class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
87 def VOPDstVCC : VOPDstOperand <VCCReg>;
89 let Uses = [EXEC] in {
91 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
92 InstSI <outs, ins, asm, pattern> {
96 let hasSideEffects = 0;
97 let UseNamedOperandTable = 1;
101 class VOPCCommon <dag ins, string asm, list<dag> pattern> :
102 VOPAnyCommon <(outs VOPDstVCC:$dst), ins, asm, pattern> {
104 let DisableEncoding = "$dst";
109 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
110 VOPAnyCommon <outs, ins, asm, pattern> {
116 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
117 VOPAnyCommon <outs, ins, asm, pattern> {
123 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
124 VOPAnyCommon <outs, ins, asm, pattern> {
126 // Using complex patterns gives VOP3 patterns a very high complexity rating,
127 // but standalone patterns are almost always prefered, so we need to adjust the
128 // priority lower. The goal is to use a high number to reduce complexity to
129 // zero (or less than zero).
130 let AddedComplexity = -1000;
136 } // End Uses = [EXEC]
138 //===----------------------------------------------------------------------===//
140 //===----------------------------------------------------------------------===//
142 class SOP1e <bits<8> op> : Enc32 {
146 let Inst{7-0} = ssrc0;
148 let Inst{22-16} = sdst;
149 let Inst{31-23} = 0x17d; //encoding;
152 class SOP2e <bits<7> op> : Enc32 {
157 let Inst{7-0} = ssrc0;
158 let Inst{15-8} = ssrc1;
159 let Inst{22-16} = sdst;
160 let Inst{29-23} = op;
161 let Inst{31-30} = 0x2; // encoding
164 class SOPCe <bits<7> op> : Enc32 {
168 let Inst{7-0} = ssrc0;
169 let Inst{15-8} = ssrc1;
170 let Inst{22-16} = op;
171 let Inst{31-23} = 0x17e;
174 class SOPKe <bits<5> op> : Enc32 {
178 let Inst{15-0} = simm16;
179 let Inst{22-16} = sdst;
180 let Inst{27-23} = op;
181 let Inst{31-28} = 0xb; //encoding
184 class SOPPe <bits<7> op> : Enc32 {
187 let Inst{15-0} = simm16;
188 let Inst{22-16} = op;
189 let Inst{31-23} = 0x17f; // encoding
192 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
197 let Inst{7-0} = offset;
199 let Inst{14-9} = sbase{6-1};
200 let Inst{21-15} = sdst;
201 let Inst{26-22} = op;
202 let Inst{31-27} = 0x18; //encoding
205 let SchedRW = [WriteSALU] in {
206 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
207 InstSI<outs, ins, asm, pattern> {
210 let hasSideEffects = 0;
215 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
216 InstSI <outs, ins, asm, pattern> {
220 let hasSideEffects = 0;
224 let UseNamedOperandTable = 1;
227 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
228 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
230 let DisableEncoding = "$dst";
233 let hasSideEffects = 0;
237 let UseNamedOperandTable = 1;
240 class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
241 InstSI <outs, ins , asm, pattern> {
245 let hasSideEffects = 0;
249 let UseNamedOperandTable = 1;
252 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
253 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
257 let hasSideEffects = 0;
261 let UseNamedOperandTable = 1;
264 } // let SchedRW = [WriteSALU]
266 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
267 InstSI<outs, ins, asm, pattern> {
273 let hasSideEffects = 0;
274 let UseNamedOperandTable = 1;
275 let SchedRW = [WriteSMEM];
278 //===----------------------------------------------------------------------===//
279 // Vector ALU operations
280 //===----------------------------------------------------------------------===//
282 class VOP1e <bits<8> op> : Enc32 {
286 let Inst{8-0} = src0;
288 let Inst{24-17} = vdst;
289 let Inst{31-25} = 0x3f; //encoding
292 class VOP2e <bits<6> op> : Enc32 {
297 let Inst{8-0} = src0;
298 let Inst{16-9} = src1;
299 let Inst{24-17} = vdst;
300 let Inst{30-25} = op;
301 let Inst{31} = 0x0; //encoding
304 class VOP2_MADKe <bits<6> op> : Enc64 {
311 let Inst{8-0} = src0;
312 let Inst{16-9} = vsrc1;
313 let Inst{24-17} = vdst;
314 let Inst{30-25} = op;
315 let Inst{31} = 0x0; // encoding
316 let Inst{63-32} = src2;
319 class VOP3e <bits<9> op> : Enc64 {
321 bits<2> src0_modifiers;
323 bits<2> src1_modifiers;
325 bits<2> src2_modifiers;
330 let Inst{7-0} = vdst;
331 let Inst{8} = src0_modifiers{1};
332 let Inst{9} = src1_modifiers{1};
333 let Inst{10} = src2_modifiers{1};
334 let Inst{11} = clamp;
335 let Inst{25-17} = op;
336 let Inst{31-26} = 0x34; //encoding
337 let Inst{40-32} = src0;
338 let Inst{49-41} = src1;
339 let Inst{58-50} = src2;
340 let Inst{60-59} = omod;
341 let Inst{61} = src0_modifiers{0};
342 let Inst{62} = src1_modifiers{0};
343 let Inst{63} = src2_modifiers{0};
346 class VOP3be <bits<9> op> : Enc64 {
348 bits<2> src0_modifiers;
350 bits<2> src1_modifiers;
352 bits<2> src2_modifiers;
357 let Inst{7-0} = vdst;
358 let Inst{14-8} = sdst;
359 let Inst{25-17} = op;
360 let Inst{31-26} = 0x34; //encoding
361 let Inst{40-32} = src0;
362 let Inst{49-41} = src1;
363 let Inst{58-50} = src2;
364 let Inst{60-59} = omod;
365 let Inst{61} = src0_modifiers{0};
366 let Inst{62} = src1_modifiers{0};
367 let Inst{63} = src2_modifiers{0};
370 class VOPCe <bits<8> op> : Enc32 {
374 let Inst{8-0} = src0;
375 let Inst{16-9} = vsrc1;
376 let Inst{24-17} = op;
377 let Inst{31-25} = 0x3e;
380 class VINTRPe <bits<2> op> : Enc32 {
386 let Inst{7-0} = vsrc;
387 let Inst{9-8} = attrchan;
388 let Inst{15-10} = attr;
389 let Inst{17-16} = op;
390 let Inst{25-18} = vdst;
391 let Inst{31-26} = 0x32; // encoding
394 class DSe <bits<8> op> : Enc64 {
403 let Inst{7-0} = offset0;
404 let Inst{15-8} = offset1;
406 let Inst{25-18} = op;
407 let Inst{31-26} = 0x36; //encoding
408 let Inst{39-32} = addr;
409 let Inst{47-40} = data0;
410 let Inst{55-48} = data1;
411 let Inst{63-56} = vdst;
414 class MUBUFe <bits<7> op> : Enc64 {
428 let Inst{11-0} = offset;
429 let Inst{12} = offen;
430 let Inst{13} = idxen;
432 let Inst{15} = addr64;
434 let Inst{24-18} = op;
435 let Inst{31-26} = 0x38; //encoding
436 let Inst{39-32} = vaddr;
437 let Inst{47-40} = vdata;
438 let Inst{52-48} = srsrc{6-2};
441 let Inst{63-56} = soffset;
444 class MTBUFe <bits<3> op> : Enc64 {
459 let Inst{11-0} = offset;
460 let Inst{12} = offen;
461 let Inst{13} = idxen;
463 let Inst{15} = addr64;
464 let Inst{18-16} = op;
465 let Inst{22-19} = dfmt;
466 let Inst{25-23} = nfmt;
467 let Inst{31-26} = 0x3a; //encoding
468 let Inst{39-32} = vaddr;
469 let Inst{47-40} = vdata;
470 let Inst{52-48} = srsrc{6-2};
473 let Inst{63-56} = soffset;
476 class MIMGe <bits<7> op> : Enc64 {
490 let Inst{11-8} = dmask;
491 let Inst{12} = unorm;
497 let Inst{24-18} = op;
499 let Inst{31-26} = 0x3c;
500 let Inst{39-32} = vaddr;
501 let Inst{47-40} = vdata;
502 let Inst{52-48} = srsrc{6-2};
503 let Inst{57-53} = ssamp{6-2};
506 class FLATe<bits<7> op> : Enc64 {
517 let Inst{24-18} = op;
518 let Inst{31-26} = 0x37; // Encoding.
519 let Inst{39-32} = addr;
520 let Inst{47-40} = data;
521 // 54-48 is reserved.
523 let Inst{63-56} = vdst;
539 let Inst{10} = compr;
542 let Inst{31-26} = 0x3e;
543 let Inst{39-32} = vsrc0;
544 let Inst{47-40} = vsrc1;
545 let Inst{55-48} = vsrc2;
546 let Inst{63-56} = vsrc3;
549 let Uses = [EXEC] in {
551 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
552 VOP1Common <outs, ins, asm, pattern>,
555 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
556 VOP2Common <outs, ins, asm, pattern>, VOP2e<op>;
558 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
559 VOPCCommon <ins, asm, pattern>, VOPCe <op>;
561 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
562 InstSI <outs, ins, asm, pattern> {
565 let hasSideEffects = 0;
568 } // End Uses = [EXEC]
570 //===----------------------------------------------------------------------===//
571 // Vector I/O operations
572 //===----------------------------------------------------------------------===//
574 let Uses = [EXEC] in {
576 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
577 InstSI <outs, ins, asm, pattern> {
581 let UseNamedOperandTable = 1;
582 let DisableEncoding = "$m0";
584 // Most instruction load and store data, so set this as the default.
588 let hasSideEffects = 0;
589 let SchedRW = [WriteLDS];
592 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
593 InstSI<outs, ins, asm, pattern> {
599 let hasSideEffects = 0;
600 let UseNamedOperandTable = 1;
601 let SchedRW = [WriteVMEM];
604 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
605 InstSI<outs, ins, asm, pattern> {
611 let hasSideEffects = 0;
612 let UseNamedOperandTable = 1;
613 let SchedRW = [WriteVMEM];
616 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
617 InstSI<outs, ins, asm, pattern>, FLATe <op> {
619 // Internally, FLAT instruction are executed as both an LDS and a
620 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
621 // and are not considered done until both have been decremented.
625 let Uses = [EXEC, FLAT_SCR]; // M0
627 let UseNamedOperandTable = 1;
628 let hasSideEffects = 0;
631 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
632 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
638 let hasSideEffects = 0; // XXX ????
642 } // End Uses = [EXEC]