1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
21 field bits<1> SALU = 0;
22 field bits<1> VALU = 0;
24 field bits<1> SOP1 = 0;
25 field bits<1> SOP2 = 0;
26 field bits<1> SOPC = 0;
27 field bits<1> SOPK = 0;
28 field bits<1> SOPP = 0;
30 field bits<1> VOP1 = 0;
31 field bits<1> VOP2 = 0;
32 field bits<1> VOP3 = 0;
33 field bits<1> VOPC = 0;
35 field bits<1> MUBUF = 0;
36 field bits<1> MTBUF = 0;
37 field bits<1> SMRD = 0;
39 field bits<1> MIMG = 0;
40 field bits<1> FLAT = 0;
42 // These need to be kept in sync with the enum in SIInstrFlags.
43 let TSFlags{0} = VM_CNT;
44 let TSFlags{1} = EXP_CNT;
45 let TSFlags{2} = LGKM_CNT;
47 let TSFlags{3} = SALU;
48 let TSFlags{4} = VALU;
50 let TSFlags{5} = SOP1;
51 let TSFlags{6} = SOP2;
52 let TSFlags{7} = SOPC;
53 let TSFlags{8} = SOPK;
54 let TSFlags{9} = SOPP;
56 let TSFlags{10} = VOP1;
57 let TSFlags{11} = VOP2;
58 let TSFlags{12} = VOP3;
59 let TSFlags{13} = VOPC;
61 let TSFlags{14} = MUBUF;
62 let TSFlags{15} = MTBUF;
63 let TSFlags{16} = SMRD;
65 let TSFlags{18} = MIMG;
66 let TSFlags{19} = FLAT;
68 // Most instructions require adjustments after selection to satisfy
69 // operand requirements.
70 let hasPostISelHook = 1;
71 let SchedRW = [Write32Bit];
86 let Uses = [EXEC] in {
88 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
89 InstSI <outs, ins, asm, pattern> {
93 let hasSideEffects = 0;
94 let UseNamedOperandTable = 1;
98 class VOPCCommon <dag ins, string asm, list<dag> pattern> :
99 VOPAnyCommon <(outs VCCReg:$dst), ins, asm, pattern> {
101 let DisableEncoding = "$dst";
106 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
107 VOPAnyCommon <outs, ins, asm, pattern> {
113 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
114 VOPAnyCommon <outs, ins, asm, pattern> {
120 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
121 VOPAnyCommon <outs, ins, asm, pattern> {
123 // Using complex patterns gives VOP3 patterns a very high complexity rating,
124 // but standalone patterns are almost always prefered, so we need to adjust the
125 // priority lower. The goal is to use a high number to reduce complexity to
126 // zero (or less than zero).
127 let AddedComplexity = -1000;
133 } // End Uses = [EXEC]
135 //===----------------------------------------------------------------------===//
137 //===----------------------------------------------------------------------===//
139 class SOP1e <bits<8> op> : Enc32 {
144 let Inst{7-0} = SSRC0;
146 let Inst{22-16} = SDST;
147 let Inst{31-23} = 0x17d; //encoding;
150 class SOP2e <bits<7> op> : Enc32 {
156 let Inst{7-0} = SSRC0;
157 let Inst{15-8} = SSRC1;
158 let Inst{22-16} = SDST;
159 let Inst{29-23} = op;
160 let Inst{31-30} = 0x2; // encoding
163 class SOPCe <bits<7> op> : Enc32 {
168 let Inst{7-0} = SSRC0;
169 let Inst{15-8} = SSRC1;
170 let Inst{22-16} = op;
171 let Inst{31-23} = 0x17e;
174 class SOPKe <bits<5> op> : Enc32 {
179 let Inst{15-0} = SIMM16;
180 let Inst{22-16} = SDST;
181 let Inst{27-23} = op;
182 let Inst{31-28} = 0xb; //encoding
185 class SOPPe <bits<7> op> : Enc32 {
189 let Inst{15-0} = simm16;
190 let Inst{22-16} = op;
191 let Inst{31-23} = 0x17f; // encoding
194 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
200 let Inst{7-0} = OFFSET;
202 let Inst{14-9} = SBASE{6-1};
203 let Inst{21-15} = SDST;
204 let Inst{26-22} = op;
205 let Inst{31-27} = 0x18; //encoding
208 let SchedRW = [WriteSALU] in {
209 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
210 InstSI<outs, ins, asm, pattern> {
213 let hasSideEffects = 0;
218 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
219 InstSI <outs, ins, asm, pattern> {
223 let hasSideEffects = 0;
227 let UseNamedOperandTable = 1;
230 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
231 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
233 let DisableEncoding = "$dst";
236 let hasSideEffects = 0;
240 let UseNamedOperandTable = 1;
243 class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
244 InstSI <outs, ins , asm, pattern> {
248 let hasSideEffects = 0;
252 let UseNamedOperandTable = 1;
255 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
256 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
260 let hasSideEffects = 0;
261 let isCodeGenOnly = 0;
265 let UseNamedOperandTable = 1;
268 } // let SchedRW = [WriteSALU]
270 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
271 InstSI<outs, ins, asm, pattern> {
277 let hasSideEffects = 0;
278 let UseNamedOperandTable = 1;
279 let SchedRW = [WriteSMEM];
282 //===----------------------------------------------------------------------===//
283 // Vector ALU operations
284 //===----------------------------------------------------------------------===//
286 class VOP1e <bits<8> op> : Enc32 {
291 let Inst{8-0} = SRC0;
293 let Inst{24-17} = VDST;
294 let Inst{31-25} = 0x3f; //encoding
297 class VOP2e <bits<6> op> : Enc32 {
303 let Inst{8-0} = SRC0;
304 let Inst{16-9} = VSRC1;
305 let Inst{24-17} = VDST;
306 let Inst{30-25} = op;
307 let Inst{31} = 0x0; //encoding
310 class VOP3e <bits<9> op> : Enc64 {
313 bits<2> src0_modifiers;
315 bits<2> src1_modifiers;
317 bits<2> src2_modifiers;
323 let Inst{8} = src0_modifiers{1};
324 let Inst{9} = src1_modifiers{1};
325 let Inst{10} = src2_modifiers{1};
326 let Inst{11} = clamp;
327 let Inst{25-17} = op;
328 let Inst{31-26} = 0x34; //encoding
329 let Inst{40-32} = src0;
330 let Inst{49-41} = src1;
331 let Inst{58-50} = src2;
332 let Inst{60-59} = omod;
333 let Inst{61} = src0_modifiers{0};
334 let Inst{62} = src1_modifiers{0};
335 let Inst{63} = src2_modifiers{0};
338 class VOP3be <bits<9> op> : Enc64 {
341 bits<2> src0_modifiers;
343 bits<2> src1_modifiers;
345 bits<2> src2_modifiers;
351 let Inst{14-8} = sdst;
352 let Inst{25-17} = op;
353 let Inst{31-26} = 0x34; //encoding
354 let Inst{40-32} = src0;
355 let Inst{49-41} = src1;
356 let Inst{58-50} = src2;
357 let Inst{60-59} = omod;
358 let Inst{61} = src0_modifiers{0};
359 let Inst{62} = src1_modifiers{0};
360 let Inst{63} = src2_modifiers{0};
363 class VOPCe <bits<8> op> : Enc32 {
368 let Inst{8-0} = SRC0;
369 let Inst{16-9} = VSRC1;
370 let Inst{24-17} = op;
371 let Inst{31-25} = 0x3e;
374 class VINTRPe <bits<2> op> : Enc32 {
381 let Inst{7-0} = VSRC;
382 let Inst{9-8} = ATTRCHAN;
383 let Inst{15-10} = ATTR;
384 let Inst{17-16} = op;
385 let Inst{25-18} = VDST;
386 let Inst{31-26} = 0x32; // encoding
389 class DSe <bits<8> op> : Enc64 {
399 let Inst{7-0} = offset0;
400 let Inst{15-8} = offset1;
402 let Inst{25-18} = op;
403 let Inst{31-26} = 0x36; //encoding
404 let Inst{39-32} = addr;
405 let Inst{47-40} = data0;
406 let Inst{55-48} = data1;
407 let Inst{63-56} = vdst;
410 class MUBUFe <bits<7> op> : Enc64 {
425 let Inst{11-0} = offset;
426 let Inst{12} = offen;
427 let Inst{13} = idxen;
429 let Inst{15} = addr64;
431 let Inst{24-18} = op;
432 let Inst{31-26} = 0x38; //encoding
433 let Inst{39-32} = vaddr;
434 let Inst{47-40} = vdata;
435 let Inst{52-48} = srsrc{6-2};
438 let Inst{63-56} = soffset;
441 class MTBUFe <bits<3> op> : Enc64 {
457 let Inst{11-0} = OFFSET;
458 let Inst{12} = OFFEN;
459 let Inst{13} = IDXEN;
461 let Inst{15} = ADDR64;
462 let Inst{18-16} = op;
463 let Inst{22-19} = DFMT;
464 let Inst{25-23} = NFMT;
465 let Inst{31-26} = 0x3a; //encoding
466 let Inst{39-32} = VADDR;
467 let Inst{47-40} = VDATA;
468 let Inst{52-48} = SRSRC{6-2};
471 let Inst{63-56} = SOFFSET;
474 class MIMGe <bits<7> op> : Enc64 {
489 let Inst{11-8} = DMASK;
490 let Inst{12} = UNORM;
496 let Inst{24-18} = op;
498 let Inst{31-26} = 0x3c;
499 let Inst{39-32} = VADDR;
500 let Inst{47-40} = VDATA;
501 let Inst{52-48} = SRSRC{6-2};
502 let Inst{57-53} = SSAMP{6-2};
505 class FLATe<bits<7> op> : Enc64 {
516 let Inst{24-18} = op;
517 let Inst{31-26} = 0x37; // Encoding.
518 let Inst{39-32} = addr;
519 let Inst{47-40} = data;
520 // 54-48 is reserved.
522 let Inst{63-56} = vdst;
538 let Inst{10} = COMPR;
541 let Inst{31-26} = 0x3e;
542 let Inst{39-32} = VSRC0;
543 let Inst{47-40} = VSRC1;
544 let Inst{55-48} = VSRC2;
545 let Inst{63-56} = VSRC3;
548 let Uses = [EXEC] in {
550 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
551 VOP1Common <outs, ins, asm, pattern>,
554 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
555 VOP2Common <outs, ins, asm, pattern>, VOP2e<op>;
557 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
558 VOP3Common <outs, ins, asm, pattern>, VOP3be<op>;
560 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
561 VOPCCommon <ins, asm, pattern>, VOPCe <op>;
563 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
564 InstSI <outs, ins, asm, pattern> {
567 let hasSideEffects = 0;
570 } // End Uses = [EXEC]
572 //===----------------------------------------------------------------------===//
573 // Vector I/O operations
574 //===----------------------------------------------------------------------===//
576 let Uses = [EXEC] in {
578 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
579 InstSI <outs, ins, asm, pattern> {
583 let UseNamedOperandTable = 1;
584 let DisableEncoding = "$m0";
585 let SchedRW = [WriteLDS];
588 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
589 InstSI<outs, ins, asm, pattern> {
595 let hasSideEffects = 0;
596 let UseNamedOperandTable = 1;
597 let SchedRW = [WriteVMEM];
600 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
601 InstSI<outs, ins, asm, pattern> {
607 let hasSideEffects = 0;
608 let UseNamedOperandTable = 1;
609 let SchedRW = [WriteVMEM];
612 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
613 InstSI<outs, ins, asm, pattern>, FLATe <op> {
615 // Internally, FLAT instruction are executed as both an LDS and a
616 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
617 // and are not considered done until both have been decremented.
621 let Uses = [EXEC, FLAT_SCR]; // M0
623 let UseNamedOperandTable = 1;
624 let hasSideEffects = 0;
627 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
628 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
634 let hasSideEffects = 0; // XXX ????
638 } // End Uses = [EXEC]