1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern> {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
20 field bits<1> MIMG = 0;
21 field bits<1> SMRD = 0;
22 field bits<1> VOP1 = 0;
23 field bits<1> VOP2 = 0;
24 field bits<1> VOP3 = 0;
25 field bits<1> VOPC = 0;
27 let TSFlags{0} = VM_CNT;
28 let TSFlags{1} = EXP_CNT;
29 let TSFlags{2} = LGKM_CNT;
30 let TSFlags{3} = MIMG;
31 let TSFlags{4} = SMRD;
32 let TSFlags{5} = VOP1;
33 let TSFlags{6} = VOP2;
34 let TSFlags{7} = VOP3;
35 let TSFlags{8} = VOPC;
38 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
39 InstSI <outs, ins, asm, pattern> {
45 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
46 InstSI <outs, ins, asm, pattern> {
52 //===----------------------------------------------------------------------===//
54 //===----------------------------------------------------------------------===//
56 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
57 Enc32<outs, ins, asm, pattern> {
62 let Inst{7-0} = SSRC0;
64 let Inst{22-16} = SDST;
65 let Inst{31-23} = 0x17d; //encoding;
69 let hasSideEffects = 0;
72 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
73 Enc32 <outs, ins, asm, pattern> {
79 let Inst{7-0} = SSRC0;
80 let Inst{15-8} = SSRC1;
81 let Inst{22-16} = SDST;
83 let Inst{31-30} = 0x2; // encoding
87 let hasSideEffects = 0;
90 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
91 Enc32<outs, ins, asm, pattern> {
96 let Inst{7-0} = SSRC0;
97 let Inst{15-8} = SSRC1;
99 let Inst{31-23} = 0x17e;
101 let DisableEncoding = "$dst";
104 let hasSideEffects = 0;
107 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
108 Enc32 <outs, ins , asm, pattern> {
113 let Inst{15-0} = SIMM16;
114 let Inst{22-16} = SDST;
115 let Inst{27-23} = op;
116 let Inst{31-28} = 0xb; //encoding
120 let hasSideEffects = 0;
123 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
131 let Inst{15-0} = SIMM16;
132 let Inst{22-16} = op;
133 let Inst{31-23} = 0x17f; // encoding
137 let hasSideEffects = 0;
140 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
141 list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
147 let Inst{7-0} = OFFSET;
149 let Inst{14-9} = SBASE{6-1};
150 let Inst{21-15} = SDST;
151 let Inst{26-22} = op;
152 let Inst{31-27} = 0x18; //encoding
158 //===----------------------------------------------------------------------===//
159 // Vector ALU operations
160 //===----------------------------------------------------------------------===//
162 let Uses = [EXEC] in {
164 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
165 Enc32 <outs, ins, asm, pattern> {
170 let Inst{8-0} = SRC0;
172 let Inst{24-17} = VDST;
173 let Inst{31-25} = 0x3f; //encoding
177 let hasSideEffects = 0;
178 let UseNamedOperandTable = 1;
182 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
183 Enc32 <outs, ins, asm, pattern> {
189 let Inst{8-0} = SRC0;
190 let Inst{16-9} = VSRC1;
191 let Inst{24-17} = VDST;
192 let Inst{30-25} = op;
193 let Inst{31} = 0x0; //encoding
197 let hasSideEffects = 0;
198 let UseNamedOperandTable = 1;
202 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
203 Enc64 <outs, ins, asm, pattern> {
215 let Inst{10-8} = abs;
216 let Inst{11} = clamp;
217 let Inst{25-17} = op;
218 let Inst{31-26} = 0x34; //encoding
219 let Inst{40-32} = src0;
220 let Inst{49-41} = src1;
221 let Inst{58-50} = src2;
222 let Inst{60-59} = omod;
223 let Inst{63-61} = neg;
227 let hasSideEffects = 0;
228 let UseNamedOperandTable = 1;
232 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
233 Enc64 <outs, ins, asm, pattern> {
244 let Inst{14-8} = sdst;
245 let Inst{25-17} = op;
246 let Inst{31-26} = 0x34; //encoding
247 let Inst{40-32} = src0;
248 let Inst{49-41} = src1;
249 let Inst{58-50} = src2;
250 let Inst{60-59} = omod;
251 let Inst{63-61} = neg;
255 let hasSideEffects = 0;
256 let UseNamedOperandTable = 1;
260 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
261 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
266 let Inst{8-0} = SRC0;
267 let Inst{16-9} = VSRC1;
268 let Inst{24-17} = op;
269 let Inst{31-25} = 0x3e;
271 let DisableEncoding = "$dst";
274 let hasSideEffects = 0;
278 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
279 Enc32 <outs, ins, asm, pattern> {
286 let Inst{7-0} = VSRC;
287 let Inst{9-8} = ATTRCHAN;
288 let Inst{15-10} = ATTR;
289 let Inst{17-16} = op;
290 let Inst{25-18} = VDST;
291 let Inst{31-26} = 0x32; // encoding
293 let neverHasSideEffects = 1;
298 } // End Uses = [EXEC]
300 //===----------------------------------------------------------------------===//
301 // Vector I/O operations
302 //===----------------------------------------------------------------------===//
304 let Uses = [EXEC] in {
306 class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
307 Enc64 <outs, ins, asm, pattern> {
317 let Inst{7-0} = offset0;
318 let Inst{15-8} = offset1;
320 let Inst{25-18} = op;
321 let Inst{31-26} = 0x36; //encoding
322 let Inst{39-32} = addr;
323 let Inst{47-40} = data0;
324 let Inst{55-48} = data1;
325 let Inst{63-56} = vdst;
330 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
331 Enc64<outs, ins, asm, pattern> {
346 let Inst{11-0} = offset;
347 let Inst{12} = offen;
348 let Inst{13} = idxen;
350 let Inst{15} = addr64;
352 let Inst{24-18} = op;
353 let Inst{31-26} = 0x38; //encoding
354 let Inst{39-32} = vaddr;
355 let Inst{47-40} = vdata;
356 let Inst{52-48} = srsrc{6-2};
359 let Inst{63-56} = soffset;
364 let neverHasSideEffects = 1;
367 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
368 Enc64<outs, ins, asm, pattern> {
384 let Inst{11-0} = OFFSET;
385 let Inst{12} = OFFEN;
386 let Inst{13} = IDXEN;
388 let Inst{15} = ADDR64;
389 let Inst{18-16} = op;
390 let Inst{22-19} = DFMT;
391 let Inst{25-23} = NFMT;
392 let Inst{31-26} = 0x3a; //encoding
393 let Inst{39-32} = VADDR;
394 let Inst{47-40} = VDATA;
395 let Inst{52-48} = SRSRC{6-2};
398 let Inst{63-56} = SOFFSET;
403 let neverHasSideEffects = 1;
406 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
407 Enc64 <outs, ins, asm, pattern> {
422 let Inst{11-8} = DMASK;
423 let Inst{12} = UNORM;
429 let Inst{24-18} = op;
431 let Inst{31-26} = 0x3c;
432 let Inst{39-32} = VADDR;
433 let Inst{47-40} = VDATA;
434 let Inst{52-48} = SRSRC{6-2};
435 let Inst{57-53} = SSAMP{6-2};
444 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
445 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
446 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
461 let Inst{10} = COMPR;
464 let Inst{31-26} = 0x3e;
465 let Inst{39-32} = VSRC0;
466 let Inst{47-40} = VSRC1;
467 let Inst{55-48} = VSRC2;
468 let Inst{63-56} = VSRC3;
473 } // End Uses = [EXEC]