1 //===-- SIInstrFormats.td - SI Instruction Formats ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 // Instructions with _32 take 32-bit operands.
13 // Instructions with _64 take 64-bit operands.
15 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
16 // encoding is the standard encoding, but instruction that make use of
17 // any of the instruction modifiers must use the 64-bit encoding.
19 // Instructions with _e32 use the 32-bit encoding.
20 // Instructions with _e64 use the 64-bit encoding.
22 //===----------------------------------------------------------------------===//
24 class VOP3b_2IN <bits<9> op, string opName, RegisterClass dstClass,
25 RegisterClass src0Class, RegisterClass src1Class,
27 : VOP3b <op, (outs dstClass:$vdst),
28 (ins src0Class:$src0, src1Class:$src1, InstFlag:$src2, InstFlag:$sdst,
29 InstFlag:$omod, InstFlag:$neg),
34 class VOP3_1_32 <bits<9> op, string opName, list<dag> pattern>
35 : VOP3b_2IN <op, opName, SReg_1, AllReg_32, VReg_32, pattern>;
37 class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
38 : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
40 class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
41 : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
44 class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
45 : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
47 class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
48 : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
50 class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
51 : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
53 class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
54 : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
56 class SOP2_VCC <bits<7> op, string opName, list<dag> pattern>
57 : SOP2 <op, (outs SReg_1:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
59 class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
60 string opName, list<dag> pattern> :
62 op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
65 multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
66 def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
67 def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
72 multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
74 def _e32 : VOP1_Helper <op, VReg_64, AllReg_64, opName, pattern>;
77 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
82 class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
83 string opName, list<dag> pattern> :
85 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
88 multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
90 def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
92 def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
97 multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
98 def _e32: VOP2_Helper <op, VReg_64, AllReg_64, opName, pattern>;
101 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
106 class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
107 : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
109 class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
110 : SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
112 class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
113 string opName, list<dag> pattern> :
115 op, (ins arc:$src0, vrc:$src1), opName, pattern
118 multiclass VOPC_32 <bits<9> op, string opName, list<dag> pattern> {
120 def _e32 : VOPC_Helper <
121 {op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
122 VReg_32, AllReg_32, opName, pattern
125 def _e64 : VOP3_1_32 <
131 multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> {
133 def _e32 : VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>;
136 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
141 class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
142 : SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
144 class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
145 : SOPC <op, (outs SCCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;