1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
21 field bits<1> SALU = 0;
22 field bits<1> VALU = 0;
24 field bits<1> SOP1 = 0;
25 field bits<1> SOP2 = 0;
26 field bits<1> SOPC = 0;
27 field bits<1> SOPK = 0;
28 field bits<1> SOPP = 0;
30 field bits<1> VOP1 = 0;
31 field bits<1> VOP2 = 0;
32 field bits<1> VOP3 = 0;
33 field bits<1> VOPC = 0;
35 field bits<1> MUBUF = 0;
36 field bits<1> MTBUF = 0;
37 field bits<1> SMRD = 0;
39 field bits<1> MIMG = 0;
40 field bits<1> FLAT = 0;
41 field bits<1> WQM = 0;
43 // These need to be kept in sync with the enum in SIInstrFlags.
44 let TSFlags{0} = VM_CNT;
45 let TSFlags{1} = EXP_CNT;
46 let TSFlags{2} = LGKM_CNT;
48 let TSFlags{3} = SALU;
49 let TSFlags{4} = VALU;
51 let TSFlags{5} = SOP1;
52 let TSFlags{6} = SOP2;
53 let TSFlags{7} = SOPC;
54 let TSFlags{8} = SOPK;
55 let TSFlags{9} = SOPP;
57 let TSFlags{10} = VOP1;
58 let TSFlags{11} = VOP2;
59 let TSFlags{12} = VOP3;
60 let TSFlags{13} = VOPC;
62 let TSFlags{14} = MUBUF;
63 let TSFlags{15} = MTBUF;
64 let TSFlags{16} = SMRD;
66 let TSFlags{18} = MIMG;
67 let TSFlags{19} = FLAT;
68 let TSFlags{20} = WQM;
70 // Most instructions require adjustments after selection to satisfy
71 // operand requirements.
72 let hasPostISelHook = 1;
73 let SchedRW = [Write32Bit];
86 class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
87 def VOPDstVCC : VOPDstOperand <VCCReg>;
89 let Uses = [EXEC] in {
91 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
92 InstSI <outs, ins, asm, pattern> {
96 let hasSideEffects = 0;
97 let UseNamedOperandTable = 1;
101 class VOPCCommon <dag ins, string asm, list<dag> pattern> :
102 VOPAnyCommon <(outs VOPDstVCC:$dst), ins, asm, pattern> {
104 let DisableEncoding = "$dst";
109 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
110 VOPAnyCommon <outs, ins, asm, pattern> {
116 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
117 VOPAnyCommon <outs, ins, asm, pattern> {
123 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
124 VOPAnyCommon <outs, ins, asm, pattern> {
126 // Using complex patterns gives VOP3 patterns a very high complexity rating,
127 // but standalone patterns are almost always prefered, so we need to adjust the
128 // priority lower. The goal is to use a high number to reduce complexity to
129 // zero (or less than zero).
130 let AddedComplexity = -1000;
135 let AsmMatchConverter = "cvtVOP3";
136 let isCodeGenOnly = 0;
141 } // End Uses = [EXEC]
143 //===----------------------------------------------------------------------===//
145 //===----------------------------------------------------------------------===//
147 class SOP1e <bits<8> op> : Enc32 {
151 let Inst{7-0} = ssrc0;
153 let Inst{22-16} = sdst;
154 let Inst{31-23} = 0x17d; //encoding;
157 class SOP2e <bits<7> op> : Enc32 {
162 let Inst{7-0} = ssrc0;
163 let Inst{15-8} = ssrc1;
164 let Inst{22-16} = sdst;
165 let Inst{29-23} = op;
166 let Inst{31-30} = 0x2; // encoding
169 class SOPCe <bits<7> op> : Enc32 {
173 let Inst{7-0} = ssrc0;
174 let Inst{15-8} = ssrc1;
175 let Inst{22-16} = op;
176 let Inst{31-23} = 0x17e;
179 class SOPKe <bits<5> op> : Enc32 {
183 let Inst{15-0} = simm16;
184 let Inst{22-16} = sdst;
185 let Inst{27-23} = op;
186 let Inst{31-28} = 0xb; //encoding
189 class SOPK64e <bits<5> op> : Enc64 {
194 let Inst{15-0} = simm16;
195 let Inst{22-16} = sdst;
196 let Inst{27-23} = op;
197 let Inst{31-28} = 0xb;
199 let Inst{63-32} = imm;
202 class SOPPe <bits<7> op> : Enc32 {
205 let Inst{15-0} = simm16;
206 let Inst{22-16} = op;
207 let Inst{31-23} = 0x17f; // encoding
210 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
215 let Inst{7-0} = offset;
217 let Inst{14-9} = sbase{6-1};
218 let Inst{21-15} = sdst;
219 let Inst{26-22} = op;
220 let Inst{31-27} = 0x18; //encoding
223 let SchedRW = [WriteSALU] in {
224 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
225 InstSI<outs, ins, asm, pattern> {
228 let hasSideEffects = 0;
229 let isCodeGenOnly = 0;
234 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
235 InstSI <outs, ins, asm, pattern> {
239 let hasSideEffects = 0;
240 let isCodeGenOnly = 0;
244 let UseNamedOperandTable = 1;
247 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
248 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
250 let DisableEncoding = "$dst";
253 let hasSideEffects = 0;
256 let isCodeGenOnly = 0;
258 let UseNamedOperandTable = 1;
261 class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
262 InstSI <outs, ins , asm, pattern> {
266 let hasSideEffects = 0;
270 let UseNamedOperandTable = 1;
273 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
274 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
278 let hasSideEffects = 0;
282 let UseNamedOperandTable = 1;
285 } // let SchedRW = [WriteSALU]
287 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
288 InstSI<outs, ins, asm, pattern> {
294 let hasSideEffects = 0;
295 let UseNamedOperandTable = 1;
296 let SchedRW = [WriteSMEM];
299 //===----------------------------------------------------------------------===//
300 // Vector ALU operations
301 //===----------------------------------------------------------------------===//
303 class VOP1e <bits<8> op> : Enc32 {
307 let Inst{8-0} = src0;
309 let Inst{24-17} = vdst;
310 let Inst{31-25} = 0x3f; //encoding
313 class VOP2e <bits<6> op> : Enc32 {
318 let Inst{8-0} = src0;
319 let Inst{16-9} = src1;
320 let Inst{24-17} = vdst;
321 let Inst{30-25} = op;
322 let Inst{31} = 0x0; //encoding
325 class VOP2_MADKe <bits<6> op> : Enc64 {
332 let Inst{8-0} = src0;
333 let Inst{16-9} = vsrc1;
334 let Inst{24-17} = vdst;
335 let Inst{30-25} = op;
336 let Inst{31} = 0x0; // encoding
337 let Inst{63-32} = src2;
340 class VOP3e <bits<9> op> : Enc64 {
342 bits<2> src0_modifiers;
344 bits<2> src1_modifiers;
346 bits<2> src2_modifiers;
351 let Inst{7-0} = vdst;
352 let Inst{8} = src0_modifiers{1};
353 let Inst{9} = src1_modifiers{1};
354 let Inst{10} = src2_modifiers{1};
355 let Inst{11} = clamp;
356 let Inst{25-17} = op;
357 let Inst{31-26} = 0x34; //encoding
358 let Inst{40-32} = src0;
359 let Inst{49-41} = src1;
360 let Inst{58-50} = src2;
361 let Inst{60-59} = omod;
362 let Inst{61} = src0_modifiers{0};
363 let Inst{62} = src1_modifiers{0};
364 let Inst{63} = src2_modifiers{0};
367 class VOP3be <bits<9> op> : Enc64 {
369 bits<2> src0_modifiers;
371 bits<2> src1_modifiers;
373 bits<2> src2_modifiers;
378 let Inst{7-0} = vdst;
379 let Inst{14-8} = sdst;
380 let Inst{25-17} = op;
381 let Inst{31-26} = 0x34; //encoding
382 let Inst{40-32} = src0;
383 let Inst{49-41} = src1;
384 let Inst{58-50} = src2;
385 let Inst{60-59} = omod;
386 let Inst{61} = src0_modifiers{0};
387 let Inst{62} = src1_modifiers{0};
388 let Inst{63} = src2_modifiers{0};
391 class VOPCe <bits<8> op> : Enc32 {
395 let Inst{8-0} = src0;
396 let Inst{16-9} = vsrc1;
397 let Inst{24-17} = op;
398 let Inst{31-25} = 0x3e;
401 class VINTRPe <bits<2> op> : Enc32 {
407 let Inst{7-0} = vsrc;
408 let Inst{9-8} = attrchan;
409 let Inst{15-10} = attr;
410 let Inst{17-16} = op;
411 let Inst{25-18} = vdst;
412 let Inst{31-26} = 0x32; // encoding
415 class DSe <bits<8> op> : Enc64 {
424 let Inst{7-0} = offset0;
425 let Inst{15-8} = offset1;
427 let Inst{25-18} = op;
428 let Inst{31-26} = 0x36; //encoding
429 let Inst{39-32} = addr;
430 let Inst{47-40} = data0;
431 let Inst{55-48} = data1;
432 let Inst{63-56} = vdst;
435 class MUBUFe <bits<7> op> : Enc64 {
449 let Inst{11-0} = offset;
450 let Inst{12} = offen;
451 let Inst{13} = idxen;
453 let Inst{15} = addr64;
455 let Inst{24-18} = op;
456 let Inst{31-26} = 0x38; //encoding
457 let Inst{39-32} = vaddr;
458 let Inst{47-40} = vdata;
459 let Inst{52-48} = srsrc{6-2};
462 let Inst{63-56} = soffset;
465 class MTBUFe <bits<3> op> : Enc64 {
480 let Inst{11-0} = offset;
481 let Inst{12} = offen;
482 let Inst{13} = idxen;
484 let Inst{15} = addr64;
485 let Inst{18-16} = op;
486 let Inst{22-19} = dfmt;
487 let Inst{25-23} = nfmt;
488 let Inst{31-26} = 0x3a; //encoding
489 let Inst{39-32} = vaddr;
490 let Inst{47-40} = vdata;
491 let Inst{52-48} = srsrc{6-2};
494 let Inst{63-56} = soffset;
497 class MIMGe <bits<7> op> : Enc64 {
511 let Inst{11-8} = dmask;
512 let Inst{12} = unorm;
518 let Inst{24-18} = op;
520 let Inst{31-26} = 0x3c;
521 let Inst{39-32} = vaddr;
522 let Inst{47-40} = vdata;
523 let Inst{52-48} = srsrc{6-2};
524 let Inst{57-53} = ssamp{6-2};
527 class FLATe<bits<7> op> : Enc64 {
538 let Inst{24-18} = op;
539 let Inst{31-26} = 0x37; // Encoding.
540 let Inst{39-32} = addr;
541 let Inst{47-40} = data;
542 // 54-48 is reserved.
544 let Inst{63-56} = vdst;
560 let Inst{10} = compr;
563 let Inst{31-26} = 0x3e;
564 let Inst{39-32} = vsrc0;
565 let Inst{47-40} = vsrc1;
566 let Inst{55-48} = vsrc2;
567 let Inst{63-56} = vsrc3;
570 let Uses = [EXEC] in {
572 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
573 VOP1Common <outs, ins, asm, pattern>,
575 let isCodeGenOnly = 0;
578 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
579 VOP2Common <outs, ins, asm, pattern>, VOP2e<op> {
580 let isCodeGenOnly = 0;
583 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
584 VOPCCommon <ins, asm, pattern>, VOPCe <op>;
586 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
587 InstSI <outs, ins, asm, pattern> {
590 let hasSideEffects = 0;
593 } // End Uses = [EXEC]
595 //===----------------------------------------------------------------------===//
596 // Vector I/O operations
597 //===----------------------------------------------------------------------===//
599 let Uses = [EXEC] in {
601 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
602 InstSI <outs, ins, asm, pattern> {
606 let UseNamedOperandTable = 1;
607 let DisableEncoding = "$m0";
609 // Most instruction load and store data, so set this as the default.
613 let hasSideEffects = 0;
614 let AsmMatchConverter = "cvtDS";
615 let SchedRW = [WriteLDS];
618 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
619 InstSI<outs, ins, asm, pattern> {
625 let hasSideEffects = 0;
626 let UseNamedOperandTable = 1;
627 let AsmMatchConverter = "cvtMubuf";
628 let SchedRW = [WriteVMEM];
631 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
632 InstSI<outs, ins, asm, pattern> {
638 let hasSideEffects = 0;
639 let UseNamedOperandTable = 1;
640 let SchedRW = [WriteVMEM];
643 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
644 InstSI<outs, ins, asm, pattern>, FLATe <op> {
646 // Internally, FLAT instruction are executed as both an LDS and a
647 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
648 // and are not considered done until both have been decremented.
652 let Uses = [EXEC, FLAT_SCR]; // M0
654 let UseNamedOperandTable = 1;
655 let hasSideEffects = 0;
658 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
659 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
665 let hasSideEffects = 0; // XXX ????
669 } // End Uses = [EXEC]