1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern> {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
20 field bits<1> MIMG = 0;
22 let TSFlags{0} = VM_CNT;
23 let TSFlags{1} = EXP_CNT;
24 let TSFlags{2} = LGKM_CNT;
25 let TSFlags{3} = MIMG;
28 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
29 InstSI <outs, ins, asm, pattern> {
35 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
36 InstSI <outs, ins, asm, pattern> {
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
46 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
47 Enc32<outs, ins, asm, pattern> {
52 let Inst{7-0} = SSRC0;
54 let Inst{22-16} = SDST;
55 let Inst{31-23} = 0x17d; //encoding;
59 let hasSideEffects = 0;
62 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
63 Enc32 <outs, ins, asm, pattern> {
69 let Inst{7-0} = SSRC0;
70 let Inst{15-8} = SSRC1;
71 let Inst{22-16} = SDST;
73 let Inst{31-30} = 0x2; // encoding
77 let hasSideEffects = 0;
80 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
81 Enc32<outs, ins, asm, pattern> {
86 let Inst{7-0} = SSRC0;
87 let Inst{15-8} = SSRC1;
89 let Inst{31-23} = 0x17e;
91 let DisableEncoding = "$dst";
94 let hasSideEffects = 0;
97 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
98 Enc32 <outs, ins , asm, pattern> {
103 let Inst{15-0} = SIMM16;
104 let Inst{22-16} = SDST;
105 let Inst{27-23} = op;
106 let Inst{31-28} = 0xb; //encoding
110 let hasSideEffects = 0;
113 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
121 let Inst{15-0} = SIMM16;
122 let Inst{22-16} = op;
123 let Inst{31-23} = 0x17f; // encoding
127 let hasSideEffects = 0;
130 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
131 list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
137 let Inst{7-0} = OFFSET;
139 let Inst{14-9} = SBASE{6-1};
140 let Inst{21-15} = SDST;
141 let Inst{26-22} = op;
142 let Inst{31-27} = 0x18; //encoding
147 //===----------------------------------------------------------------------===//
148 // Vector ALU operations
149 //===----------------------------------------------------------------------===//
151 let Uses = [EXEC] in {
153 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
154 Enc32 <outs, ins, asm, pattern> {
159 let Inst{8-0} = SRC0;
161 let Inst{24-17} = VDST;
162 let Inst{31-25} = 0x3f; //encoding
166 let hasSideEffects = 0;
169 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
170 Enc32 <outs, ins, asm, pattern> {
176 let Inst{8-0} = SRC0;
177 let Inst{16-9} = VSRC1;
178 let Inst{24-17} = VDST;
179 let Inst{30-25} = op;
180 let Inst{31} = 0x0; //encoding
184 let hasSideEffects = 0;
187 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
188 Enc64 <outs, ins, asm, pattern> {
200 let Inst{10-8} = abs;
201 let Inst{11} = clamp;
202 let Inst{25-17} = op;
203 let Inst{31-26} = 0x34; //encoding
204 let Inst{40-32} = src0;
205 let Inst{49-41} = src1;
206 let Inst{58-50} = src2;
207 let Inst{60-59} = omod;
208 let Inst{63-61} = neg;
212 let hasSideEffects = 0;
215 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
216 Enc64 <outs, ins, asm, pattern> {
227 let Inst{14-8} = sdst;
228 let Inst{25-17} = op;
229 let Inst{31-26} = 0x34; //encoding
230 let Inst{40-32} = src0;
231 let Inst{49-41} = src1;
232 let Inst{58-50} = src2;
233 let Inst{60-59} = omod;
234 let Inst{63-61} = neg;
238 let hasSideEffects = 0;
241 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
242 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
247 let Inst{8-0} = SRC0;
248 let Inst{16-9} = VSRC1;
249 let Inst{24-17} = op;
250 let Inst{31-25} = 0x3e;
252 let DisableEncoding = "$dst";
255 let hasSideEffects = 0;
258 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
259 Enc32 <outs, ins, asm, pattern> {
266 let Inst{7-0} = VSRC;
267 let Inst{9-8} = ATTRCHAN;
268 let Inst{15-10} = ATTR;
269 let Inst{17-16} = op;
270 let Inst{25-18} = VDST;
271 let Inst{31-26} = 0x32; // encoding
273 let neverHasSideEffects = 1;
278 } // End Uses = [EXEC]
280 //===----------------------------------------------------------------------===//
281 // Vector I/O operations
282 //===----------------------------------------------------------------------===//
284 let Uses = [EXEC] in {
286 class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
287 Enc64 <outs, ins, asm, pattern> {
297 let Inst{7-0} = offset0;
298 let Inst{15-8} = offset1;
300 let Inst{25-18} = op;
301 let Inst{31-26} = 0x36; //encoding
302 let Inst{39-32} = addr;
303 let Inst{47-40} = data0;
304 let Inst{55-48} = data1;
305 let Inst{63-56} = vdst;
310 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
311 Enc64<outs, ins, asm, pattern> {
326 let Inst{11-0} = offset;
327 let Inst{12} = offen;
328 let Inst{13} = idxen;
330 let Inst{15} = addr64;
332 let Inst{24-18} = op;
333 let Inst{31-26} = 0x38; //encoding
334 let Inst{39-32} = vaddr;
335 let Inst{47-40} = vdata;
336 let Inst{52-48} = srsrc{6-2};
339 let Inst{63-56} = soffset;
344 let neverHasSideEffects = 1;
347 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
348 Enc64<outs, ins, asm, pattern> {
364 let Inst{11-0} = OFFSET;
365 let Inst{12} = OFFEN;
366 let Inst{13} = IDXEN;
368 let Inst{15} = ADDR64;
369 let Inst{18-16} = op;
370 let Inst{22-19} = DFMT;
371 let Inst{25-23} = NFMT;
372 let Inst{31-26} = 0x3a; //encoding
373 let Inst{39-32} = VADDR;
374 let Inst{47-40} = VDATA;
375 let Inst{52-48} = SRSRC{6-2};
378 let Inst{63-56} = SOFFSET;
383 let neverHasSideEffects = 1;
386 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
387 Enc64 <outs, ins, asm, pattern> {
402 let Inst{11-8} = DMASK;
403 let Inst{12} = UNORM;
409 let Inst{24-18} = op;
411 let Inst{31-26} = 0x3c;
412 let Inst{39-32} = VADDR;
413 let Inst{47-40} = VDATA;
414 let Inst{52-48} = SRSRC{6-2};
415 let Inst{57-53} = SSAMP{6-2};
424 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
425 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
426 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
441 let Inst{10} = COMPR;
444 let Inst{31-26} = 0x3e;
445 let Inst{39-32} = VSRC0;
446 let Inst{47-40} = VSRC1;
447 let Inst{55-48} = VSRC2;
448 let Inst{63-56} = VSRC3;
453 } // End Uses = [EXEC]