1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
20 field bits<1> MIMG = 0;
21 field bits<1> SMRD = 0;
22 field bits<1> VOP1 = 0;
23 field bits<1> VOP2 = 0;
24 field bits<1> VOP3 = 0;
25 field bits<1> VOPC = 0;
26 field bits<1> SALU = 0;
27 field bits<1> MUBUF = 0;
28 field bits<1> MTBUF = 0;
30 // These need to be kept in sync with the enum in SIInstrFlags.
31 let TSFlags{0} = VM_CNT;
32 let TSFlags{1} = EXP_CNT;
33 let TSFlags{2} = LGKM_CNT;
34 let TSFlags{3} = MIMG;
35 let TSFlags{4} = SMRD;
36 let TSFlags{5} = VOP1;
37 let TSFlags{6} = VOP2;
38 let TSFlags{7} = VOP3;
39 let TSFlags{8} = VOPC;
40 let TSFlags{9} = SALU;
41 let TSFlags{10} = MUBUF;
42 let TSFlags{11} = MTBUF;
57 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
58 InstSI <outs, ins, asm, pattern> {
62 let hasSideEffects = 0;
63 let UseNamedOperandTable = 1;
64 // Using complex patterns gives VOP3 patterns a very high complexity rating,
65 // but standalone patterns are almost always prefered, so we need to adjust the
66 // priority lower. The goal is to use a high number to reduce complexity to
67 // zero (or less than zero).
68 let AddedComplexity = -1000;
76 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
80 class SOP1e <bits<8> op> : Enc32 {
85 let Inst{7-0} = SSRC0;
87 let Inst{22-16} = SDST;
88 let Inst{31-23} = 0x17d; //encoding;
91 class SOP2e <bits<7> op> : Enc32 {
97 let Inst{7-0} = SSRC0;
98 let Inst{15-8} = SSRC1;
99 let Inst{22-16} = SDST;
100 let Inst{29-23} = op;
101 let Inst{31-30} = 0x2; // encoding
104 class SOPCe <bits<7> op> : Enc32 {
109 let Inst{7-0} = SSRC0;
110 let Inst{15-8} = SSRC1;
111 let Inst{22-16} = op;
112 let Inst{31-23} = 0x17e;
115 class SOPKe <bits<5> op> : Enc32 {
120 let Inst{15-0} = SIMM16;
121 let Inst{22-16} = SDST;
122 let Inst{27-23} = op;
123 let Inst{31-28} = 0xb; //encoding
126 class SOPPe <bits<7> op> : Enc32 {
130 let Inst{15-0} = simm16;
131 let Inst{22-16} = op;
132 let Inst{31-23} = 0x17f; // encoding
135 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
141 let Inst{7-0} = OFFSET;
143 let Inst{14-9} = SBASE{6-1};
144 let Inst{21-15} = SDST;
145 let Inst{26-22} = op;
146 let Inst{31-27} = 0x18; //encoding
149 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
150 InstSI<outs, ins, asm, pattern>, SOP1e <op> {
154 let hasSideEffects = 0;
158 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
159 InstSI <outs, ins, asm, pattern>, SOP2e<op> {
163 let hasSideEffects = 0;
167 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
168 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
170 let DisableEncoding = "$dst";
173 let hasSideEffects = 0;
177 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
178 InstSI <outs, ins , asm, pattern>, SOPKe<op> {
182 let hasSideEffects = 0;
186 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
187 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
191 let hasSideEffects = 0;
195 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
196 list<dag> pattern> : InstSI<outs, ins, asm, pattern>, SMRDe<op, imm> {
202 let UseNamedOperandTable = 1;
205 //===----------------------------------------------------------------------===//
206 // Vector ALU operations
207 //===----------------------------------------------------------------------===//
209 class VOP1e <bits<8> op> : Enc32 {
214 let Inst{8-0} = SRC0;
216 let Inst{24-17} = VDST;
217 let Inst{31-25} = 0x3f; //encoding
220 class VOP2e <bits<6> op> : Enc32 {
226 let Inst{8-0} = SRC0;
227 let Inst{16-9} = VSRC1;
228 let Inst{24-17} = VDST;
229 let Inst{30-25} = op;
230 let Inst{31} = 0x0; //encoding
233 class VOP3e <bits<9> op> : Enc64 {
236 bits<2> src0_modifiers;
238 bits<2> src1_modifiers;
240 bits<2> src2_modifiers;
246 let Inst{8} = src0_modifiers{1};
247 let Inst{9} = src1_modifiers{1};
248 let Inst{10} = src2_modifiers{1};
249 let Inst{11} = clamp;
250 let Inst{25-17} = op;
251 let Inst{31-26} = 0x34; //encoding
252 let Inst{40-32} = src0;
253 let Inst{49-41} = src1;
254 let Inst{58-50} = src2;
255 let Inst{60-59} = omod;
256 let Inst{61} = src0_modifiers{0};
257 let Inst{62} = src1_modifiers{0};
258 let Inst{63} = src2_modifiers{0};
261 class VOP3be <bits<9> op> : Enc64 {
264 bits<2> src0_modifiers;
266 bits<2> src1_modifiers;
268 bits<2> src2_modifiers;
274 let Inst{14-8} = sdst;
275 let Inst{25-17} = op;
276 let Inst{31-26} = 0x34; //encoding
277 let Inst{40-32} = src0;
278 let Inst{49-41} = src1;
279 let Inst{58-50} = src2;
280 let Inst{60-59} = omod;
281 let Inst{61} = src0_modifiers{0};
282 let Inst{62} = src1_modifiers{0};
283 let Inst{63} = src2_modifiers{0};
286 class VOPCe <bits<8> op> : Enc32 {
291 let Inst{8-0} = SRC0;
292 let Inst{16-9} = VSRC1;
293 let Inst{24-17} = op;
294 let Inst{31-25} = 0x3e;
297 class VINTRPe <bits<2> op> : Enc32 {
304 let Inst{7-0} = VSRC;
305 let Inst{9-8} = ATTRCHAN;
306 let Inst{15-10} = ATTR;
307 let Inst{17-16} = op;
308 let Inst{25-18} = VDST;
309 let Inst{31-26} = 0x32; // encoding
312 class DSe <bits<8> op> : Enc64 {
322 let Inst{7-0} = offset0;
323 let Inst{15-8} = offset1;
325 let Inst{25-18} = op;
326 let Inst{31-26} = 0x36; //encoding
327 let Inst{39-32} = addr;
328 let Inst{47-40} = data0;
329 let Inst{55-48} = data1;
330 let Inst{63-56} = vdst;
333 class MUBUFe <bits<7> op> : Enc64 {
348 let Inst{11-0} = offset;
349 let Inst{12} = offen;
350 let Inst{13} = idxen;
352 let Inst{15} = addr64;
354 let Inst{24-18} = op;
355 let Inst{31-26} = 0x38; //encoding
356 let Inst{39-32} = vaddr;
357 let Inst{47-40} = vdata;
358 let Inst{52-48} = srsrc{6-2};
361 let Inst{63-56} = soffset;
364 class MTBUFe <bits<3> op> : Enc64 {
380 let Inst{11-0} = OFFSET;
381 let Inst{12} = OFFEN;
382 let Inst{13} = IDXEN;
384 let Inst{15} = ADDR64;
385 let Inst{18-16} = op;
386 let Inst{22-19} = DFMT;
387 let Inst{25-23} = NFMT;
388 let Inst{31-26} = 0x3a; //encoding
389 let Inst{39-32} = VADDR;
390 let Inst{47-40} = VDATA;
391 let Inst{52-48} = SRSRC{6-2};
394 let Inst{63-56} = SOFFSET;
397 class MIMGe <bits<7> op> : Enc64 {
412 let Inst{11-8} = DMASK;
413 let Inst{12} = UNORM;
419 let Inst{24-18} = op;
421 let Inst{31-26} = 0x3c;
422 let Inst{39-32} = VADDR;
423 let Inst{47-40} = VDATA;
424 let Inst{52-48} = SRSRC{6-2};
425 let Inst{57-53} = SSAMP{6-2};
442 let Inst{10} = COMPR;
445 let Inst{31-26} = 0x3e;
446 let Inst{39-32} = VSRC0;
447 let Inst{47-40} = VSRC1;
448 let Inst{55-48} = VSRC2;
449 let Inst{63-56} = VSRC3;
452 let Uses = [EXEC] in {
454 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
455 InstSI <outs, ins, asm, pattern>, VOP1e<op> {
459 let hasSideEffects = 0;
460 let UseNamedOperandTable = 1;
464 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
465 InstSI <outs, ins, asm, pattern>, VOP2e<op> {
469 let hasSideEffects = 0;
470 let UseNamedOperandTable = 1;
474 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
475 VOP3Common <outs, ins, asm, pattern>, VOP3e<op>;
477 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
478 VOP3Common <outs, ins, asm, pattern>, VOP3be<op>;
480 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
481 InstSI <(outs VCCReg:$dst), ins, asm, pattern>, VOPCe <op> {
483 let DisableEncoding = "$dst";
486 let hasSideEffects = 0;
487 let UseNamedOperandTable = 1;
491 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
492 InstSI <outs, ins, asm, pattern>, VINTRPe<op> {
494 let neverHasSideEffects = 1;
499 } // End Uses = [EXEC]
501 //===----------------------------------------------------------------------===//
502 // Vector I/O operations
503 //===----------------------------------------------------------------------===//
505 let Uses = [EXEC] in {
507 class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
508 InstSI <outs, ins, asm, pattern> , DSe<op> {
511 let UseNamedOperandTable = 1;
514 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
515 InstSI<outs, ins, asm, pattern>, MUBUFe <op> {
521 let neverHasSideEffects = 1;
522 let UseNamedOperandTable = 1;
525 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
526 InstSI<outs, ins, asm, pattern>, MTBUFe <op> {
532 let neverHasSideEffects = 1;
535 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
536 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
545 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
546 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
547 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
553 } // End Uses = [EXEC]