1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
20 field bits<1> MIMG = 0;
21 field bits<1> SMRD = 0;
22 field bits<1> VOP1 = 0;
23 field bits<1> VOP2 = 0;
24 field bits<1> VOP3 = 0;
25 field bits<1> VOPC = 0;
26 field bits<1> SALU = 0;
27 field bits<1> MUBUF = 0;
28 field bits<1> MTBUF = 0;
29 field bits<1> FLAT = 0;
31 // These need to be kept in sync with the enum in SIInstrFlags.
32 let TSFlags{0} = VM_CNT;
33 let TSFlags{1} = EXP_CNT;
34 let TSFlags{2} = LGKM_CNT;
35 let TSFlags{3} = MIMG;
36 let TSFlags{4} = SMRD;
37 let TSFlags{5} = VOP1;
38 let TSFlags{6} = VOP2;
39 let TSFlags{7} = VOP3;
40 let TSFlags{8} = VOPC;
41 let TSFlags{9} = SALU;
42 let TSFlags{10} = MUBUF;
43 let TSFlags{11} = MTBUF;
44 let TSFlags{12} = FLAT;
46 // Most instructions require adjustments after selection to satisfy
47 // operand requirements.
48 let hasPostISelHook = 1;
63 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
64 InstSI <outs, ins, asm, pattern> {
68 let hasSideEffects = 0;
69 let UseNamedOperandTable = 1;
70 // Using complex patterns gives VOP3 patterns a very high complexity rating,
71 // but standalone patterns are almost always prefered, so we need to adjust the
72 // priority lower. The goal is to use a high number to reduce complexity to
73 // zero (or less than zero).
74 let AddedComplexity = -1000;
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 class SOP1e <bits<8> op> : Enc32 {
91 let Inst{7-0} = SSRC0;
93 let Inst{22-16} = SDST;
94 let Inst{31-23} = 0x17d; //encoding;
97 class SOP2e <bits<7> op> : Enc32 {
103 let Inst{7-0} = SSRC0;
104 let Inst{15-8} = SSRC1;
105 let Inst{22-16} = SDST;
106 let Inst{29-23} = op;
107 let Inst{31-30} = 0x2; // encoding
110 class SOPCe <bits<7> op> : Enc32 {
115 let Inst{7-0} = SSRC0;
116 let Inst{15-8} = SSRC1;
117 let Inst{22-16} = op;
118 let Inst{31-23} = 0x17e;
121 class SOPKe <bits<5> op> : Enc32 {
126 let Inst{15-0} = SIMM16;
127 let Inst{22-16} = SDST;
128 let Inst{27-23} = op;
129 let Inst{31-28} = 0xb; //encoding
132 class SOPPe <bits<7> op> : Enc32 {
136 let Inst{15-0} = simm16;
137 let Inst{22-16} = op;
138 let Inst{31-23} = 0x17f; // encoding
141 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
147 let Inst{7-0} = OFFSET;
149 let Inst{14-9} = SBASE{6-1};
150 let Inst{21-15} = SDST;
151 let Inst{26-22} = op;
152 let Inst{31-27} = 0x18; //encoding
155 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
156 InstSI<outs, ins, asm, pattern>, SOP1e <op> {
160 let hasSideEffects = 0;
164 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
165 InstSI <outs, ins, asm, pattern>, SOP2e<op> {
169 let hasSideEffects = 0;
172 let UseNamedOperandTable = 1;
175 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
176 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
178 let DisableEncoding = "$dst";
181 let hasSideEffects = 0;
184 let UseNamedOperandTable = 1;
187 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
188 InstSI <outs, ins , asm, pattern>, SOPKe<op> {
192 let hasSideEffects = 0;
195 let UseNamedOperandTable = 1;
198 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
199 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
203 let hasSideEffects = 0;
206 let UseNamedOperandTable = 1;
209 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
210 InstSI<outs, ins, asm, pattern> {
216 let UseNamedOperandTable = 1;
219 //===----------------------------------------------------------------------===//
220 // Vector ALU operations
221 //===----------------------------------------------------------------------===//
223 class VOP1e <bits<8> op> : Enc32 {
228 let Inst{8-0} = SRC0;
230 let Inst{24-17} = VDST;
231 let Inst{31-25} = 0x3f; //encoding
234 class VOP2e <bits<6> op> : Enc32 {
240 let Inst{8-0} = SRC0;
241 let Inst{16-9} = VSRC1;
242 let Inst{24-17} = VDST;
243 let Inst{30-25} = op;
244 let Inst{31} = 0x0; //encoding
247 class VOP3e <bits<9> op> : Enc64 {
250 bits<2> src0_modifiers;
252 bits<2> src1_modifiers;
254 bits<2> src2_modifiers;
260 let Inst{8} = src0_modifiers{1};
261 let Inst{9} = src1_modifiers{1};
262 let Inst{10} = src2_modifiers{1};
263 let Inst{11} = clamp;
264 let Inst{25-17} = op;
265 let Inst{31-26} = 0x34; //encoding
266 let Inst{40-32} = src0;
267 let Inst{49-41} = src1;
268 let Inst{58-50} = src2;
269 let Inst{60-59} = omod;
270 let Inst{61} = src0_modifiers{0};
271 let Inst{62} = src1_modifiers{0};
272 let Inst{63} = src2_modifiers{0};
275 class VOP3be <bits<9> op> : Enc64 {
278 bits<2> src0_modifiers;
280 bits<2> src1_modifiers;
282 bits<2> src2_modifiers;
288 let Inst{14-8} = sdst;
289 let Inst{25-17} = op;
290 let Inst{31-26} = 0x34; //encoding
291 let Inst{40-32} = src0;
292 let Inst{49-41} = src1;
293 let Inst{58-50} = src2;
294 let Inst{60-59} = omod;
295 let Inst{61} = src0_modifiers{0};
296 let Inst{62} = src1_modifiers{0};
297 let Inst{63} = src2_modifiers{0};
300 class VOPCe <bits<8> op> : Enc32 {
305 let Inst{8-0} = SRC0;
306 let Inst{16-9} = VSRC1;
307 let Inst{24-17} = op;
308 let Inst{31-25} = 0x3e;
311 class VINTRPe <bits<2> op> : Enc32 {
318 let Inst{7-0} = VSRC;
319 let Inst{9-8} = ATTRCHAN;
320 let Inst{15-10} = ATTR;
321 let Inst{17-16} = op;
322 let Inst{25-18} = VDST;
323 let Inst{31-26} = 0x32; // encoding
326 class DSe <bits<8> op> : Enc64 {
336 let Inst{7-0} = offset0;
337 let Inst{15-8} = offset1;
339 let Inst{25-18} = op;
340 let Inst{31-26} = 0x36; //encoding
341 let Inst{39-32} = addr;
342 let Inst{47-40} = data0;
343 let Inst{55-48} = data1;
344 let Inst{63-56} = vdst;
347 class MUBUFe <bits<7> op> : Enc64 {
362 let Inst{11-0} = offset;
363 let Inst{12} = offen;
364 let Inst{13} = idxen;
366 let Inst{15} = addr64;
368 let Inst{24-18} = op;
369 let Inst{31-26} = 0x38; //encoding
370 let Inst{39-32} = vaddr;
371 let Inst{47-40} = vdata;
372 let Inst{52-48} = srsrc{6-2};
375 let Inst{63-56} = soffset;
378 class MTBUFe <bits<3> op> : Enc64 {
394 let Inst{11-0} = OFFSET;
395 let Inst{12} = OFFEN;
396 let Inst{13} = IDXEN;
398 let Inst{15} = ADDR64;
399 let Inst{18-16} = op;
400 let Inst{22-19} = DFMT;
401 let Inst{25-23} = NFMT;
402 let Inst{31-26} = 0x3a; //encoding
403 let Inst{39-32} = VADDR;
404 let Inst{47-40} = VDATA;
405 let Inst{52-48} = SRSRC{6-2};
408 let Inst{63-56} = SOFFSET;
411 class MIMGe <bits<7> op> : Enc64 {
426 let Inst{11-8} = DMASK;
427 let Inst{12} = UNORM;
433 let Inst{24-18} = op;
435 let Inst{31-26} = 0x3c;
436 let Inst{39-32} = VADDR;
437 let Inst{47-40} = VDATA;
438 let Inst{52-48} = SRSRC{6-2};
439 let Inst{57-53} = SSAMP{6-2};
442 class FLATe<bits<7> op> : Enc64 {
453 let Inst{24-18} = op;
454 let Inst{31-26} = 0x37; // Encoding.
455 let Inst{39-32} = addr;
456 let Inst{47-40} = data;
457 // 54-48 is reserved.
459 let Inst{63-56} = vdst;
475 let Inst{10} = COMPR;
478 let Inst{31-26} = 0x3e;
479 let Inst{39-32} = VSRC0;
480 let Inst{47-40} = VSRC1;
481 let Inst{55-48} = VSRC2;
482 let Inst{63-56} = VSRC3;
485 let Uses = [EXEC] in {
487 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
488 InstSI <outs, ins, asm, pattern>, VOP1e<op> {
492 let hasSideEffects = 0;
493 let UseNamedOperandTable = 1;
497 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
498 InstSI <outs, ins, asm, pattern>, VOP2e<op> {
502 let hasSideEffects = 0;
503 let UseNamedOperandTable = 1;
507 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
508 VOP3Common <outs, ins, asm, pattern>, VOP3e<op>;
510 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
511 VOP3Common <outs, ins, asm, pattern>, VOP3be<op>;
513 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
514 InstSI <(outs VCCReg:$dst), ins, asm, pattern>, VOPCe <op> {
516 let DisableEncoding = "$dst";
519 let hasSideEffects = 0;
520 let UseNamedOperandTable = 1;
524 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
525 InstSI <outs, ins, asm, pattern>, VINTRPe<op> {
527 let neverHasSideEffects = 1;
532 } // End Uses = [EXEC]
534 //===----------------------------------------------------------------------===//
535 // Vector I/O operations
536 //===----------------------------------------------------------------------===//
538 let Uses = [EXEC] in {
540 class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
541 InstSI <outs, ins, asm, pattern> , DSe<op> {
544 let UseNamedOperandTable = 1;
547 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
548 InstSI<outs, ins, asm, pattern>, MUBUFe <op> {
554 let neverHasSideEffects = 1;
555 let UseNamedOperandTable = 1;
558 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
559 InstSI<outs, ins, asm, pattern> {
565 let neverHasSideEffects = 1;
566 let UseNamedOperandTable = 1;
569 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
570 InstSI<outs, ins, asm, pattern>, FLATe <op> {
572 // Internally, FLAT instruction are executed as both an LDS and a
573 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
574 // and are not considered done until both have been decremented.
578 let Uses = [EXEC, FLAT_SCR]; // M0
580 let UseNamedOperandTable = 1;
581 let hasSideEffects = 0;
584 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
585 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
594 } // End Uses = [EXEC]