1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCInstrDesc.h"
27 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
28 : AMDGPUInstrInfo(st),
31 //===----------------------------------------------------------------------===//
32 // TargetInstrInfo callbacks
33 //===----------------------------------------------------------------------===//
35 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
36 unsigned &BaseReg, unsigned &Offset,
37 const TargetRegisterInfo *TRI) const {
38 unsigned Opc = LdSt->getOpcode();
40 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
41 AMDGPU::OpName::offset);
43 // Normal, single offset LDS instruction.
44 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
45 AMDGPU::OpName::addr);
47 BaseReg = AddrReg->getReg();
48 Offset = OffsetImm->getImm();
52 // The 2 offset instructions use offset0 and offset1 instead. We can treat
53 // these as a load with a single offset if the 2 offsets are consecutive. We
54 // will use this for some partially aligned loads.
55 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
56 AMDGPU::OpName::offset0);
57 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
58 AMDGPU::OpName::offset1);
60 uint8_t Offset0 = Offset0Imm->getImm();
61 uint8_t Offset1 = Offset1Imm->getImm();
62 assert(Offset1 > Offset0);
64 if (Offset1 - Offset0 == 1) {
65 // Each of these offsets is in element sized units, so we need to convert
66 // to bytes of the individual reads.
70 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
72 assert(LdSt->mayStore());
73 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
74 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
77 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
78 AMDGPU::OpName::addr);
79 BaseReg = AddrReg->getReg();
80 Offset = EltSize * Offset0;
87 if (isMUBUF(Opc) || isMTBUF(Opc)) {
88 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
91 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
92 AMDGPU::OpName::vaddr);
96 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
97 AMDGPU::OpName::offset);
98 BaseReg = AddrReg->getReg();
99 Offset = OffsetImm->getImm();
104 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
105 AMDGPU::OpName::offset);
109 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
110 AMDGPU::OpName::sbase);
111 BaseReg = SBaseReg->getReg();
112 Offset = OffsetImm->getImm();
120 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MI, DebugLoc DL,
122 unsigned DestReg, unsigned SrcReg,
123 bool KillSrc) const {
125 // If we are trying to copy to or from SCC, there is a bug somewhere else in
126 // the backend. While it may be theoretically possible to do this, it should
127 // never be necessary.
128 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
130 static const int16_t Sub0_15[] = {
131 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
132 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
133 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
134 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
137 static const int16_t Sub0_7[] = {
138 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
139 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
142 static const int16_t Sub0_3[] = {
143 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
146 static const int16_t Sub0_2[] = {
147 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
150 static const int16_t Sub0_1[] = {
151 AMDGPU::sub0, AMDGPU::sub1, 0
155 const int16_t *SubIndices;
157 if (AMDGPU::M0 == DestReg) {
158 // Check if M0 isn't already set to this value
159 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
160 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
162 if (!I->definesRegister(AMDGPU::M0))
165 unsigned Opc = I->getOpcode();
166 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
169 if (!I->readsRegister(SrcReg))
172 // The copy isn't necessary
177 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
178 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
179 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
180 .addReg(SrcReg, getKillRegState(KillSrc));
183 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
184 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
185 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
186 .addReg(SrcReg, getKillRegState(KillSrc));
189 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
190 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
191 Opcode = AMDGPU::S_MOV_B32;
194 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
195 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
196 Opcode = AMDGPU::S_MOV_B32;
199 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
200 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
201 Opcode = AMDGPU::S_MOV_B32;
202 SubIndices = Sub0_15;
204 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
205 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
206 AMDGPU::SReg_32RegClass.contains(SrcReg));
207 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
208 .addReg(SrcReg, getKillRegState(KillSrc));
211 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
212 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
213 AMDGPU::SReg_64RegClass.contains(SrcReg));
214 Opcode = AMDGPU::V_MOV_B32_e32;
217 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
218 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
219 Opcode = AMDGPU::V_MOV_B32_e32;
222 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
223 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
224 AMDGPU::SReg_128RegClass.contains(SrcReg));
225 Opcode = AMDGPU::V_MOV_B32_e32;
228 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
229 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
230 AMDGPU::SReg_256RegClass.contains(SrcReg));
231 Opcode = AMDGPU::V_MOV_B32_e32;
234 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
235 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
236 AMDGPU::SReg_512RegClass.contains(SrcReg));
237 Opcode = AMDGPU::V_MOV_B32_e32;
238 SubIndices = Sub0_15;
241 llvm_unreachable("Can't copy register!");
244 while (unsigned SubIdx = *SubIndices++) {
245 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
246 get(Opcode), RI.getSubReg(DestReg, SubIdx));
248 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
251 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
255 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
258 // Try to map original to commuted opcode
259 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
262 // Try to map commuted to original opcode
263 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
269 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
270 MachineBasicBlock::iterator MI,
271 unsigned SrcReg, bool isKill,
273 const TargetRegisterClass *RC,
274 const TargetRegisterInfo *TRI) const {
275 MachineFunction *MF = MBB.getParent();
276 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
277 MachineRegisterInfo &MRI = MF->getRegInfo();
278 DebugLoc DL = MBB.findDebugLoc(MI);
279 unsigned KillFlag = isKill ? RegState::Kill : 0;
281 if (RI.hasVGPRs(RC)) {
282 LLVMContext &Ctx = MF->getFunction()->getContext();
283 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
284 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
286 } else if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
287 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF);
288 unsigned TgtReg = MFI->SpillTracker.LaneVGPR;
290 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), TgtReg)
291 .addReg(SrcReg, KillFlag)
293 MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg, Lane);
294 } else if (RI.isSGPRClass(RC)) {
295 // We are only allowed to create one new instruction when spilling
296 // registers, so we need to use pseudo instruction for vector
299 // Reserve a spot in the spill tracker for each sub-register of
300 // the vector register.
301 unsigned NumSubRegs = RC->getSize() / 4;
302 unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MF, NumSubRegs);
303 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
307 switch (RC->getSize() * 8) {
308 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
309 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
310 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
311 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
312 default: llvm_unreachable("Cannot spill register class");
315 BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
319 llvm_unreachable("VGPR spilling not supported");
323 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
324 MachineBasicBlock::iterator MI,
325 unsigned DestReg, int FrameIndex,
326 const TargetRegisterClass *RC,
327 const TargetRegisterInfo *TRI) const {
328 MachineFunction *MF = MBB.getParent();
329 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
330 DebugLoc DL = MBB.findDebugLoc(MI);
332 if (RI.hasVGPRs(RC)) {
333 LLVMContext &Ctx = MF->getFunction()->getContext();
334 Ctx.emitError("SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!");
335 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
337 } else if (RI.isSGPRClass(RC)){
339 switch(RC->getSize() * 8) {
340 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
341 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
342 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
343 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
344 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
345 default: llvm_unreachable("Cannot spill register class");
348 SIMachineFunctionInfo::SpilledReg Spill =
349 MFI->SpillTracker.getSpilledReg(FrameIndex);
351 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
355 llvm_unreachable("VGPR spilling not supported");
359 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
362 case AMDGPU::SI_SPILL_S512_SAVE:
363 case AMDGPU::SI_SPILL_S512_RESTORE:
365 case AMDGPU::SI_SPILL_S256_SAVE:
366 case AMDGPU::SI_SPILL_S256_RESTORE:
368 case AMDGPU::SI_SPILL_S128_SAVE:
369 case AMDGPU::SI_SPILL_S128_RESTORE:
371 case AMDGPU::SI_SPILL_S64_SAVE:
372 case AMDGPU::SI_SPILL_S64_RESTORE:
374 case AMDGPU::SI_SPILL_S32_RESTORE:
376 default: llvm_unreachable("Invalid spill opcode");
380 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
389 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
394 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
395 SIMachineFunctionInfo *MFI =
396 MI->getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
397 MachineBasicBlock &MBB = *MI->getParent();
398 DebugLoc DL = MBB.findDebugLoc(MI);
399 switch (MI->getOpcode()) {
400 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
402 // SGPR register spill
403 case AMDGPU::SI_SPILL_S512_SAVE:
404 case AMDGPU::SI_SPILL_S256_SAVE:
405 case AMDGPU::SI_SPILL_S128_SAVE:
406 case AMDGPU::SI_SPILL_S64_SAVE: {
407 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
408 unsigned FrameIndex = MI->getOperand(2).getImm();
410 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
411 SIMachineFunctionInfo::SpilledReg Spill;
412 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
413 &AMDGPU::SGPR_32RegClass, i);
414 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
416 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
417 MI->getOperand(0).getReg())
419 .addImm(Spill.Lane + i);
421 MI->eraseFromParent();
425 // SGPR register restore
426 case AMDGPU::SI_SPILL_S512_RESTORE:
427 case AMDGPU::SI_SPILL_S256_RESTORE:
428 case AMDGPU::SI_SPILL_S128_RESTORE:
429 case AMDGPU::SI_SPILL_S64_RESTORE:
430 case AMDGPU::SI_SPILL_S32_RESTORE: {
431 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
433 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
434 SIMachineFunctionInfo::SpilledReg Spill;
435 unsigned FrameIndex = MI->getOperand(2).getImm();
436 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
437 &AMDGPU::SGPR_32RegClass, i);
438 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
440 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
441 .addReg(MI->getOperand(1).getReg())
442 .addImm(Spill.Lane + i);
445 MI->eraseFromParent();
448 case AMDGPU::SI_CONSTDATA_PTR: {
449 unsigned Reg = MI->getOperand(0).getReg();
450 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
451 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
453 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
455 // Add 32-bit offset from this instruction to the start of the constant data.
456 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_I32), RegLo)
458 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
459 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
460 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
463 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
464 .addReg(AMDGPU::SCC, RegState::Implicit);
465 MI->eraseFromParent();
472 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
475 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
478 // Make sure it s legal to commute operands for VOP2.
479 if (isVOP2(MI->getOpcode()) &&
480 (!isOperandLegal(MI, 1, &MI->getOperand(2)) ||
481 !isOperandLegal(MI, 2, &MI->getOperand(1))))
484 if (!MI->getOperand(2).isReg()) {
485 // XXX: Commute instructions with FPImm operands
486 if (NewMI || MI->getOperand(2).isFPImm() ||
487 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
491 // XXX: Commute VOP3 instructions with abs and neg set.
492 if (isVOP3(MI->getOpcode()) &&
493 (MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
494 AMDGPU::OpName::abs)).getImm() ||
495 MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
496 AMDGPU::OpName::neg)).getImm()))
499 unsigned Reg = MI->getOperand(1).getReg();
500 unsigned SubReg = MI->getOperand(1).getSubReg();
501 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
502 MI->getOperand(2).ChangeToRegister(Reg, false);
503 MI->getOperand(2).setSubReg(SubReg);
505 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
509 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
514 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
515 MachineBasicBlock::iterator I,
517 unsigned SrcReg) const {
518 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
519 DstReg) .addReg(SrcReg);
522 bool SIInstrInfo::isMov(unsigned Opcode) const {
524 default: return false;
525 case AMDGPU::S_MOV_B32:
526 case AMDGPU::S_MOV_B64:
527 case AMDGPU::V_MOV_B32_e32:
528 case AMDGPU::V_MOV_B32_e64:
534 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
535 return RC != &AMDGPU::EXECRegRegClass;
539 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
540 AliasAnalysis *AA) const {
541 switch(MI->getOpcode()) {
542 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
543 case AMDGPU::S_MOV_B32:
544 case AMDGPU::S_MOV_B64:
545 case AMDGPU::V_MOV_B32_e32:
546 return MI->getOperand(1).isImm();
552 // Helper function generated by tablegen. We are wrapping this with
553 // an SIInstrInfo function that returns bool rather than int.
554 int isDS(uint16_t Opcode);
558 bool SIInstrInfo::isDS(uint16_t Opcode) const {
559 return ::AMDGPU::isDS(Opcode) != -1;
562 bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
563 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
566 bool SIInstrInfo::isSMRD(uint16_t Opcode) const {
567 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
570 bool SIInstrInfo::isMUBUF(uint16_t Opcode) const {
571 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
574 bool SIInstrInfo::isMTBUF(uint16_t Opcode) const {
575 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
578 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
579 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
582 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
583 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
586 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
587 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
590 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
591 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
594 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
595 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
598 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
599 int32_t Val = Imm.getSExtValue();
600 if (Val >= -16 && Val <= 64)
603 // The actual type of the operand does not seem to matter as long
604 // as the bits match one of the inline immediate values. For example:
606 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
607 // so it is a legal inline immediate.
609 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
610 // floating-point, so it is a legal inline immediate.
612 return (APInt::floatToBits(0.0f) == Imm) ||
613 (APInt::floatToBits(1.0f) == Imm) ||
614 (APInt::floatToBits(-1.0f) == Imm) ||
615 (APInt::floatToBits(0.5f) == Imm) ||
616 (APInt::floatToBits(-0.5f) == Imm) ||
617 (APInt::floatToBits(2.0f) == Imm) ||
618 (APInt::floatToBits(-2.0f) == Imm) ||
619 (APInt::floatToBits(4.0f) == Imm) ||
620 (APInt::floatToBits(-4.0f) == Imm);
623 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
625 return isInlineConstant(APInt(32, MO.getImm(), true));
628 APFloat FpImm = MO.getFPImm()->getValueAPF();
629 return isInlineConstant(FpImm.bitcastToAPInt());
635 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
636 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
639 static bool compareMachineOp(const MachineOperand &Op0,
640 const MachineOperand &Op1) {
641 if (Op0.getType() != Op1.getType())
644 switch (Op0.getType()) {
645 case MachineOperand::MO_Register:
646 return Op0.getReg() == Op1.getReg();
647 case MachineOperand::MO_Immediate:
648 return Op0.getImm() == Op1.getImm();
649 case MachineOperand::MO_FPImmediate:
650 return Op0.getFPImm() == Op1.getFPImm();
652 llvm_unreachable("Didn't expect to be comparing these operand types");
656 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
657 const MachineOperand &MO) const {
658 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
660 assert(MO.isImm() || MO.isFPImm());
662 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
665 if (OpInfo.RegClass < 0)
668 return RI.regClassCanUseImmediate(OpInfo.RegClass);
671 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
672 return AMDGPU::getVOPe32(Opcode) != -1;
675 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
676 StringRef &ErrInfo) const {
677 uint16_t Opcode = MI->getOpcode();
678 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
679 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
680 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
682 // Make sure the number of operands is correct.
683 const MCInstrDesc &Desc = get(Opcode);
684 if (!Desc.isVariadic() &&
685 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
686 ErrInfo = "Instruction has wrong number of operands.";
690 // Make sure the register classes are correct
691 for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
692 switch (Desc.OpInfo[i].OperandType) {
693 case MCOI::OPERAND_REGISTER: {
694 int RegClass = Desc.OpInfo[i].RegClass;
695 if (!RI.regClassCanUseImmediate(RegClass) &&
696 (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) {
697 ErrInfo = "Expected register, but got immediate";
702 case MCOI::OPERAND_IMMEDIATE:
703 // Check if this operand is an immediate.
704 // FrameIndex operands will be replaced by immediates, so they are
706 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
707 !MI->getOperand(i).isFI()) {
708 ErrInfo = "Expected immediate, but got non-immediate";
716 if (!MI->getOperand(i).isReg())
719 int RegClass = Desc.OpInfo[i].RegClass;
720 if (RegClass != -1) {
721 unsigned Reg = MI->getOperand(i).getReg();
722 if (TargetRegisterInfo::isVirtualRegister(Reg))
725 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
726 if (!RC->contains(Reg)) {
727 ErrInfo = "Operand has incorrect register class.";
735 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
736 unsigned ConstantBusCount = 0;
737 unsigned SGPRUsed = AMDGPU::NoRegister;
738 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
739 const MachineOperand &MO = MI->getOperand(i);
740 if (MO.isReg() && MO.isUse() &&
741 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
743 // EXEC register uses the constant bus.
744 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
747 // SGPRs use the constant bus
748 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
750 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
751 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
752 if (SGPRUsed != MO.getReg()) {
754 SGPRUsed = MO.getReg();
758 // Literal constants use the constant bus.
759 if (isLiteralConstant(MO))
762 if (ConstantBusCount > 1) {
763 ErrInfo = "VOP* instruction uses the constant bus more than once";
768 // Verify SRC1 for VOP2 and VOPC
769 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
770 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
771 if (Src1.isImm() || Src1.isFPImm()) {
772 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
778 if (isVOP3(Opcode)) {
779 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
780 ErrInfo = "VOP3 src0 cannot be a literal constant.";
783 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
784 ErrInfo = "VOP3 src1 cannot be a literal constant.";
787 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
788 ErrInfo = "VOP3 src2 cannot be a literal constant.";
793 // Verify misc. restrictions on specific instructions.
794 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
795 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
798 const MachineOperand &Src0 = MI->getOperand(2);
799 const MachineOperand &Src1 = MI->getOperand(3);
800 const MachineOperand &Src2 = MI->getOperand(4);
801 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
802 if (!compareMachineOp(Src0, Src1) &&
803 !compareMachineOp(Src0, Src2)) {
804 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
813 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
814 switch (MI.getOpcode()) {
815 default: return AMDGPU::INSTRUCTION_LIST_END;
816 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
817 case AMDGPU::COPY: return AMDGPU::COPY;
818 case AMDGPU::PHI: return AMDGPU::PHI;
819 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
820 case AMDGPU::S_MOV_B32:
821 return MI.getOperand(1).isReg() ?
822 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
823 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
824 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
825 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
826 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
827 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
828 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
829 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
830 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
831 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
832 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
833 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
834 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
835 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
836 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
837 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
838 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
839 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
840 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
841 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
842 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
843 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
844 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
845 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
846 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
847 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
848 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
849 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
850 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
851 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
852 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
853 case AMDGPU::S_LOAD_DWORD_IMM:
854 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
855 case AMDGPU::S_LOAD_DWORDX2_IMM:
856 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
857 case AMDGPU::S_LOAD_DWORDX4_IMM:
858 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
859 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
860 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
861 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
865 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
866 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
869 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
870 unsigned OpNo) const {
871 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
872 const MCInstrDesc &Desc = get(MI.getOpcode());
873 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
874 Desc.OpInfo[OpNo].RegClass == -1)
875 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
877 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
878 return RI.getRegClass(RCID);
881 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
882 switch (MI.getOpcode()) {
884 case AMDGPU::REG_SEQUENCE:
886 case AMDGPU::INSERT_SUBREG:
887 return RI.hasVGPRs(getOpRegClass(MI, 0));
889 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
893 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
894 MachineBasicBlock::iterator I = MI;
895 MachineOperand &MO = MI->getOperand(OpIdx);
896 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
897 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
898 const TargetRegisterClass *RC = RI.getRegClass(RCID);
899 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
901 Opcode = AMDGPU::COPY;
902 } else if (RI.isSGPRClass(RC)) {
903 Opcode = AMDGPU::S_MOV_B32;
906 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
907 unsigned Reg = MRI.createVirtualRegister(VRC);
908 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
910 MO.ChangeToRegister(Reg, false);
913 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
914 MachineRegisterInfo &MRI,
915 MachineOperand &SuperReg,
916 const TargetRegisterClass *SuperRC,
918 const TargetRegisterClass *SubRC)
920 assert(SuperReg.isReg());
922 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
923 unsigned SubReg = MRI.createVirtualRegister(SubRC);
925 // Just in case the super register is itself a sub-register, copy it to a new
926 // value so we don't need to worry about merging its subreg index with the
927 // SubIdx passed to this function. The register coalescer should be able to
928 // eliminate this extra copy.
929 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
931 .addOperand(SuperReg);
933 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
935 .addReg(NewSuperReg, 0, SubIdx);
939 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
940 MachineBasicBlock::iterator MII,
941 MachineRegisterInfo &MRI,
943 const TargetRegisterClass *SuperRC,
945 const TargetRegisterClass *SubRC) const {
947 // XXX - Is there a better way to do this?
948 if (SubIdx == AMDGPU::sub0)
949 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
950 if (SubIdx == AMDGPU::sub1)
951 return MachineOperand::CreateImm(Op.getImm() >> 32);
953 llvm_unreachable("Unhandled register index for immediate");
956 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
958 return MachineOperand::CreateReg(SubReg, false);
961 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
962 MachineBasicBlock::iterator MI,
963 MachineRegisterInfo &MRI,
964 const TargetRegisterClass *RC,
965 const MachineOperand &Op) const {
966 MachineBasicBlock *MBB = MI->getParent();
967 DebugLoc DL = MI->getDebugLoc();
968 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
969 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
970 unsigned Dst = MRI.createVirtualRegister(RC);
972 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
974 .addImm(Op.getImm() & 0xFFFFFFFF);
975 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
977 .addImm(Op.getImm() >> 32);
979 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
981 .addImm(AMDGPU::sub0)
983 .addImm(AMDGPU::sub1);
985 Worklist.push_back(Lo);
986 Worklist.push_back(Hi);
991 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
992 const MachineOperand *MO) const {
993 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
994 const MCInstrDesc &InstDesc = get(MI->getOpcode());
995 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
996 const TargetRegisterClass *DefinedRC =
997 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
999 MO = &MI->getOperand(OpIdx);
1003 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1004 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass));
1008 // Handle non-register types that are treated like immediates.
1009 assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI());
1012 // This opperand expects an immediate
1015 return RI.regClassCanUseImmediate(DefinedRC);
1018 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1019 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1021 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1022 AMDGPU::OpName::src0);
1023 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1024 AMDGPU::OpName::src1);
1025 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1026 AMDGPU::OpName::src2);
1029 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1031 if (!isOperandLegal(MI, Src0Idx))
1032 legalizeOpWithMove(MI, Src0Idx);
1035 if (isOperandLegal(MI, Src1Idx))
1038 // Usually src0 of VOP2 instructions allow more types of inputs
1039 // than src1, so try to commute the instruction to decrease our
1040 // chances of having to insert a MOV instruction to legalize src1.
1041 if (MI->isCommutable()) {
1042 if (commuteInstruction(MI))
1043 // If we are successful in commuting, then we know MI is legal, so
1048 legalizeOpWithMove(MI, Src1Idx);
1052 // XXX - Do any VOP3 instructions read VCC?
1054 if (isVOP3(MI->getOpcode())) {
1055 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
1056 unsigned SGPRReg = AMDGPU::NoRegister;
1057 for (unsigned i = 0; i < 3; ++i) {
1058 int Idx = VOP3Idx[i];
1061 MachineOperand &MO = MI->getOperand(Idx);
1064 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1065 continue; // VGPRs are legal
1067 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1069 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1070 SGPRReg = MO.getReg();
1071 // We can use one SGPR in each VOP3 instruction.
1074 } else if (!isLiteralConstant(MO)) {
1075 // If it is not a register and not a literal constant, then it must be
1076 // an inline constant which is always legal.
1079 // If we make it this far, then the operand is not legal and we must
1081 legalizeOpWithMove(MI, Idx);
1085 // Legalize REG_SEQUENCE and PHI
1086 // The register class of the operands much be the same type as the register
1087 // class of the output.
1088 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1089 MI->getOpcode() == AMDGPU::PHI) {
1090 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1091 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1092 if (!MI->getOperand(i).isReg() ||
1093 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1095 const TargetRegisterClass *OpRC =
1096 MRI.getRegClass(MI->getOperand(i).getReg());
1097 if (RI.hasVGPRs(OpRC)) {
1104 // If any of the operands are VGPR registers, then they all most be
1105 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1107 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1110 VRC = RI.getEquivalentVGPRClass(SRC);
1117 // Update all the operands so they have the same type.
1118 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1119 if (!MI->getOperand(i).isReg() ||
1120 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1122 unsigned DstReg = MRI.createVirtualRegister(RC);
1123 MachineBasicBlock *InsertBB;
1124 MachineBasicBlock::iterator Insert;
1125 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1126 InsertBB = MI->getParent();
1129 // MI is a PHI instruction.
1130 InsertBB = MI->getOperand(i + 1).getMBB();
1131 Insert = InsertBB->getFirstTerminator();
1133 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1134 get(AMDGPU::COPY), DstReg)
1135 .addOperand(MI->getOperand(i));
1136 MI->getOperand(i).setReg(DstReg);
1140 // Legalize INSERT_SUBREG
1141 // src0 must have the same register class as dst
1142 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1143 unsigned Dst = MI->getOperand(0).getReg();
1144 unsigned Src0 = MI->getOperand(1).getReg();
1145 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1146 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1147 if (DstRC != Src0RC) {
1148 MachineBasicBlock &MBB = *MI->getParent();
1149 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1150 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1152 MI->getOperand(1).setReg(NewSrc0);
1157 // Legalize MUBUF* instructions
1158 // FIXME: If we start using the non-addr64 instructions for compute, we
1159 // may need to legalize them here.
1161 int SRsrcIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1162 AMDGPU::OpName::srsrc);
1163 int VAddrIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1164 AMDGPU::OpName::vaddr);
1165 if (SRsrcIdx != -1 && VAddrIdx != -1) {
1166 const TargetRegisterClass *VAddrRC =
1167 RI.getRegClass(get(MI->getOpcode()).OpInfo[VAddrIdx].RegClass);
1169 if(VAddrRC->getSize() == 8 &&
1170 MRI.getRegClass(MI->getOperand(SRsrcIdx).getReg()) != VAddrRC) {
1171 // We have a MUBUF instruction that uses a 64-bit vaddr register and
1172 // srsrc has the incorrect register class. In order to fix this, we
1173 // need to extract the pointer from the resource descriptor (srsrc),
1174 // add it to the value of vadd, then store the result in the vaddr
1175 // operand. Then, we need to set the pointer field of the resource
1176 // descriptor to zero.
1178 MachineBasicBlock &MBB = *MI->getParent();
1179 MachineOperand &SRsrcOp = MI->getOperand(SRsrcIdx);
1180 MachineOperand &VAddrOp = MI->getOperand(VAddrIdx);
1181 unsigned SRsrcPtrLo, SRsrcPtrHi, VAddrLo, VAddrHi;
1182 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1183 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1184 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1185 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1186 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1187 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1188 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1190 // SRsrcPtrLo = srsrc:sub0
1191 SRsrcPtrLo = buildExtractSubReg(MI, MRI, SRsrcOp,
1192 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1194 // SRsrcPtrHi = srsrc:sub1
1195 SRsrcPtrHi = buildExtractSubReg(MI, MRI, SRsrcOp,
1196 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1198 // VAddrLo = vaddr:sub0
1199 VAddrLo = buildExtractSubReg(MI, MRI, VAddrOp,
1200 &AMDGPU::VReg_64RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1202 // VAddrHi = vaddr:sub1
1203 VAddrHi = buildExtractSubReg(MI, MRI, VAddrOp,
1204 &AMDGPU::VReg_64RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1206 // NewVaddrLo = SRsrcPtrLo + VAddrLo
1207 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1211 .addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
1213 // NewVaddrHi = SRsrcPtrHi + VAddrHi
1214 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1218 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1219 .addReg(AMDGPU::VCC, RegState::Implicit);
1221 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1222 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1225 .addImm(AMDGPU::sub0)
1227 .addImm(AMDGPU::sub1);
1230 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1234 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1235 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1237 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1239 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1240 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1242 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1244 // NewSRsrc = {Zero64, SRsrcFormat}
1245 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1248 .addImm(AMDGPU::sub0_sub1)
1249 .addReg(SRsrcFormatLo)
1250 .addImm(AMDGPU::sub2)
1251 .addReg(SRsrcFormatHi)
1252 .addImm(AMDGPU::sub3);
1254 // Update the instruction to use NewVaddr
1255 MI->getOperand(VAddrIdx).setReg(NewVAddr);
1256 // Update the instruction to use NewSRsrc
1257 MI->getOperand(SRsrcIdx).setReg(NewSRsrc);
1262 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1263 MachineBasicBlock *MBB = MI->getParent();
1264 switch (MI->getOpcode()) {
1265 case AMDGPU::S_LOAD_DWORD_IMM:
1266 case AMDGPU::S_LOAD_DWORD_SGPR:
1267 case AMDGPU::S_LOAD_DWORDX2_IMM:
1268 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1269 case AMDGPU::S_LOAD_DWORDX4_IMM:
1270 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1271 unsigned NewOpcode = getVALUOp(*MI);
1275 if (MI->getOperand(2).isReg()) {
1276 RegOffset = MI->getOperand(2).getReg();
1279 assert(MI->getOperand(2).isImm());
1280 // SMRD instructions take a dword offsets and MUBUF instructions
1281 // take a byte offset.
1282 ImmOffset = MI->getOperand(2).getImm() << 2;
1283 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1284 if (isUInt<12>(ImmOffset)) {
1285 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1289 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1296 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1297 unsigned DWord0 = RegOffset;
1298 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1299 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1300 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1302 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1304 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1305 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1306 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1307 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1308 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1310 .addImm(AMDGPU::sub0)
1312 .addImm(AMDGPU::sub1)
1314 .addImm(AMDGPU::sub2)
1316 .addImm(AMDGPU::sub3);
1317 MI->setDesc(get(NewOpcode));
1318 if (MI->getOperand(2).isReg()) {
1319 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1321 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1323 MI->getOperand(1).setReg(SRsrc);
1324 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1328 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1329 SmallVector<MachineInstr *, 128> Worklist;
1330 Worklist.push_back(&TopInst);
1332 while (!Worklist.empty()) {
1333 MachineInstr *Inst = Worklist.pop_back_val();
1334 MachineBasicBlock *MBB = Inst->getParent();
1335 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1337 unsigned Opcode = Inst->getOpcode();
1338 unsigned NewOpcode = getVALUOp(*Inst);
1340 // Handle some special cases
1343 if (isSMRD(Inst->getOpcode())) {
1344 moveSMRDToVALU(Inst, MRI);
1347 case AMDGPU::S_MOV_B64: {
1348 DebugLoc DL = Inst->getDebugLoc();
1350 // If the source operand is a register we can replace this with a
1352 if (Inst->getOperand(1).isReg()) {
1353 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1354 .addOperand(Inst->getOperand(0))
1355 .addOperand(Inst->getOperand(1));
1356 Worklist.push_back(Copy);
1358 // Otherwise, we need to split this into two movs, because there is
1359 // no 64-bit VALU move instruction.
1360 unsigned Reg = Inst->getOperand(0).getReg();
1361 unsigned Dst = split64BitImm(Worklist,
1364 MRI.getRegClass(Reg),
1365 Inst->getOperand(1));
1366 MRI.replaceRegWith(Reg, Dst);
1368 Inst->eraseFromParent();
1371 case AMDGPU::S_AND_B64:
1372 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1373 Inst->eraseFromParent();
1376 case AMDGPU::S_OR_B64:
1377 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1378 Inst->eraseFromParent();
1381 case AMDGPU::S_XOR_B64:
1382 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1383 Inst->eraseFromParent();
1386 case AMDGPU::S_NOT_B64:
1387 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1388 Inst->eraseFromParent();
1391 case AMDGPU::S_BCNT1_I32_B64:
1392 splitScalar64BitBCNT(Worklist, Inst);
1393 Inst->eraseFromParent();
1396 case AMDGPU::S_BFE_U64:
1397 case AMDGPU::S_BFE_I64:
1398 case AMDGPU::S_BFM_B64:
1399 llvm_unreachable("Moving this op to VALU not implemented");
1402 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1403 // We cannot move this instruction to the VALU, so we should try to
1404 // legalize its operands instead.
1405 legalizeOperands(Inst);
1409 // Use the new VALU Opcode.
1410 const MCInstrDesc &NewDesc = get(NewOpcode);
1411 Inst->setDesc(NewDesc);
1413 // Remove any references to SCC. Vector instructions can't read from it, and
1414 // We're just about to add the implicit use / defs of VCC, and we don't want
1416 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1417 MachineOperand &Op = Inst->getOperand(i);
1418 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1419 Inst->RemoveOperand(i);
1422 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1423 // We are converting these to a BFE, so we need to add the missing
1424 // operands for the size and offset.
1425 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1426 Inst->addOperand(Inst->getOperand(1));
1427 Inst->getOperand(1).ChangeToImmediate(0);
1428 Inst->addOperand(MachineOperand::CreateImm(0));
1429 Inst->addOperand(MachineOperand::CreateImm(0));
1430 Inst->addOperand(MachineOperand::CreateImm(0));
1431 Inst->addOperand(MachineOperand::CreateImm(Size));
1433 // XXX - Other pointless operands. There are 4, but it seems you only need
1434 // 3 to not hit an assertion later in MCInstLower.
1435 Inst->addOperand(MachineOperand::CreateImm(0));
1436 Inst->addOperand(MachineOperand::CreateImm(0));
1437 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1438 // The VALU version adds the second operand to the result, so insert an
1440 Inst->addOperand(MachineOperand::CreateImm(0));
1443 addDescImplicitUseDef(NewDesc, Inst);
1445 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1446 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1447 // If we need to move this to VGPRs, we need to unpack the second operand
1448 // back into the 2 separate ones for bit offset and width.
1449 assert(OffsetWidthOp.isImm() &&
1450 "Scalar BFE is only implemented for constant width and offset");
1451 uint32_t Imm = OffsetWidthOp.getImm();
1453 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1454 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1456 Inst->RemoveOperand(2); // Remove old immediate.
1457 Inst->addOperand(Inst->getOperand(1));
1458 Inst->getOperand(1).ChangeToImmediate(0);
1459 Inst->addOperand(MachineOperand::CreateImm(0));
1460 Inst->addOperand(MachineOperand::CreateImm(Offset));
1461 Inst->addOperand(MachineOperand::CreateImm(0));
1462 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1463 Inst->addOperand(MachineOperand::CreateImm(0));
1464 Inst->addOperand(MachineOperand::CreateImm(0));
1467 // Update the destination register class.
1469 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1472 // For target instructions, getOpRegClass just returns the virtual
1473 // register class associated with the operand, so we need to find an
1474 // equivalent VGPR register class in order to move the instruction to the
1478 case AMDGPU::REG_SEQUENCE:
1479 case AMDGPU::INSERT_SUBREG:
1480 if (RI.hasVGPRs(NewDstRC))
1482 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1490 unsigned DstReg = Inst->getOperand(0).getReg();
1491 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1492 MRI.replaceRegWith(DstReg, NewDstReg);
1494 // Legalize the operands
1495 legalizeOperands(Inst);
1497 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1498 E = MRI.use_end(); I != E; ++I) {
1499 MachineInstr &UseMI = *I->getParent();
1500 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1501 Worklist.push_back(&UseMI);
1507 //===----------------------------------------------------------------------===//
1508 // Indirect addressing callbacks
1509 //===----------------------------------------------------------------------===//
1511 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1512 unsigned Channel) const {
1513 assert(Channel == 0);
1517 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1518 return &AMDGPU::VReg_32RegClass;
1521 void SIInstrInfo::splitScalar64BitUnaryOp(
1522 SmallVectorImpl<MachineInstr *> &Worklist,
1524 unsigned Opcode) const {
1525 MachineBasicBlock &MBB = *Inst->getParent();
1526 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1528 MachineOperand &Dest = Inst->getOperand(0);
1529 MachineOperand &Src0 = Inst->getOperand(1);
1530 DebugLoc DL = Inst->getDebugLoc();
1532 MachineBasicBlock::iterator MII = Inst;
1534 const MCInstrDesc &InstDesc = get(Opcode);
1535 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1536 MRI.getRegClass(Src0.getReg()) :
1537 &AMDGPU::SGPR_32RegClass;
1539 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1541 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1542 AMDGPU::sub0, Src0SubRC);
1544 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1545 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1547 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1548 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1549 .addOperand(SrcReg0Sub0);
1551 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1552 AMDGPU::sub1, Src0SubRC);
1554 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1555 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1556 .addOperand(SrcReg0Sub1);
1558 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1559 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1561 .addImm(AMDGPU::sub0)
1563 .addImm(AMDGPU::sub1);
1565 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1567 // Try to legalize the operands in case we need to swap the order to keep it
1569 Worklist.push_back(LoHalf);
1570 Worklist.push_back(HiHalf);
1573 void SIInstrInfo::splitScalar64BitBinaryOp(
1574 SmallVectorImpl<MachineInstr *> &Worklist,
1576 unsigned Opcode) const {
1577 MachineBasicBlock &MBB = *Inst->getParent();
1578 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1580 MachineOperand &Dest = Inst->getOperand(0);
1581 MachineOperand &Src0 = Inst->getOperand(1);
1582 MachineOperand &Src1 = Inst->getOperand(2);
1583 DebugLoc DL = Inst->getDebugLoc();
1585 MachineBasicBlock::iterator MII = Inst;
1587 const MCInstrDesc &InstDesc = get(Opcode);
1588 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1589 MRI.getRegClass(Src0.getReg()) :
1590 &AMDGPU::SGPR_32RegClass;
1592 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1593 const TargetRegisterClass *Src1RC = Src1.isReg() ?
1594 MRI.getRegClass(Src1.getReg()) :
1595 &AMDGPU::SGPR_32RegClass;
1597 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
1599 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1600 AMDGPU::sub0, Src0SubRC);
1601 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1602 AMDGPU::sub0, Src1SubRC);
1604 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1605 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1607 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1608 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1609 .addOperand(SrcReg0Sub0)
1610 .addOperand(SrcReg1Sub0);
1612 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1613 AMDGPU::sub1, Src0SubRC);
1614 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1615 AMDGPU::sub1, Src1SubRC);
1617 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1618 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1619 .addOperand(SrcReg0Sub1)
1620 .addOperand(SrcReg1Sub1);
1622 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1623 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1625 .addImm(AMDGPU::sub0)
1627 .addImm(AMDGPU::sub1);
1629 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1631 // Try to legalize the operands in case we need to swap the order to keep it
1633 Worklist.push_back(LoHalf);
1634 Worklist.push_back(HiHalf);
1637 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
1638 MachineInstr *Inst) const {
1639 MachineBasicBlock &MBB = *Inst->getParent();
1640 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1642 MachineBasicBlock::iterator MII = Inst;
1643 DebugLoc DL = Inst->getDebugLoc();
1645 MachineOperand &Dest = Inst->getOperand(0);
1646 MachineOperand &Src = Inst->getOperand(1);
1648 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
1649 const TargetRegisterClass *SrcRC = Src.isReg() ?
1650 MRI.getRegClass(Src.getReg()) :
1651 &AMDGPU::SGPR_32RegClass;
1653 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1654 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1656 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
1658 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1659 AMDGPU::sub0, SrcSubRC);
1660 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1661 AMDGPU::sub1, SrcSubRC);
1663 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
1664 .addOperand(SrcRegSub0)
1667 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
1668 .addOperand(SrcRegSub1)
1671 MRI.replaceRegWith(Dest.getReg(), ResultReg);
1673 Worklist.push_back(First);
1674 Worklist.push_back(Second);
1677 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
1678 MachineInstr *Inst) const {
1679 // Add the implict and explicit register definitions.
1680 if (NewDesc.ImplicitUses) {
1681 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
1682 unsigned Reg = NewDesc.ImplicitUses[i];
1683 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
1687 if (NewDesc.ImplicitDefs) {
1688 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
1689 unsigned Reg = NewDesc.ImplicitDefs[i];
1690 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
1695 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1696 MachineBasicBlock *MBB,
1697 MachineBasicBlock::iterator I,
1699 unsigned Address, unsigned OffsetReg) const {
1700 const DebugLoc &DL = MBB->findDebugLoc(I);
1701 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1702 getIndirectIndexBegin(*MBB->getParent()));
1704 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
1705 .addReg(IndirectBaseReg, RegState::Define)
1706 .addOperand(I->getOperand(0))
1707 .addReg(IndirectBaseReg)
1713 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1714 MachineBasicBlock *MBB,
1715 MachineBasicBlock::iterator I,
1717 unsigned Address, unsigned OffsetReg) const {
1718 const DebugLoc &DL = MBB->findDebugLoc(I);
1719 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1720 getIndirectIndexBegin(*MBB->getParent()));
1722 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
1723 .addOperand(I->getOperand(0))
1724 .addOperand(I->getOperand(1))
1725 .addReg(IndirectBaseReg)
1731 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1732 const MachineFunction &MF) const {
1733 int End = getIndirectIndexEnd(MF);
1734 int Begin = getIndirectIndexBegin(MF);
1740 for (int Index = Begin; Index <= End; ++Index)
1741 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1743 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
1744 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1746 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
1747 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1749 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
1750 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1752 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
1753 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1755 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
1756 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
1759 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
1760 unsigned OperandName) const {
1761 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
1765 return &MI.getOperand(Idx);