1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI(st) {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
79 int64_t &Offset1) const {
80 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
83 unsigned Opc0 = Load0->getMachineOpcode();
84 unsigned Opc1 = Load1->getMachineOpcode();
86 // Make sure both are actually loads.
87 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
90 if (isDS(Opc0) && isDS(Opc1)) {
92 // FIXME: Handle this case:
93 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
97 if (Load0->getOperand(1) != Load1->getOperand(1))
101 if (findChainOperand(Load0) != findChainOperand(Load1))
104 // Skip read2 / write2 variants for simplicity.
105 // TODO: We should report true if the used offsets are adjacent (excluded
107 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
108 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
111 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
112 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
116 if (isSMRD(Opc0) && isSMRD(Opc1)) {
117 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
120 if (Load0->getOperand(0) != Load1->getOperand(0))
124 if (findChainOperand(Load0) != findChainOperand(Load1))
127 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
128 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
132 // MUBUF and MTBUF can access the same addresses.
133 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
135 // MUBUF and MTBUF have vaddr at different indices.
136 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
137 findChainOperand(Load0) != findChainOperand(Load1) ||
138 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
139 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
142 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
143 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
145 if (OffIdx0 == -1 || OffIdx1 == -1)
148 // getNamedOperandIdx returns the index for MachineInstrs. Since they
149 // inlcude the output in the operand list, but SDNodes don't, we need to
150 // subtract the index by one.
154 SDValue Off0 = Load0->getOperand(OffIdx0);
155 SDValue Off1 = Load1->getOperand(OffIdx1);
157 // The offset might be a FrameIndexSDNode.
158 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
161 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
162 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
169 static bool isStride64(unsigned Opc) {
171 case AMDGPU::DS_READ2ST64_B32:
172 case AMDGPU::DS_READ2ST64_B64:
173 case AMDGPU::DS_WRITE2ST64_B32:
174 case AMDGPU::DS_WRITE2ST64_B64:
181 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
182 unsigned &BaseReg, unsigned &Offset,
183 const TargetRegisterInfo *TRI) const {
184 unsigned Opc = LdSt->getOpcode();
186 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
187 AMDGPU::OpName::offset);
189 // Normal, single offset LDS instruction.
190 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
191 AMDGPU::OpName::addr);
193 BaseReg = AddrReg->getReg();
194 Offset = OffsetImm->getImm();
198 // The 2 offset instructions use offset0 and offset1 instead. We can treat
199 // these as a load with a single offset if the 2 offsets are consecutive. We
200 // will use this for some partially aligned loads.
201 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
202 AMDGPU::OpName::offset0);
203 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
204 AMDGPU::OpName::offset1);
206 uint8_t Offset0 = Offset0Imm->getImm();
207 uint8_t Offset1 = Offset1Imm->getImm();
208 assert(Offset1 > Offset0);
210 if (Offset1 - Offset0 == 1) {
211 // Each of these offsets is in element sized units, so we need to convert
212 // to bytes of the individual reads.
216 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
218 assert(LdSt->mayStore());
219 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
220 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
226 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
227 AMDGPU::OpName::addr);
228 BaseReg = AddrReg->getReg();
229 Offset = EltSize * Offset0;
236 if (isMUBUF(Opc) || isMTBUF(Opc)) {
237 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
240 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
241 AMDGPU::OpName::vaddr);
245 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
246 AMDGPU::OpName::offset);
247 BaseReg = AddrReg->getReg();
248 Offset = OffsetImm->getImm();
253 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
254 AMDGPU::OpName::offset);
258 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
259 AMDGPU::OpName::sbase);
260 BaseReg = SBaseReg->getReg();
261 Offset = OffsetImm->getImm();
268 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
269 MachineInstr *SecondLdSt,
270 unsigned NumLoads) const {
271 unsigned Opc0 = FirstLdSt->getOpcode();
272 unsigned Opc1 = SecondLdSt->getOpcode();
274 // TODO: This needs finer tuning
278 if (isDS(Opc0) && isDS(Opc1))
281 if (isSMRD(Opc0) && isSMRD(Opc1))
284 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
291 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
292 MachineBasicBlock::iterator MI, DebugLoc DL,
293 unsigned DestReg, unsigned SrcReg,
294 bool KillSrc) const {
296 // If we are trying to copy to or from SCC, there is a bug somewhere else in
297 // the backend. While it may be theoretically possible to do this, it should
298 // never be necessary.
299 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
301 static const int16_t Sub0_15[] = {
302 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
303 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
304 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
305 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
308 static const int16_t Sub0_7[] = {
309 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
310 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
313 static const int16_t Sub0_3[] = {
314 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
317 static const int16_t Sub0_2[] = {
318 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
321 static const int16_t Sub0_1[] = {
322 AMDGPU::sub0, AMDGPU::sub1, 0
326 const int16_t *SubIndices;
328 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
329 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
330 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
331 .addReg(SrcReg, getKillRegState(KillSrc));
334 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
335 if (DestReg == AMDGPU::VCC) {
336 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
337 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
338 .addReg(SrcReg, getKillRegState(KillSrc));
340 // FIXME: Hack until VReg_1 removed.
341 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
342 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
344 .addReg(SrcReg, getKillRegState(KillSrc));
350 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
356 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
357 Opcode = AMDGPU::S_MOV_B32;
360 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
361 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
362 Opcode = AMDGPU::S_MOV_B32;
365 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
366 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
367 Opcode = AMDGPU::S_MOV_B32;
368 SubIndices = Sub0_15;
370 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
371 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
372 AMDGPU::SReg_32RegClass.contains(SrcReg));
373 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
374 .addReg(SrcReg, getKillRegState(KillSrc));
377 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
378 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
379 AMDGPU::SReg_64RegClass.contains(SrcReg));
380 Opcode = AMDGPU::V_MOV_B32_e32;
383 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
384 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
385 Opcode = AMDGPU::V_MOV_B32_e32;
388 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
389 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
390 AMDGPU::SReg_128RegClass.contains(SrcReg));
391 Opcode = AMDGPU::V_MOV_B32_e32;
394 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
395 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
396 AMDGPU::SReg_256RegClass.contains(SrcReg));
397 Opcode = AMDGPU::V_MOV_B32_e32;
400 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
401 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
402 AMDGPU::SReg_512RegClass.contains(SrcReg));
403 Opcode = AMDGPU::V_MOV_B32_e32;
404 SubIndices = Sub0_15;
407 llvm_unreachable("Can't copy register!");
410 while (unsigned SubIdx = *SubIndices++) {
411 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
412 get(Opcode), RI.getSubReg(DestReg, SubIdx));
414 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
417 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
421 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
424 // Try to map original to commuted opcode
425 NewOpc = AMDGPU::getCommuteRev(Opcode);
426 // Check if the commuted (REV) opcode exists on the target.
427 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
430 // Try to map commuted to original opcode
431 NewOpc = AMDGPU::getCommuteOrig(Opcode);
432 // Check if the original (non-REV) opcode exists on the target.
433 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
439 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
441 if (DstRC->getSize() == 4) {
442 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
443 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
444 return AMDGPU::S_MOV_B64;
445 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
446 return AMDGPU::V_MOV_B64_PSEUDO;
451 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
452 MachineBasicBlock::iterator MI,
453 unsigned SrcReg, bool isKill,
455 const TargetRegisterClass *RC,
456 const TargetRegisterInfo *TRI) const {
457 MachineFunction *MF = MBB.getParent();
458 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
459 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
460 DebugLoc DL = MBB.findDebugLoc(MI);
463 if (RI.isSGPRClass(RC)) {
464 // We are only allowed to create one new instruction when spilling
465 // registers, so we need to use pseudo instruction for spilling
467 switch (RC->getSize() * 8) {
468 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
469 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
470 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
471 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
472 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
474 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
475 MFI->setHasSpilledVGPRs();
477 switch(RC->getSize() * 8) {
478 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
479 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
480 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
481 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
482 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
483 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
488 FrameInfo->setObjectAlignment(FrameIndex, 4);
489 BuildMI(MBB, MI, DL, get(Opcode))
491 .addFrameIndex(FrameIndex)
492 // Place-holder registers, these will be filled in by
493 // SIPrepareScratchRegs.
494 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
495 .addReg(AMDGPU::SGPR0, RegState::Undef);
497 LLVMContext &Ctx = MF->getFunction()->getContext();
498 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
500 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
505 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
506 MachineBasicBlock::iterator MI,
507 unsigned DestReg, int FrameIndex,
508 const TargetRegisterClass *RC,
509 const TargetRegisterInfo *TRI) const {
510 MachineFunction *MF = MBB.getParent();
511 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
512 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
513 DebugLoc DL = MBB.findDebugLoc(MI);
516 if (RI.isSGPRClass(RC)){
517 switch(RC->getSize() * 8) {
518 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
519 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
520 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
521 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
522 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
524 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
525 switch(RC->getSize() * 8) {
526 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
527 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
528 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
529 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
530 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
531 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
536 FrameInfo->setObjectAlignment(FrameIndex, 4);
537 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
538 .addFrameIndex(FrameIndex)
539 // Place-holder registers, these will be filled in by
540 // SIPrepareScratchRegs.
541 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
542 .addReg(AMDGPU::SGPR0, RegState::Undef);
545 LLVMContext &Ctx = MF->getFunction()->getContext();
546 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
547 " restore register");
548 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
552 /// \param @Offset Offset in bytes of the FrameIndex being spilled
553 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
554 MachineBasicBlock::iterator MI,
555 RegScavenger *RS, unsigned TmpReg,
556 unsigned FrameOffset,
557 unsigned Size) const {
558 MachineFunction *MF = MBB.getParent();
559 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
560 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
561 const SIRegisterInfo *TRI =
562 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
563 DebugLoc DL = MBB.findDebugLoc(MI);
564 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
565 unsigned WavefrontSize = ST.getWavefrontSize();
567 unsigned TIDReg = MFI->getTIDReg();
568 if (!MFI->hasCalculatedTID()) {
569 MachineBasicBlock &Entry = MBB.getParent()->front();
570 MachineBasicBlock::iterator Insert = Entry.front();
571 DebugLoc DL = Insert->getDebugLoc();
573 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
574 if (TIDReg == AMDGPU::NoRegister)
578 if (MFI->getShaderType() == ShaderType::COMPUTE &&
579 WorkGroupSize > WavefrontSize) {
581 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
582 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
583 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
584 unsigned InputPtrReg =
585 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
586 static const unsigned TIDIGRegs[3] = {
587 TIDIGXReg, TIDIGYReg, TIDIGZReg
589 for (unsigned Reg : TIDIGRegs) {
590 if (!Entry.isLiveIn(Reg))
591 Entry.addLiveIn(Reg);
594 RS->enterBasicBlock(&Entry);
595 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
596 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
597 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
599 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
600 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
602 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
604 // NGROUPS.X * NGROUPS.Y
605 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
608 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
609 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
612 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
613 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
617 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
618 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
623 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
628 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
634 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
638 MFI->setTIDReg(TIDReg);
641 // Add FrameIndex to LDS offset
642 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
643 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
650 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
659 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
664 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
665 MachineBasicBlock &MBB = *MI->getParent();
666 DebugLoc DL = MBB.findDebugLoc(MI);
667 switch (MI->getOpcode()) {
668 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
670 case AMDGPU::SI_CONSTDATA_PTR: {
671 unsigned Reg = MI->getOperand(0).getReg();
672 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
673 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
675 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
677 // Add 32-bit offset from this instruction to the start of the constant data.
678 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
680 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
681 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
682 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
685 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
686 .addReg(AMDGPU::SCC, RegState::Implicit);
687 MI->eraseFromParent();
690 case AMDGPU::SGPR_USE:
691 // This is just a placeholder for register allocation.
692 MI->eraseFromParent();
695 case AMDGPU::V_MOV_B64_PSEUDO: {
696 unsigned Dst = MI->getOperand(0).getReg();
697 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
698 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
700 const MachineOperand &SrcOp = MI->getOperand(1);
701 // FIXME: Will this work for 64-bit floating point immediates?
702 assert(!SrcOp.isFPImm());
704 APInt Imm(64, SrcOp.getImm());
705 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
706 .addImm(Imm.getLoBits(32).getZExtValue())
707 .addReg(Dst, RegState::Implicit);
708 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
709 .addImm(Imm.getHiBits(32).getZExtValue())
710 .addReg(Dst, RegState::Implicit);
712 assert(SrcOp.isReg());
713 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
714 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
715 .addReg(Dst, RegState::Implicit);
716 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
717 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
718 .addReg(Dst, RegState::Implicit);
720 MI->eraseFromParent();
727 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
730 if (MI->getNumOperands() < 3)
733 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
734 AMDGPU::OpName::src0);
735 assert(Src0Idx != -1 && "Should always have src0 operand");
737 MachineOperand &Src0 = MI->getOperand(Src0Idx);
741 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
742 AMDGPU::OpName::src1);
746 MachineOperand &Src1 = MI->getOperand(Src1Idx);
748 // Make sure it's legal to commute operands for VOP2.
749 if (isVOP2(MI->getOpcode()) &&
750 (!isOperandLegal(MI, Src0Idx, &Src1) ||
751 !isOperandLegal(MI, Src1Idx, &Src0))) {
756 // Allow commuting instructions with Imm operands.
757 if (NewMI || !Src1.isImm() ||
758 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
762 // Be sure to copy the source modifiers to the right place.
763 if (MachineOperand *Src0Mods
764 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
765 MachineOperand *Src1Mods
766 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
768 int Src0ModsVal = Src0Mods->getImm();
769 if (!Src1Mods && Src0ModsVal != 0)
772 // XXX - This assert might be a lie. It might be useful to have a neg
773 // modifier with 0.0.
774 int Src1ModsVal = Src1Mods->getImm();
775 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
777 Src1Mods->setImm(Src0ModsVal);
778 Src0Mods->setImm(Src1ModsVal);
781 unsigned Reg = Src0.getReg();
782 unsigned SubReg = Src0.getSubReg();
784 Src0.ChangeToImmediate(Src1.getImm());
786 llvm_unreachable("Should only have immediates");
788 Src1.ChangeToRegister(Reg, false);
789 Src1.setSubReg(SubReg);
791 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
795 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
800 // This needs to be implemented because the source modifiers may be inserted
801 // between the true commutable operands, and the base
802 // TargetInstrInfo::commuteInstruction uses it.
803 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
805 unsigned &SrcOpIdx2) const {
806 const MCInstrDesc &MCID = MI->getDesc();
807 if (!MCID.isCommutable())
810 unsigned Opc = MI->getOpcode();
811 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
815 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
817 if (!MI->getOperand(Src0Idx).isReg())
820 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
824 if (!MI->getOperand(Src1Idx).isReg())
827 // If any source modifiers are set, the generic instruction commuting won't
828 // understand how to copy the source modifiers.
829 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
830 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
838 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
839 MachineBasicBlock::iterator I,
841 unsigned SrcReg) const {
842 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
843 DstReg) .addReg(SrcReg);
846 bool SIInstrInfo::isMov(unsigned Opcode) const {
848 default: return false;
849 case AMDGPU::S_MOV_B32:
850 case AMDGPU::S_MOV_B64:
851 case AMDGPU::V_MOV_B32_e32:
852 case AMDGPU::V_MOV_B32_e64:
858 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
859 return RC != &AMDGPU::EXECRegRegClass;
863 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
864 AliasAnalysis *AA) const {
865 switch(MI->getOpcode()) {
866 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
867 case AMDGPU::S_MOV_B32:
868 case AMDGPU::S_MOV_B64:
869 case AMDGPU::V_MOV_B32_e32:
870 return MI->getOperand(1).isImm();
874 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
875 int WidthB, int OffsetB) {
876 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
877 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
878 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
879 return LowOffset + LowWidth <= HighOffset;
882 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
883 MachineInstr *MIb) const {
884 unsigned BaseReg0, Offset0;
885 unsigned BaseReg1, Offset1;
887 if (getLdStBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
888 getLdStBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
889 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
890 "read2 / write2 not expected here yet");
891 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
892 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
893 if (BaseReg0 == BaseReg1 &&
894 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
902 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
904 AliasAnalysis *AA) const {
905 unsigned Opc0 = MIa->getOpcode();
906 unsigned Opc1 = MIb->getOpcode();
908 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
909 "MIa must load from or modify a memory location");
910 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
911 "MIb must load from or modify a memory location");
913 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
916 // XXX - Can we relax this between address spaces?
917 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
920 // TODO: Should we check the address space from the MachineMemOperand? That
921 // would allow us to distinguish objects we know don't alias based on the
922 // underlying addres space, even if it was lowered to a different one,
923 // e.g. private accesses lowered to use MUBUF instructions on a scratch
927 return checkInstOffsetsDoNotOverlap(MIa, MIb);
929 return !isFLAT(Opc1);
932 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
933 if (isMUBUF(Opc1) || isMTBUF(Opc1))
934 return checkInstOffsetsDoNotOverlap(MIa, MIb);
936 return !isFLAT(Opc1) && !isSMRD(Opc1);
941 return checkInstOffsetsDoNotOverlap(MIa, MIb);
943 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
948 return checkInstOffsetsDoNotOverlap(MIa, MIb);
956 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
957 int64_t SVal = Imm.getSExtValue();
958 if (SVal >= -16 && SVal <= 64)
961 if (Imm.getBitWidth() == 64) {
962 uint64_t Val = Imm.getZExtValue();
963 return (DoubleToBits(0.0) == Val) ||
964 (DoubleToBits(1.0) == Val) ||
965 (DoubleToBits(-1.0) == Val) ||
966 (DoubleToBits(0.5) == Val) ||
967 (DoubleToBits(-0.5) == Val) ||
968 (DoubleToBits(2.0) == Val) ||
969 (DoubleToBits(-2.0) == Val) ||
970 (DoubleToBits(4.0) == Val) ||
971 (DoubleToBits(-4.0) == Val);
974 // The actual type of the operand does not seem to matter as long
975 // as the bits match one of the inline immediate values. For example:
977 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
978 // so it is a legal inline immediate.
980 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
981 // floating-point, so it is a legal inline immediate.
982 uint32_t Val = Imm.getZExtValue();
984 return (FloatToBits(0.0f) == Val) ||
985 (FloatToBits(1.0f) == Val) ||
986 (FloatToBits(-1.0f) == Val) ||
987 (FloatToBits(0.5f) == Val) ||
988 (FloatToBits(-0.5f) == Val) ||
989 (FloatToBits(2.0f) == Val) ||
990 (FloatToBits(-2.0f) == Val) ||
991 (FloatToBits(4.0f) == Val) ||
992 (FloatToBits(-4.0f) == Val);
995 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
996 unsigned OpSize) const {
998 // MachineOperand provides no way to tell the true operand size, since it
999 // only records a 64-bit value. We need to know the size to determine if a
1000 // 32-bit floating point immediate bit pattern is legal for an integer
1001 // immediate. It would be for any 32-bit integer operand, but would not be
1002 // for a 64-bit one.
1004 unsigned BitSize = 8 * OpSize;
1005 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1011 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1012 unsigned OpSize) const {
1013 return MO.isImm() && !isInlineConstant(MO, OpSize);
1016 static bool compareMachineOp(const MachineOperand &Op0,
1017 const MachineOperand &Op1) {
1018 if (Op0.getType() != Op1.getType())
1021 switch (Op0.getType()) {
1022 case MachineOperand::MO_Register:
1023 return Op0.getReg() == Op1.getReg();
1024 case MachineOperand::MO_Immediate:
1025 return Op0.getImm() == Op1.getImm();
1027 llvm_unreachable("Didn't expect to be comparing these operand types");
1031 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1032 const MachineOperand &MO) const {
1033 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1035 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1037 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1040 if (OpInfo.RegClass < 0)
1043 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1044 if (isLiteralConstant(MO, OpSize))
1045 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1047 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1050 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) const {
1052 case AMDGPUAS::GLOBAL_ADDRESS: {
1053 // MUBUF instructions a 12-bit offset in bytes.
1054 return isUInt<12>(OffsetSize);
1056 case AMDGPUAS::CONSTANT_ADDRESS: {
1057 // SMRD instructions have an 8-bit offset in dwords on SI and
1058 // a 20-bit offset in bytes on VI.
1059 if (RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1060 return isUInt<20>(OffsetSize);
1062 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1064 case AMDGPUAS::LOCAL_ADDRESS:
1065 case AMDGPUAS::REGION_ADDRESS: {
1066 // The single offset versions have a 16-bit offset in bytes.
1067 return isUInt<16>(OffsetSize);
1069 case AMDGPUAS::PRIVATE_ADDRESS:
1070 // Indirect register addressing does not use any offsets.
1076 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1077 int Op32 = AMDGPU::getVOPe32(Opcode);
1081 return pseudoToMCOpcode(Op32) != -1;
1084 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1085 // The src0_modifier operand is present on all instructions
1086 // that have modifiers.
1088 return AMDGPU::getNamedOperandIdx(Opcode,
1089 AMDGPU::OpName::src0_modifiers) != -1;
1092 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1093 unsigned OpName) const {
1094 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1095 return Mods && Mods->getImm();
1098 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1099 const MachineOperand &MO,
1100 unsigned OpSize) const {
1101 // Literal constants use the constant bus.
1102 if (isLiteralConstant(MO, OpSize))
1105 if (!MO.isReg() || !MO.isUse())
1108 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1109 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1111 // FLAT_SCR is just an SGPR pair.
1112 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1115 // EXEC register uses the constant bus.
1116 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1119 // SGPRs use the constant bus
1120 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1121 (!MO.isImplicit() &&
1122 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1123 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1130 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1131 StringRef &ErrInfo) const {
1132 uint16_t Opcode = MI->getOpcode();
1133 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1134 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1135 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1136 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1138 // Make sure the number of operands is correct.
1139 const MCInstrDesc &Desc = get(Opcode);
1140 if (!Desc.isVariadic() &&
1141 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1142 ErrInfo = "Instruction has wrong number of operands.";
1146 // Make sure the register classes are correct
1147 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1148 if (MI->getOperand(i).isFPImm()) {
1149 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1150 "all fp values to integers.";
1154 int RegClass = Desc.OpInfo[i].RegClass;
1156 switch (Desc.OpInfo[i].OperandType) {
1157 case MCOI::OPERAND_REGISTER:
1158 if (MI->getOperand(i).isImm()) {
1159 ErrInfo = "Illegal immediate value for operand.";
1163 case AMDGPU::OPERAND_REG_IMM32:
1165 case AMDGPU::OPERAND_REG_INLINE_C:
1166 if (isLiteralConstant(MI->getOperand(i),
1167 RI.getRegClass(RegClass)->getSize())) {
1168 ErrInfo = "Illegal immediate value for operand.";
1172 case MCOI::OPERAND_IMMEDIATE:
1173 // Check if this operand is an immediate.
1174 // FrameIndex operands will be replaced by immediates, so they are
1176 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1177 ErrInfo = "Expected immediate, but got non-immediate";
1185 if (!MI->getOperand(i).isReg())
1188 if (RegClass != -1) {
1189 unsigned Reg = MI->getOperand(i).getReg();
1190 if (TargetRegisterInfo::isVirtualRegister(Reg))
1193 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1194 if (!RC->contains(Reg)) {
1195 ErrInfo = "Operand has incorrect register class.";
1203 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1204 // Only look at the true operands. Only a real operand can use the constant
1205 // bus, and we don't want to check pseudo-operands like the source modifier
1207 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1209 unsigned ConstantBusCount = 0;
1210 unsigned SGPRUsed = AMDGPU::NoRegister;
1211 for (int OpIdx : OpIndices) {
1214 const MachineOperand &MO = MI->getOperand(OpIdx);
1215 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1217 if (MO.getReg() != SGPRUsed)
1219 SGPRUsed = MO.getReg();
1225 if (ConstantBusCount > 1) {
1226 ErrInfo = "VOP* instruction uses the constant bus more than once";
1231 // Verify misc. restrictions on specific instructions.
1232 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1233 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1234 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1235 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1236 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1237 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1238 if (!compareMachineOp(Src0, Src1) &&
1239 !compareMachineOp(Src0, Src2)) {
1240 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1249 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1250 switch (MI.getOpcode()) {
1251 default: return AMDGPU::INSTRUCTION_LIST_END;
1252 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1253 case AMDGPU::COPY: return AMDGPU::COPY;
1254 case AMDGPU::PHI: return AMDGPU::PHI;
1255 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1256 case AMDGPU::S_MOV_B32:
1257 return MI.getOperand(1).isReg() ?
1258 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1259 case AMDGPU::S_ADD_I32:
1260 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1261 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1262 case AMDGPU::S_SUB_I32:
1263 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1264 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1265 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1266 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1267 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1268 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1269 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1270 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1271 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1272 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1273 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1274 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1275 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1276 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1277 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1278 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1279 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1280 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1281 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1282 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1283 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1284 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1285 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1286 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1287 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1288 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1289 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1290 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1291 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1292 case AMDGPU::S_LOAD_DWORD_IMM:
1293 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1294 case AMDGPU::S_LOAD_DWORDX2_IMM:
1295 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1296 case AMDGPU::S_LOAD_DWORDX4_IMM:
1297 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1298 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1299 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1300 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1304 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1305 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1308 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1309 unsigned OpNo) const {
1310 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1311 const MCInstrDesc &Desc = get(MI.getOpcode());
1312 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1313 Desc.OpInfo[OpNo].RegClass == -1) {
1314 unsigned Reg = MI.getOperand(OpNo).getReg();
1316 if (TargetRegisterInfo::isVirtualRegister(Reg))
1317 return MRI.getRegClass(Reg);
1318 return RI.getPhysRegClass(Reg);
1321 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1322 return RI.getRegClass(RCID);
1325 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1326 switch (MI.getOpcode()) {
1328 case AMDGPU::REG_SEQUENCE:
1330 case AMDGPU::INSERT_SUBREG:
1331 return RI.hasVGPRs(getOpRegClass(MI, 0));
1333 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1337 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1338 MachineBasicBlock::iterator I = MI;
1339 MachineBasicBlock *MBB = MI->getParent();
1340 MachineOperand &MO = MI->getOperand(OpIdx);
1341 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1342 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1343 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1344 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1346 Opcode = AMDGPU::COPY;
1347 else if (RI.isSGPRClass(RC))
1348 Opcode = AMDGPU::S_MOV_B32;
1351 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1352 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1353 VRC = &AMDGPU::VReg_64RegClass;
1355 VRC = &AMDGPU::VGPR_32RegClass;
1357 unsigned Reg = MRI.createVirtualRegister(VRC);
1358 DebugLoc DL = MBB->findDebugLoc(I);
1359 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1361 MO.ChangeToRegister(Reg, false);
1364 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1365 MachineRegisterInfo &MRI,
1366 MachineOperand &SuperReg,
1367 const TargetRegisterClass *SuperRC,
1369 const TargetRegisterClass *SubRC)
1371 assert(SuperReg.isReg());
1373 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1374 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1376 // Just in case the super register is itself a sub-register, copy it to a new
1377 // value so we don't need to worry about merging its subreg index with the
1378 // SubIdx passed to this function. The register coalescer should be able to
1379 // eliminate this extra copy.
1380 MachineBasicBlock *MBB = MI->getParent();
1381 DebugLoc DL = MI->getDebugLoc();
1383 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1384 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1386 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1387 .addReg(NewSuperReg, 0, SubIdx);
1392 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1393 MachineBasicBlock::iterator MII,
1394 MachineRegisterInfo &MRI,
1396 const TargetRegisterClass *SuperRC,
1398 const TargetRegisterClass *SubRC) const {
1400 // XXX - Is there a better way to do this?
1401 if (SubIdx == AMDGPU::sub0)
1402 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1403 if (SubIdx == AMDGPU::sub1)
1404 return MachineOperand::CreateImm(Op.getImm() >> 32);
1406 llvm_unreachable("Unhandled register index for immediate");
1409 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1411 return MachineOperand::CreateReg(SubReg, false);
1414 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1415 MachineBasicBlock::iterator MI,
1416 MachineRegisterInfo &MRI,
1417 const TargetRegisterClass *RC,
1418 const MachineOperand &Op) const {
1419 MachineBasicBlock *MBB = MI->getParent();
1420 DebugLoc DL = MI->getDebugLoc();
1421 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1422 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1423 unsigned Dst = MRI.createVirtualRegister(RC);
1425 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1427 .addImm(Op.getImm() & 0xFFFFFFFF);
1428 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1430 .addImm(Op.getImm() >> 32);
1432 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1434 .addImm(AMDGPU::sub0)
1436 .addImm(AMDGPU::sub1);
1438 Worklist.push_back(Lo);
1439 Worklist.push_back(Hi);
1444 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1445 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1446 assert(Inst->getNumExplicitOperands() == 3);
1447 MachineOperand Op1 = Inst->getOperand(1);
1448 Inst->RemoveOperand(1);
1449 Inst->addOperand(Op1);
1452 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1453 const MachineOperand *MO) const {
1454 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1455 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1456 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1457 const TargetRegisterClass *DefinedRC =
1458 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1460 MO = &MI->getOperand(OpIdx);
1462 if (isVALU(InstDesc.Opcode) &&
1463 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1465 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1466 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1469 const MachineOperand &Op = MI->getOperand(i);
1470 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1471 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1479 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1481 // In order to be legal, the common sub-class must be equal to the
1482 // class of the current operand. For example:
1484 // v_mov_b32 s0 ; Operand defined as vsrc_32
1485 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1487 // s_sendmsg 0, s0 ; Operand defined as m0reg
1488 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1490 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1494 // Handle non-register types that are treated like immediates.
1495 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1498 // This operand expects an immediate.
1502 return isImmOperandLegal(MI, OpIdx, *MO);
1505 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1506 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1508 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1509 AMDGPU::OpName::src0);
1510 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1511 AMDGPU::OpName::src1);
1512 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1513 AMDGPU::OpName::src2);
1516 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1518 if (!isOperandLegal(MI, Src0Idx))
1519 legalizeOpWithMove(MI, Src0Idx);
1522 if (isOperandLegal(MI, Src1Idx))
1525 // Usually src0 of VOP2 instructions allow more types of inputs
1526 // than src1, so try to commute the instruction to decrease our
1527 // chances of having to insert a MOV instruction to legalize src1.
1528 if (MI->isCommutable()) {
1529 if (commuteInstruction(MI))
1530 // If we are successful in commuting, then we know MI is legal, so
1535 legalizeOpWithMove(MI, Src1Idx);
1539 // XXX - Do any VOP3 instructions read VCC?
1541 if (isVOP3(MI->getOpcode())) {
1542 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1544 // Find the one SGPR operand we are allowed to use.
1545 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1547 for (unsigned i = 0; i < 3; ++i) {
1548 int Idx = VOP3Idx[i];
1551 MachineOperand &MO = MI->getOperand(Idx);
1554 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1555 continue; // VGPRs are legal
1557 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1559 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1560 SGPRReg = MO.getReg();
1561 // We can use one SGPR in each VOP3 instruction.
1564 } else if (!isLiteralConstant(MO, getOpSize(MI->getOpcode(), Idx))) {
1565 // If it is not a register and not a literal constant, then it must be
1566 // an inline constant which is always legal.
1569 // If we make it this far, then the operand is not legal and we must
1571 legalizeOpWithMove(MI, Idx);
1575 // Legalize REG_SEQUENCE and PHI
1576 // The register class of the operands much be the same type as the register
1577 // class of the output.
1578 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1579 MI->getOpcode() == AMDGPU::PHI) {
1580 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1581 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1582 if (!MI->getOperand(i).isReg() ||
1583 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1585 const TargetRegisterClass *OpRC =
1586 MRI.getRegClass(MI->getOperand(i).getReg());
1587 if (RI.hasVGPRs(OpRC)) {
1594 // If any of the operands are VGPR registers, then they all most be
1595 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1597 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1600 VRC = RI.getEquivalentVGPRClass(SRC);
1607 // Update all the operands so they have the same type.
1608 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1609 if (!MI->getOperand(i).isReg() ||
1610 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1612 unsigned DstReg = MRI.createVirtualRegister(RC);
1613 MachineBasicBlock *InsertBB;
1614 MachineBasicBlock::iterator Insert;
1615 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1616 InsertBB = MI->getParent();
1619 // MI is a PHI instruction.
1620 InsertBB = MI->getOperand(i + 1).getMBB();
1621 Insert = InsertBB->getFirstTerminator();
1623 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1624 get(AMDGPU::COPY), DstReg)
1625 .addOperand(MI->getOperand(i));
1626 MI->getOperand(i).setReg(DstReg);
1630 // Legalize INSERT_SUBREG
1631 // src0 must have the same register class as dst
1632 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1633 unsigned Dst = MI->getOperand(0).getReg();
1634 unsigned Src0 = MI->getOperand(1).getReg();
1635 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1636 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1637 if (DstRC != Src0RC) {
1638 MachineBasicBlock &MBB = *MI->getParent();
1639 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1640 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1642 MI->getOperand(1).setReg(NewSrc0);
1647 // Legalize MUBUF* instructions
1648 // FIXME: If we start using the non-addr64 instructions for compute, we
1649 // may need to legalize them here.
1651 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1652 if (SRsrcIdx != -1) {
1653 // We have an MUBUF instruction
1654 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1655 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1656 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1657 RI.getRegClass(SRsrcRC))) {
1658 // The operands are legal.
1659 // FIXME: We may need to legalize operands besided srsrc.
1663 MachineBasicBlock &MBB = *MI->getParent();
1664 // Extract the the ptr from the resource descriptor.
1666 // SRsrcPtrLo = srsrc:sub0
1667 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1668 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VGPR_32RegClass);
1670 // SRsrcPtrHi = srsrc:sub1
1671 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1672 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VGPR_32RegClass);
1674 // Create an empty resource descriptor
1675 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1676 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1677 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1678 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1679 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1682 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1686 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1687 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1689 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1691 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1692 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1694 .addImm(RsrcDataFormat >> 32);
1696 // NewSRsrc = {Zero64, SRsrcFormat}
1697 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1700 .addImm(AMDGPU::sub0_sub1)
1701 .addReg(SRsrcFormatLo)
1702 .addImm(AMDGPU::sub2)
1703 .addReg(SRsrcFormatHi)
1704 .addImm(AMDGPU::sub3);
1706 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1707 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1708 unsigned NewVAddrLo;
1709 unsigned NewVAddrHi;
1711 // This is already an ADDR64 instruction so we need to add the pointer
1712 // extracted from the resource descriptor to the current value of VAddr.
1713 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1714 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1716 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1717 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1720 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1721 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1723 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1724 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1727 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1728 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1729 .addReg(AMDGPU::VCC, RegState::Implicit);
1732 // This instructions is the _OFFSET variant, so we need to convert it to
1734 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1735 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1736 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1738 // Create the new instruction.
1739 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1740 MachineInstr *Addr64 =
1741 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1744 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1745 // This will be replaced later
1746 // with the new value of vaddr.
1747 .addOperand(*SOffset)
1748 .addOperand(*Offset);
1750 MI->removeFromParent();
1753 NewVAddrLo = SRsrcPtrLo;
1754 NewVAddrHi = SRsrcPtrHi;
1755 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1756 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1759 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1760 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1763 .addImm(AMDGPU::sub0)
1765 .addImm(AMDGPU::sub1);
1768 // Update the instruction to use NewVaddr
1769 VAddr->setReg(NewVAddr);
1770 // Update the instruction to use NewSRsrc
1771 SRsrc->setReg(NewSRsrc);
1775 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1776 const TargetRegisterClass *HalfRC,
1777 unsigned HalfImmOp, unsigned HalfSGPROp,
1778 MachineInstr *&Lo, MachineInstr *&Hi) const {
1780 DebugLoc DL = MI->getDebugLoc();
1781 MachineBasicBlock *MBB = MI->getParent();
1782 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1783 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1784 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1785 unsigned HalfSize = HalfRC->getSize();
1786 const MachineOperand *OffOp =
1787 getNamedOperand(*MI, AMDGPU::OpName::offset);
1788 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1790 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1793 bool isVI = RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
1794 unsigned OffScale = isVI ? 1 : 4;
1795 // Handle the _IMM variant
1796 unsigned LoOffset = OffOp->getImm() * OffScale;
1797 unsigned HiOffset = LoOffset + HalfSize;
1798 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1800 .addImm(LoOffset / OffScale);
1802 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1803 unsigned OffsetSGPR =
1804 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1805 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1806 .addImm(HiOffset); // The offset in register is in bytes.
1807 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1809 .addReg(OffsetSGPR);
1811 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1813 .addImm(HiOffset / OffScale);
1816 // Handle the _SGPR variant
1817 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1818 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1821 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1822 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1825 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1827 .addReg(OffsetSGPR);
1830 unsigned SubLo, SubHi;
1833 SubLo = AMDGPU::sub0;
1834 SubHi = AMDGPU::sub1;
1837 SubLo = AMDGPU::sub0_sub1;
1838 SubHi = AMDGPU::sub2_sub3;
1841 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1842 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1845 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1846 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1849 llvm_unreachable("Unhandled HalfSize");
1852 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1853 .addOperand(MI->getOperand(0))
1860 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1861 MachineBasicBlock *MBB = MI->getParent();
1862 switch (MI->getOpcode()) {
1863 case AMDGPU::S_LOAD_DWORD_IMM:
1864 case AMDGPU::S_LOAD_DWORD_SGPR:
1865 case AMDGPU::S_LOAD_DWORDX2_IMM:
1866 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1867 case AMDGPU::S_LOAD_DWORDX4_IMM:
1868 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1869 unsigned NewOpcode = getVALUOp(*MI);
1873 if (MI->getOperand(2).isReg()) {
1874 RegOffset = MI->getOperand(2).getReg();
1877 assert(MI->getOperand(2).isImm());
1878 // SMRD instructions take a dword offsets on SI and byte offset on VI
1879 // and MUBUF instructions always take a byte offset.
1880 ImmOffset = MI->getOperand(2).getImm();
1881 if (RI.ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
1883 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1885 if (isUInt<12>(ImmOffset)) {
1886 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1890 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1897 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1898 unsigned DWord0 = RegOffset;
1899 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1900 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1901 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1902 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1904 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1906 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1907 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1908 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1909 .addImm(RsrcDataFormat >> 32);
1910 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1912 .addImm(AMDGPU::sub0)
1914 .addImm(AMDGPU::sub1)
1916 .addImm(AMDGPU::sub2)
1918 .addImm(AMDGPU::sub3);
1919 MI->setDesc(get(NewOpcode));
1920 if (MI->getOperand(2).isReg()) {
1921 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1923 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1925 MI->getOperand(1).setReg(SRsrc);
1926 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
1927 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1929 const TargetRegisterClass *NewDstRC =
1930 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
1932 unsigned DstReg = MI->getOperand(0).getReg();
1933 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1934 MRI.replaceRegWith(DstReg, NewDstReg);
1937 case AMDGPU::S_LOAD_DWORDX8_IMM:
1938 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
1939 MachineInstr *Lo, *Hi;
1940 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
1941 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
1942 MI->eraseFromParent();
1943 moveSMRDToVALU(Lo, MRI);
1944 moveSMRDToVALU(Hi, MRI);
1948 case AMDGPU::S_LOAD_DWORDX16_IMM:
1949 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
1950 MachineInstr *Lo, *Hi;
1951 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
1952 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
1953 MI->eraseFromParent();
1954 moveSMRDToVALU(Lo, MRI);
1955 moveSMRDToVALU(Hi, MRI);
1961 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1962 SmallVector<MachineInstr *, 128> Worklist;
1963 Worklist.push_back(&TopInst);
1965 while (!Worklist.empty()) {
1966 MachineInstr *Inst = Worklist.pop_back_val();
1967 MachineBasicBlock *MBB = Inst->getParent();
1968 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1970 unsigned Opcode = Inst->getOpcode();
1971 unsigned NewOpcode = getVALUOp(*Inst);
1973 // Handle some special cases
1976 if (isSMRD(Inst->getOpcode())) {
1977 moveSMRDToVALU(Inst, MRI);
1980 case AMDGPU::S_MOV_B64: {
1981 DebugLoc DL = Inst->getDebugLoc();
1983 // If the source operand is a register we can replace this with a
1985 if (Inst->getOperand(1).isReg()) {
1986 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1987 .addOperand(Inst->getOperand(0))
1988 .addOperand(Inst->getOperand(1));
1989 Worklist.push_back(Copy);
1991 // Otherwise, we need to split this into two movs, because there is
1992 // no 64-bit VALU move instruction.
1993 unsigned Reg = Inst->getOperand(0).getReg();
1994 unsigned Dst = split64BitImm(Worklist,
1997 MRI.getRegClass(Reg),
1998 Inst->getOperand(1));
1999 MRI.replaceRegWith(Reg, Dst);
2001 Inst->eraseFromParent();
2004 case AMDGPU::S_AND_B64:
2005 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
2006 Inst->eraseFromParent();
2009 case AMDGPU::S_OR_B64:
2010 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
2011 Inst->eraseFromParent();
2014 case AMDGPU::S_XOR_B64:
2015 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
2016 Inst->eraseFromParent();
2019 case AMDGPU::S_NOT_B64:
2020 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
2021 Inst->eraseFromParent();
2024 case AMDGPU::S_BCNT1_I32_B64:
2025 splitScalar64BitBCNT(Worklist, Inst);
2026 Inst->eraseFromParent();
2029 case AMDGPU::S_BFE_I64: {
2030 splitScalar64BitBFE(Worklist, Inst);
2031 Inst->eraseFromParent();
2035 case AMDGPU::S_LSHL_B32:
2036 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2037 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2041 case AMDGPU::S_ASHR_I32:
2042 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2043 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2047 case AMDGPU::S_LSHR_B32:
2048 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2049 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2053 case AMDGPU::S_LSHL_B64:
2054 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2055 NewOpcode = AMDGPU::V_LSHLREV_B64;
2059 case AMDGPU::S_ASHR_I64:
2060 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2061 NewOpcode = AMDGPU::V_ASHRREV_I64;
2065 case AMDGPU::S_LSHR_B64:
2066 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2067 NewOpcode = AMDGPU::V_LSHRREV_B64;
2072 case AMDGPU::S_BFE_U64:
2073 case AMDGPU::S_BFM_B64:
2074 llvm_unreachable("Moving this op to VALU not implemented");
2077 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2078 // We cannot move this instruction to the VALU, so we should try to
2079 // legalize its operands instead.
2080 legalizeOperands(Inst);
2084 // Use the new VALU Opcode.
2085 const MCInstrDesc &NewDesc = get(NewOpcode);
2086 Inst->setDesc(NewDesc);
2088 // Remove any references to SCC. Vector instructions can't read from it, and
2089 // We're just about to add the implicit use / defs of VCC, and we don't want
2091 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2092 MachineOperand &Op = Inst->getOperand(i);
2093 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2094 Inst->RemoveOperand(i);
2097 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2098 // We are converting these to a BFE, so we need to add the missing
2099 // operands for the size and offset.
2100 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2101 Inst->addOperand(MachineOperand::CreateImm(0));
2102 Inst->addOperand(MachineOperand::CreateImm(Size));
2104 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2105 // The VALU version adds the second operand to the result, so insert an
2107 Inst->addOperand(MachineOperand::CreateImm(0));
2110 addDescImplicitUseDef(NewDesc, Inst);
2112 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2113 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2114 // If we need to move this to VGPRs, we need to unpack the second operand
2115 // back into the 2 separate ones for bit offset and width.
2116 assert(OffsetWidthOp.isImm() &&
2117 "Scalar BFE is only implemented for constant width and offset");
2118 uint32_t Imm = OffsetWidthOp.getImm();
2120 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2121 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2122 Inst->RemoveOperand(2); // Remove old immediate.
2123 Inst->addOperand(MachineOperand::CreateImm(Offset));
2124 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2127 // Update the destination register class.
2129 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2132 // For target instructions, getOpRegClass just returns the virtual
2133 // register class associated with the operand, so we need to find an
2134 // equivalent VGPR register class in order to move the instruction to the
2138 case AMDGPU::REG_SEQUENCE:
2139 case AMDGPU::INSERT_SUBREG:
2140 if (RI.hasVGPRs(NewDstRC))
2142 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2150 unsigned DstReg = Inst->getOperand(0).getReg();
2151 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2152 MRI.replaceRegWith(DstReg, NewDstReg);
2154 // Legalize the operands
2155 legalizeOperands(Inst);
2157 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
2158 E = MRI.use_end(); I != E; ++I) {
2159 MachineInstr &UseMI = *I->getParent();
2160 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2161 Worklist.push_back(&UseMI);
2167 //===----------------------------------------------------------------------===//
2168 // Indirect addressing callbacks
2169 //===----------------------------------------------------------------------===//
2171 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2172 unsigned Channel) const {
2173 assert(Channel == 0);
2177 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2178 return &AMDGPU::VGPR_32RegClass;
2181 void SIInstrInfo::splitScalar64BitUnaryOp(
2182 SmallVectorImpl<MachineInstr *> &Worklist,
2184 unsigned Opcode) const {
2185 MachineBasicBlock &MBB = *Inst->getParent();
2186 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2188 MachineOperand &Dest = Inst->getOperand(0);
2189 MachineOperand &Src0 = Inst->getOperand(1);
2190 DebugLoc DL = Inst->getDebugLoc();
2192 MachineBasicBlock::iterator MII = Inst;
2194 const MCInstrDesc &InstDesc = get(Opcode);
2195 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2196 MRI.getRegClass(Src0.getReg()) :
2197 &AMDGPU::SGPR_32RegClass;
2199 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2201 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2202 AMDGPU::sub0, Src0SubRC);
2204 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2205 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2207 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2208 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2209 .addOperand(SrcReg0Sub0);
2211 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2212 AMDGPU::sub1, Src0SubRC);
2214 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2215 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2216 .addOperand(SrcReg0Sub1);
2218 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2219 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2221 .addImm(AMDGPU::sub0)
2223 .addImm(AMDGPU::sub1);
2225 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2227 // Try to legalize the operands in case we need to swap the order to keep it
2229 Worklist.push_back(LoHalf);
2230 Worklist.push_back(HiHalf);
2233 void SIInstrInfo::splitScalar64BitBinaryOp(
2234 SmallVectorImpl<MachineInstr *> &Worklist,
2236 unsigned Opcode) const {
2237 MachineBasicBlock &MBB = *Inst->getParent();
2238 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2240 MachineOperand &Dest = Inst->getOperand(0);
2241 MachineOperand &Src0 = Inst->getOperand(1);
2242 MachineOperand &Src1 = Inst->getOperand(2);
2243 DebugLoc DL = Inst->getDebugLoc();
2245 MachineBasicBlock::iterator MII = Inst;
2247 const MCInstrDesc &InstDesc = get(Opcode);
2248 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2249 MRI.getRegClass(Src0.getReg()) :
2250 &AMDGPU::SGPR_32RegClass;
2252 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2253 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2254 MRI.getRegClass(Src1.getReg()) :
2255 &AMDGPU::SGPR_32RegClass;
2257 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2259 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2260 AMDGPU::sub0, Src0SubRC);
2261 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2262 AMDGPU::sub0, Src1SubRC);
2264 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2265 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2267 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2268 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2269 .addOperand(SrcReg0Sub0)
2270 .addOperand(SrcReg1Sub0);
2272 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2273 AMDGPU::sub1, Src0SubRC);
2274 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2275 AMDGPU::sub1, Src1SubRC);
2277 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2278 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2279 .addOperand(SrcReg0Sub1)
2280 .addOperand(SrcReg1Sub1);
2282 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2283 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2285 .addImm(AMDGPU::sub0)
2287 .addImm(AMDGPU::sub1);
2289 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2291 // Try to legalize the operands in case we need to swap the order to keep it
2293 Worklist.push_back(LoHalf);
2294 Worklist.push_back(HiHalf);
2297 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2298 MachineInstr *Inst) const {
2299 MachineBasicBlock &MBB = *Inst->getParent();
2300 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2302 MachineBasicBlock::iterator MII = Inst;
2303 DebugLoc DL = Inst->getDebugLoc();
2305 MachineOperand &Dest = Inst->getOperand(0);
2306 MachineOperand &Src = Inst->getOperand(1);
2308 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2309 const TargetRegisterClass *SrcRC = Src.isReg() ?
2310 MRI.getRegClass(Src.getReg()) :
2311 &AMDGPU::SGPR_32RegClass;
2313 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2314 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2316 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2318 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2319 AMDGPU::sub0, SrcSubRC);
2320 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2321 AMDGPU::sub1, SrcSubRC);
2323 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2324 .addOperand(SrcRegSub0)
2327 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2328 .addOperand(SrcRegSub1)
2331 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2333 Worklist.push_back(First);
2334 Worklist.push_back(Second);
2337 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2338 MachineInstr *Inst) const {
2339 MachineBasicBlock &MBB = *Inst->getParent();
2340 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2341 MachineBasicBlock::iterator MII = Inst;
2342 DebugLoc DL = Inst->getDebugLoc();
2344 MachineOperand &Dest = Inst->getOperand(0);
2345 uint32_t Imm = Inst->getOperand(2).getImm();
2346 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2347 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2351 // Only sext_inreg cases handled.
2352 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2357 if (BitWidth < 32) {
2358 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2359 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2360 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2362 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2363 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2367 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2371 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2373 .addImm(AMDGPU::sub0)
2375 .addImm(AMDGPU::sub1);
2377 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2381 MachineOperand &Src = Inst->getOperand(1);
2382 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2383 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2385 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2387 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2389 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2390 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2391 .addImm(AMDGPU::sub0)
2393 .addImm(AMDGPU::sub1);
2395 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2398 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2399 MachineInstr *Inst) const {
2400 // Add the implict and explicit register definitions.
2401 if (NewDesc.ImplicitUses) {
2402 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2403 unsigned Reg = NewDesc.ImplicitUses[i];
2404 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2408 if (NewDesc.ImplicitDefs) {
2409 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2410 unsigned Reg = NewDesc.ImplicitDefs[i];
2411 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2416 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2417 int OpIndices[3]) const {
2418 const MCInstrDesc &Desc = get(MI->getOpcode());
2420 // Find the one SGPR operand we are allowed to use.
2421 unsigned SGPRReg = AMDGPU::NoRegister;
2423 // First we need to consider the instruction's operand requirements before
2424 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2425 // of VCC, but we are still bound by the constant bus requirement to only use
2428 // If the operand's class is an SGPR, we can never move it.
2430 for (const MachineOperand &MO : MI->implicit_operands()) {
2431 // We only care about reads.
2435 if (MO.getReg() == AMDGPU::VCC)
2438 if (MO.getReg() == AMDGPU::FLAT_SCR)
2439 return AMDGPU::FLAT_SCR;
2442 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2443 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2445 for (unsigned i = 0; i < 3; ++i) {
2446 int Idx = OpIndices[i];
2450 const MachineOperand &MO = MI->getOperand(Idx);
2451 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2452 SGPRReg = MO.getReg();
2454 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2455 UsedSGPRs[i] = MO.getReg();
2458 if (SGPRReg != AMDGPU::NoRegister)
2461 // We don't have a required SGPR operand, so we have a bit more freedom in
2462 // selecting operands to move.
2464 // Try to select the most used SGPR. If an SGPR is equal to one of the
2465 // others, we choose that.
2468 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2469 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2471 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2472 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2473 SGPRReg = UsedSGPRs[0];
2476 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2477 if (UsedSGPRs[1] == UsedSGPRs[2])
2478 SGPRReg = UsedSGPRs[1];
2484 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2485 MachineBasicBlock *MBB,
2486 MachineBasicBlock::iterator I,
2488 unsigned Address, unsigned OffsetReg) const {
2489 const DebugLoc &DL = MBB->findDebugLoc(I);
2490 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2491 getIndirectIndexBegin(*MBB->getParent()));
2493 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2494 .addReg(IndirectBaseReg, RegState::Define)
2495 .addOperand(I->getOperand(0))
2496 .addReg(IndirectBaseReg)
2502 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2503 MachineBasicBlock *MBB,
2504 MachineBasicBlock::iterator I,
2506 unsigned Address, unsigned OffsetReg) const {
2507 const DebugLoc &DL = MBB->findDebugLoc(I);
2508 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2509 getIndirectIndexBegin(*MBB->getParent()));
2511 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2512 .addOperand(I->getOperand(0))
2513 .addOperand(I->getOperand(1))
2514 .addReg(IndirectBaseReg)
2520 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2521 const MachineFunction &MF) const {
2522 int End = getIndirectIndexEnd(MF);
2523 int Begin = getIndirectIndexBegin(MF);
2529 for (int Index = Begin; Index <= End; ++Index)
2530 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2532 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2533 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2535 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2536 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2538 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2539 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2541 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2542 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2544 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2545 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2548 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2549 unsigned OperandName) const {
2550 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2554 return &MI.getOperand(Idx);
2557 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2558 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2559 if (ST.isAmdHsaOS())
2560 RsrcDataFormat |= (1ULL << 56);
2562 return RsrcDataFormat;