1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCInstrDesc.h"
27 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
28 : AMDGPUInstrInfo(st),
31 //===----------------------------------------------------------------------===//
32 // TargetInstrInfo callbacks
33 //===----------------------------------------------------------------------===//
35 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
36 unsigned &BaseReg, unsigned &Offset,
37 const TargetRegisterInfo *TRI) const {
38 unsigned Opc = LdSt->getOpcode();
40 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
41 AMDGPU::OpName::offset);
43 // Normal, single offset LDS instruction.
44 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
45 AMDGPU::OpName::addr);
47 BaseReg = AddrReg->getReg();
48 Offset = OffsetImm->getImm();
52 // The 2 offset instructions use offset0 and offset1 instead. We can treat
53 // these as a load with a single offset if the 2 offsets are consecutive. We
54 // will use this for some partially aligned loads.
55 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
56 AMDGPU::OpName::offset0);
57 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
58 AMDGPU::OpName::offset1);
60 uint8_t Offset0 = Offset0Imm->getImm();
61 uint8_t Offset1 = Offset1Imm->getImm();
62 assert(Offset1 > Offset0);
64 if (Offset1 - Offset0 == 1) {
65 // Each of these offsets is in element sized units, so we need to convert
66 // to bytes of the individual reads.
70 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
72 assert(LdSt->mayStore());
73 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
74 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
77 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
78 AMDGPU::OpName::addr);
79 BaseReg = AddrReg->getReg();
80 Offset = EltSize * Offset0;
87 if (isMUBUF(Opc) || isMTBUF(Opc)) {
88 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
91 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
92 AMDGPU::OpName::vaddr);
96 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
97 AMDGPU::OpName::offset);
98 BaseReg = AddrReg->getReg();
99 Offset = OffsetImm->getImm();
104 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
105 AMDGPU::OpName::offset);
109 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
110 AMDGPU::OpName::sbase);
111 BaseReg = SBaseReg->getReg();
112 Offset = OffsetImm->getImm();
120 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MI, DebugLoc DL,
122 unsigned DestReg, unsigned SrcReg,
123 bool KillSrc) const {
125 // If we are trying to copy to or from SCC, there is a bug somewhere else in
126 // the backend. While it may be theoretically possible to do this, it should
127 // never be necessary.
128 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
130 static const int16_t Sub0_15[] = {
131 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
132 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
133 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
134 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
137 static const int16_t Sub0_7[] = {
138 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
139 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
142 static const int16_t Sub0_3[] = {
143 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
146 static const int16_t Sub0_2[] = {
147 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
150 static const int16_t Sub0_1[] = {
151 AMDGPU::sub0, AMDGPU::sub1, 0
155 const int16_t *SubIndices;
157 if (AMDGPU::M0 == DestReg) {
158 // Check if M0 isn't already set to this value
159 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
160 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
162 if (!I->definesRegister(AMDGPU::M0))
165 unsigned Opc = I->getOpcode();
166 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
169 if (!I->readsRegister(SrcReg))
172 // The copy isn't necessary
177 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
178 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
179 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
180 .addReg(SrcReg, getKillRegState(KillSrc));
183 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
184 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
185 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
186 .addReg(SrcReg, getKillRegState(KillSrc));
189 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
190 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
191 Opcode = AMDGPU::S_MOV_B32;
194 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
195 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
196 Opcode = AMDGPU::S_MOV_B32;
199 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
200 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
201 Opcode = AMDGPU::S_MOV_B32;
202 SubIndices = Sub0_15;
204 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
205 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
206 AMDGPU::SReg_32RegClass.contains(SrcReg));
207 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
208 .addReg(SrcReg, getKillRegState(KillSrc));
211 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
212 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
213 AMDGPU::SReg_64RegClass.contains(SrcReg));
214 Opcode = AMDGPU::V_MOV_B32_e32;
217 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
218 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
219 Opcode = AMDGPU::V_MOV_B32_e32;
222 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
223 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
224 AMDGPU::SReg_128RegClass.contains(SrcReg));
225 Opcode = AMDGPU::V_MOV_B32_e32;
228 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
229 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
230 AMDGPU::SReg_256RegClass.contains(SrcReg));
231 Opcode = AMDGPU::V_MOV_B32_e32;
234 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
235 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
236 AMDGPU::SReg_512RegClass.contains(SrcReg));
237 Opcode = AMDGPU::V_MOV_B32_e32;
238 SubIndices = Sub0_15;
241 llvm_unreachable("Can't copy register!");
244 while (unsigned SubIdx = *SubIndices++) {
245 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
246 get(Opcode), RI.getSubReg(DestReg, SubIdx));
248 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
251 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
255 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
258 // Try to map original to commuted opcode
259 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
262 // Try to map commuted to original opcode
263 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
269 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
270 MachineBasicBlock::iterator MI,
271 unsigned SrcReg, bool isKill,
273 const TargetRegisterClass *RC,
274 const TargetRegisterInfo *TRI) const {
275 MachineFunction *MF = MBB.getParent();
276 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
277 MachineRegisterInfo &MRI = MF->getRegInfo();
278 DebugLoc DL = MBB.findDebugLoc(MI);
279 unsigned KillFlag = isKill ? RegState::Kill : 0;
281 if (RI.hasVGPRs(RC)) {
282 LLVMContext &Ctx = MF->getFunction()->getContext();
283 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
284 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
286 } else if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
287 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF);
288 unsigned TgtReg = MFI->SpillTracker.LaneVGPR;
290 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), TgtReg)
291 .addReg(SrcReg, KillFlag)
293 MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg, Lane);
294 } else if (RI.isSGPRClass(RC)) {
295 // We are only allowed to create one new instruction when spilling
296 // registers, so we need to use pseudo instruction for vector
299 // Reserve a spot in the spill tracker for each sub-register of
300 // the vector register.
301 unsigned NumSubRegs = RC->getSize() / 4;
302 unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MF, NumSubRegs);
303 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
307 switch (RC->getSize() * 8) {
308 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
309 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
310 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
311 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
312 default: llvm_unreachable("Cannot spill register class");
315 BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
319 llvm_unreachable("VGPR spilling not supported");
323 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
324 MachineBasicBlock::iterator MI,
325 unsigned DestReg, int FrameIndex,
326 const TargetRegisterClass *RC,
327 const TargetRegisterInfo *TRI) const {
328 MachineFunction *MF = MBB.getParent();
329 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
330 DebugLoc DL = MBB.findDebugLoc(MI);
332 if (RI.hasVGPRs(RC)) {
333 LLVMContext &Ctx = MF->getFunction()->getContext();
334 Ctx.emitError("SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!");
335 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
337 } else if (RI.isSGPRClass(RC)){
339 switch(RC->getSize() * 8) {
340 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
341 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
342 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
343 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
344 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
345 default: llvm_unreachable("Cannot spill register class");
348 SIMachineFunctionInfo::SpilledReg Spill =
349 MFI->SpillTracker.getSpilledReg(FrameIndex);
351 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
355 llvm_unreachable("VGPR spilling not supported");
359 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
362 case AMDGPU::SI_SPILL_S512_SAVE:
363 case AMDGPU::SI_SPILL_S512_RESTORE:
365 case AMDGPU::SI_SPILL_S256_SAVE:
366 case AMDGPU::SI_SPILL_S256_RESTORE:
368 case AMDGPU::SI_SPILL_S128_SAVE:
369 case AMDGPU::SI_SPILL_S128_RESTORE:
371 case AMDGPU::SI_SPILL_S64_SAVE:
372 case AMDGPU::SI_SPILL_S64_RESTORE:
374 case AMDGPU::SI_SPILL_S32_RESTORE:
376 default: llvm_unreachable("Invalid spill opcode");
380 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
389 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
394 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
395 SIMachineFunctionInfo *MFI =
396 MI->getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
397 MachineBasicBlock &MBB = *MI->getParent();
398 DebugLoc DL = MBB.findDebugLoc(MI);
399 switch (MI->getOpcode()) {
400 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
402 // SGPR register spill
403 case AMDGPU::SI_SPILL_S512_SAVE:
404 case AMDGPU::SI_SPILL_S256_SAVE:
405 case AMDGPU::SI_SPILL_S128_SAVE:
406 case AMDGPU::SI_SPILL_S64_SAVE: {
407 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
408 unsigned FrameIndex = MI->getOperand(2).getImm();
410 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
411 SIMachineFunctionInfo::SpilledReg Spill;
412 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
413 &AMDGPU::SGPR_32RegClass, i);
414 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
416 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
417 MI->getOperand(0).getReg())
419 .addImm(Spill.Lane + i);
421 MI->eraseFromParent();
425 // SGPR register restore
426 case AMDGPU::SI_SPILL_S512_RESTORE:
427 case AMDGPU::SI_SPILL_S256_RESTORE:
428 case AMDGPU::SI_SPILL_S128_RESTORE:
429 case AMDGPU::SI_SPILL_S64_RESTORE:
430 case AMDGPU::SI_SPILL_S32_RESTORE: {
431 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
433 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
434 SIMachineFunctionInfo::SpilledReg Spill;
435 unsigned FrameIndex = MI->getOperand(2).getImm();
436 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
437 &AMDGPU::SGPR_32RegClass, i);
438 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
440 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
441 .addReg(MI->getOperand(1).getReg())
442 .addImm(Spill.Lane + i);
445 MI->eraseFromParent();
448 case AMDGPU::SI_CONSTDATA_PTR: {
449 unsigned Reg = MI->getOperand(0).getReg();
450 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
451 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
453 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
455 // Add 32-bit offset from this instruction to the start of the constant data.
456 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_I32), RegLo)
458 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
459 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
460 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
463 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
464 .addReg(AMDGPU::SCC, RegState::Implicit);
465 MI->eraseFromParent();
472 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
475 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
478 // Make sure it s legal to commute operands for VOP2.
479 if (isVOP2(MI->getOpcode()) &&
480 (!isOperandLegal(MI, 1, &MI->getOperand(2)) ||
481 !isOperandLegal(MI, 2, &MI->getOperand(1))))
484 if (!MI->getOperand(2).isReg()) {
485 // XXX: Commute instructions with FPImm operands
486 if (NewMI || MI->getOperand(2).isFPImm() ||
487 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
491 // XXX: Commute VOP3 instructions with abs and neg set .
492 const MachineOperand *Abs = getNamedOperand(*MI, AMDGPU::OpName::abs);
493 const MachineOperand *Neg = getNamedOperand(*MI, AMDGPU::OpName::neg);
494 const MachineOperand *Src0Mods = getNamedOperand(*MI,
495 AMDGPU::OpName::src0_modifiers);
496 const MachineOperand *Src1Mods = getNamedOperand(*MI,
497 AMDGPU::OpName::src1_modifiers);
498 const MachineOperand *Src2Mods = getNamedOperand(*MI,
499 AMDGPU::OpName::src2_modifiers);
501 if ((Abs && Abs->getImm()) || (Neg && Neg->getImm()) ||
502 (Src0Mods && Src0Mods->getImm()) || (Src1Mods && Src1Mods->getImm()) ||
503 (Src2Mods && Src2Mods->getImm()))
506 unsigned Reg = MI->getOperand(1).getReg();
507 unsigned SubReg = MI->getOperand(1).getSubReg();
508 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
509 MI->getOperand(2).ChangeToRegister(Reg, false);
510 MI->getOperand(2).setSubReg(SubReg);
512 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
516 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
521 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
522 MachineBasicBlock::iterator I,
524 unsigned SrcReg) const {
525 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
526 DstReg) .addReg(SrcReg);
529 bool SIInstrInfo::isMov(unsigned Opcode) const {
531 default: return false;
532 case AMDGPU::S_MOV_B32:
533 case AMDGPU::S_MOV_B64:
534 case AMDGPU::V_MOV_B32_e32:
535 case AMDGPU::V_MOV_B32_e64:
541 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
542 return RC != &AMDGPU::EXECRegRegClass;
546 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
547 AliasAnalysis *AA) const {
548 switch(MI->getOpcode()) {
549 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
550 case AMDGPU::S_MOV_B32:
551 case AMDGPU::S_MOV_B64:
552 case AMDGPU::V_MOV_B32_e32:
553 return MI->getOperand(1).isImm();
559 // Helper function generated by tablegen. We are wrapping this with
560 // an SIInstrInfo function that returns bool rather than int.
561 int isDS(uint16_t Opcode);
565 bool SIInstrInfo::isDS(uint16_t Opcode) const {
566 return ::AMDGPU::isDS(Opcode) != -1;
569 bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
570 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
573 bool SIInstrInfo::isSMRD(uint16_t Opcode) const {
574 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
577 bool SIInstrInfo::isMUBUF(uint16_t Opcode) const {
578 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
581 bool SIInstrInfo::isMTBUF(uint16_t Opcode) const {
582 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
585 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
586 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
589 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
590 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
593 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
594 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
597 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
598 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
601 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
602 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
605 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
606 int32_t Val = Imm.getSExtValue();
607 if (Val >= -16 && Val <= 64)
610 // The actual type of the operand does not seem to matter as long
611 // as the bits match one of the inline immediate values. For example:
613 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
614 // so it is a legal inline immediate.
616 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
617 // floating-point, so it is a legal inline immediate.
619 return (APInt::floatToBits(0.0f) == Imm) ||
620 (APInt::floatToBits(1.0f) == Imm) ||
621 (APInt::floatToBits(-1.0f) == Imm) ||
622 (APInt::floatToBits(0.5f) == Imm) ||
623 (APInt::floatToBits(-0.5f) == Imm) ||
624 (APInt::floatToBits(2.0f) == Imm) ||
625 (APInt::floatToBits(-2.0f) == Imm) ||
626 (APInt::floatToBits(4.0f) == Imm) ||
627 (APInt::floatToBits(-4.0f) == Imm);
630 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
632 return isInlineConstant(APInt(32, MO.getImm(), true));
635 APFloat FpImm = MO.getFPImm()->getValueAPF();
636 return isInlineConstant(FpImm.bitcastToAPInt());
642 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
643 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
646 static bool compareMachineOp(const MachineOperand &Op0,
647 const MachineOperand &Op1) {
648 if (Op0.getType() != Op1.getType())
651 switch (Op0.getType()) {
652 case MachineOperand::MO_Register:
653 return Op0.getReg() == Op1.getReg();
654 case MachineOperand::MO_Immediate:
655 return Op0.getImm() == Op1.getImm();
656 case MachineOperand::MO_FPImmediate:
657 return Op0.getFPImm() == Op1.getFPImm();
659 llvm_unreachable("Didn't expect to be comparing these operand types");
663 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
664 const MachineOperand &MO) const {
665 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
667 assert(MO.isImm() || MO.isFPImm());
669 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
672 if (OpInfo.RegClass < 0)
675 return RI.regClassCanUseImmediate(OpInfo.RegClass);
678 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
679 return AMDGPU::getVOPe32(Opcode) != -1;
682 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
683 // The src0_modifier operand is present on all instructions
684 // that have modifiers.
686 return AMDGPU::getNamedOperandIdx(Opcode,
687 AMDGPU::OpName::src0_modifiers) != -1;
690 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
691 StringRef &ErrInfo) const {
692 uint16_t Opcode = MI->getOpcode();
693 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
694 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
695 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
697 // Make sure the number of operands is correct.
698 const MCInstrDesc &Desc = get(Opcode);
699 if (!Desc.isVariadic() &&
700 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
701 ErrInfo = "Instruction has wrong number of operands.";
705 // Make sure the register classes are correct
706 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
707 switch (Desc.OpInfo[i].OperandType) {
708 case MCOI::OPERAND_REGISTER: {
709 int RegClass = Desc.OpInfo[i].RegClass;
710 if (!RI.regClassCanUseImmediate(RegClass) &&
711 (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) {
712 // Handle some special cases:
713 // Src0 can of VOP1, VOP2, VOPC can be an immediate no matter what
714 // the register class.
715 if (i != Src0Idx || (!isVOP1(Opcode) && !isVOP2(Opcode) &&
717 ErrInfo = "Expected register, but got immediate";
723 case MCOI::OPERAND_IMMEDIATE:
724 // Check if this operand is an immediate.
725 // FrameIndex operands will be replaced by immediates, so they are
727 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
728 !MI->getOperand(i).isFI()) {
729 ErrInfo = "Expected immediate, but got non-immediate";
737 if (!MI->getOperand(i).isReg())
740 int RegClass = Desc.OpInfo[i].RegClass;
741 if (RegClass != -1) {
742 unsigned Reg = MI->getOperand(i).getReg();
743 if (TargetRegisterInfo::isVirtualRegister(Reg))
746 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
747 if (!RC->contains(Reg)) {
748 ErrInfo = "Operand has incorrect register class.";
756 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
757 unsigned ConstantBusCount = 0;
758 unsigned SGPRUsed = AMDGPU::NoRegister;
759 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
760 const MachineOperand &MO = MI->getOperand(i);
761 if (MO.isReg() && MO.isUse() &&
762 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
764 // EXEC register uses the constant bus.
765 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
768 // SGPRs use the constant bus
769 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
771 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
772 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
773 if (SGPRUsed != MO.getReg()) {
775 SGPRUsed = MO.getReg();
779 // Literal constants use the constant bus.
780 if (isLiteralConstant(MO))
783 if (ConstantBusCount > 1) {
784 ErrInfo = "VOP* instruction uses the constant bus more than once";
789 // Verify SRC1 for VOP2 and VOPC
790 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
791 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
792 if (Src1.isImm() || Src1.isFPImm()) {
793 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
799 if (isVOP3(Opcode)) {
800 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
801 ErrInfo = "VOP3 src0 cannot be a literal constant.";
804 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
805 ErrInfo = "VOP3 src1 cannot be a literal constant.";
808 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
809 ErrInfo = "VOP3 src2 cannot be a literal constant.";
814 // Verify misc. restrictions on specific instructions.
815 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
816 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
819 const MachineOperand &Src0 = MI->getOperand(2);
820 const MachineOperand &Src1 = MI->getOperand(3);
821 const MachineOperand &Src2 = MI->getOperand(4);
822 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
823 if (!compareMachineOp(Src0, Src1) &&
824 !compareMachineOp(Src0, Src2)) {
825 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
834 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
835 switch (MI.getOpcode()) {
836 default: return AMDGPU::INSTRUCTION_LIST_END;
837 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
838 case AMDGPU::COPY: return AMDGPU::COPY;
839 case AMDGPU::PHI: return AMDGPU::PHI;
840 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
841 case AMDGPU::S_MOV_B32:
842 return MI.getOperand(1).isReg() ?
843 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
844 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
845 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
846 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
847 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
848 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
849 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
850 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
851 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
852 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
853 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
854 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
855 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
856 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
857 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
858 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
859 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
860 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
861 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
862 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
863 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
864 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
865 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
866 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
867 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
868 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
869 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
870 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
871 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
872 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
873 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
874 case AMDGPU::S_LOAD_DWORD_IMM:
875 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
876 case AMDGPU::S_LOAD_DWORDX2_IMM:
877 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
878 case AMDGPU::S_LOAD_DWORDX4_IMM:
879 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
880 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
881 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
882 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
886 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
887 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
890 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
891 unsigned OpNo) const {
892 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
893 const MCInstrDesc &Desc = get(MI.getOpcode());
894 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
895 Desc.OpInfo[OpNo].RegClass == -1)
896 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
898 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
899 return RI.getRegClass(RCID);
902 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
903 switch (MI.getOpcode()) {
905 case AMDGPU::REG_SEQUENCE:
907 case AMDGPU::INSERT_SUBREG:
908 return RI.hasVGPRs(getOpRegClass(MI, 0));
910 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
914 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
915 MachineBasicBlock::iterator I = MI;
916 MachineOperand &MO = MI->getOperand(OpIdx);
917 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
918 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
919 const TargetRegisterClass *RC = RI.getRegClass(RCID);
920 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
922 Opcode = AMDGPU::COPY;
923 } else if (RI.isSGPRClass(RC)) {
924 Opcode = AMDGPU::S_MOV_B32;
927 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
928 unsigned Reg = MRI.createVirtualRegister(VRC);
929 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
931 MO.ChangeToRegister(Reg, false);
934 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
935 MachineRegisterInfo &MRI,
936 MachineOperand &SuperReg,
937 const TargetRegisterClass *SuperRC,
939 const TargetRegisterClass *SubRC)
941 assert(SuperReg.isReg());
943 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
944 unsigned SubReg = MRI.createVirtualRegister(SubRC);
946 // Just in case the super register is itself a sub-register, copy it to a new
947 // value so we don't need to worry about merging its subreg index with the
948 // SubIdx passed to this function. The register coalescer should be able to
949 // eliminate this extra copy.
950 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
952 .addOperand(SuperReg);
954 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
956 .addReg(NewSuperReg, 0, SubIdx);
960 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
961 MachineBasicBlock::iterator MII,
962 MachineRegisterInfo &MRI,
964 const TargetRegisterClass *SuperRC,
966 const TargetRegisterClass *SubRC) const {
968 // XXX - Is there a better way to do this?
969 if (SubIdx == AMDGPU::sub0)
970 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
971 if (SubIdx == AMDGPU::sub1)
972 return MachineOperand::CreateImm(Op.getImm() >> 32);
974 llvm_unreachable("Unhandled register index for immediate");
977 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
979 return MachineOperand::CreateReg(SubReg, false);
982 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
983 MachineBasicBlock::iterator MI,
984 MachineRegisterInfo &MRI,
985 const TargetRegisterClass *RC,
986 const MachineOperand &Op) const {
987 MachineBasicBlock *MBB = MI->getParent();
988 DebugLoc DL = MI->getDebugLoc();
989 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
990 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
991 unsigned Dst = MRI.createVirtualRegister(RC);
993 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
995 .addImm(Op.getImm() & 0xFFFFFFFF);
996 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
998 .addImm(Op.getImm() >> 32);
1000 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1002 .addImm(AMDGPU::sub0)
1004 .addImm(AMDGPU::sub1);
1006 Worklist.push_back(Lo);
1007 Worklist.push_back(Hi);
1012 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1013 const MachineOperand *MO) const {
1014 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1015 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1016 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1017 const TargetRegisterClass *DefinedRC =
1018 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1020 MO = &MI->getOperand(OpIdx);
1024 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1025 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass));
1029 // Handle non-register types that are treated like immediates.
1030 assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI());
1033 // This opperand expects an immediate
1036 return RI.regClassCanUseImmediate(DefinedRC);
1039 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1040 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1042 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1043 AMDGPU::OpName::src0);
1044 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1045 AMDGPU::OpName::src1);
1046 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1047 AMDGPU::OpName::src2);
1050 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1052 if (!isOperandLegal(MI, Src0Idx))
1053 legalizeOpWithMove(MI, Src0Idx);
1056 if (isOperandLegal(MI, Src1Idx))
1059 // Usually src0 of VOP2 instructions allow more types of inputs
1060 // than src1, so try to commute the instruction to decrease our
1061 // chances of having to insert a MOV instruction to legalize src1.
1062 if (MI->isCommutable()) {
1063 if (commuteInstruction(MI))
1064 // If we are successful in commuting, then we know MI is legal, so
1069 legalizeOpWithMove(MI, Src1Idx);
1073 // XXX - Do any VOP3 instructions read VCC?
1075 if (isVOP3(MI->getOpcode())) {
1076 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
1077 unsigned SGPRReg = AMDGPU::NoRegister;
1078 for (unsigned i = 0; i < 3; ++i) {
1079 int Idx = VOP3Idx[i];
1082 MachineOperand &MO = MI->getOperand(Idx);
1085 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1086 continue; // VGPRs are legal
1088 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1090 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1091 SGPRReg = MO.getReg();
1092 // We can use one SGPR in each VOP3 instruction.
1095 } else if (!isLiteralConstant(MO)) {
1096 // If it is not a register and not a literal constant, then it must be
1097 // an inline constant which is always legal.
1100 // If we make it this far, then the operand is not legal and we must
1102 legalizeOpWithMove(MI, Idx);
1106 // Legalize REG_SEQUENCE and PHI
1107 // The register class of the operands much be the same type as the register
1108 // class of the output.
1109 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1110 MI->getOpcode() == AMDGPU::PHI) {
1111 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1112 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1113 if (!MI->getOperand(i).isReg() ||
1114 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1116 const TargetRegisterClass *OpRC =
1117 MRI.getRegClass(MI->getOperand(i).getReg());
1118 if (RI.hasVGPRs(OpRC)) {
1125 // If any of the operands are VGPR registers, then they all most be
1126 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1128 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1131 VRC = RI.getEquivalentVGPRClass(SRC);
1138 // Update all the operands so they have the same type.
1139 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1140 if (!MI->getOperand(i).isReg() ||
1141 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1143 unsigned DstReg = MRI.createVirtualRegister(RC);
1144 MachineBasicBlock *InsertBB;
1145 MachineBasicBlock::iterator Insert;
1146 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1147 InsertBB = MI->getParent();
1150 // MI is a PHI instruction.
1151 InsertBB = MI->getOperand(i + 1).getMBB();
1152 Insert = InsertBB->getFirstTerminator();
1154 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1155 get(AMDGPU::COPY), DstReg)
1156 .addOperand(MI->getOperand(i));
1157 MI->getOperand(i).setReg(DstReg);
1161 // Legalize INSERT_SUBREG
1162 // src0 must have the same register class as dst
1163 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1164 unsigned Dst = MI->getOperand(0).getReg();
1165 unsigned Src0 = MI->getOperand(1).getReg();
1166 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1167 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1168 if (DstRC != Src0RC) {
1169 MachineBasicBlock &MBB = *MI->getParent();
1170 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1171 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1173 MI->getOperand(1).setReg(NewSrc0);
1178 // Legalize MUBUF* instructions
1179 // FIXME: If we start using the non-addr64 instructions for compute, we
1180 // may need to legalize them here.
1182 int SRsrcIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1183 AMDGPU::OpName::srsrc);
1184 int VAddrIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1185 AMDGPU::OpName::vaddr);
1186 if (SRsrcIdx != -1 && VAddrIdx != -1) {
1187 const TargetRegisterClass *VAddrRC =
1188 RI.getRegClass(get(MI->getOpcode()).OpInfo[VAddrIdx].RegClass);
1190 if(VAddrRC->getSize() == 8 &&
1191 MRI.getRegClass(MI->getOperand(SRsrcIdx).getReg()) != VAddrRC) {
1192 // We have a MUBUF instruction that uses a 64-bit vaddr register and
1193 // srsrc has the incorrect register class. In order to fix this, we
1194 // need to extract the pointer from the resource descriptor (srsrc),
1195 // add it to the value of vadd, then store the result in the vaddr
1196 // operand. Then, we need to set the pointer field of the resource
1197 // descriptor to zero.
1199 MachineBasicBlock &MBB = *MI->getParent();
1200 MachineOperand &SRsrcOp = MI->getOperand(SRsrcIdx);
1201 MachineOperand &VAddrOp = MI->getOperand(VAddrIdx);
1202 unsigned SRsrcPtrLo, SRsrcPtrHi, VAddrLo, VAddrHi;
1203 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1204 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1205 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1206 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1207 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1208 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1209 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1211 // SRsrcPtrLo = srsrc:sub0
1212 SRsrcPtrLo = buildExtractSubReg(MI, MRI, SRsrcOp,
1213 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1215 // SRsrcPtrHi = srsrc:sub1
1216 SRsrcPtrHi = buildExtractSubReg(MI, MRI, SRsrcOp,
1217 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1219 // VAddrLo = vaddr:sub0
1220 VAddrLo = buildExtractSubReg(MI, MRI, VAddrOp,
1221 &AMDGPU::VReg_64RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1223 // VAddrHi = vaddr:sub1
1224 VAddrHi = buildExtractSubReg(MI, MRI, VAddrOp,
1225 &AMDGPU::VReg_64RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1227 // NewVaddrLo = SRsrcPtrLo + VAddrLo
1228 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1232 .addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
1234 // NewVaddrHi = SRsrcPtrHi + VAddrHi
1235 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1239 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1240 .addReg(AMDGPU::VCC, RegState::Implicit);
1242 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1243 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1246 .addImm(AMDGPU::sub0)
1248 .addImm(AMDGPU::sub1);
1251 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1255 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1256 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1258 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1260 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1261 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1263 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1265 // NewSRsrc = {Zero64, SRsrcFormat}
1266 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1269 .addImm(AMDGPU::sub0_sub1)
1270 .addReg(SRsrcFormatLo)
1271 .addImm(AMDGPU::sub2)
1272 .addReg(SRsrcFormatHi)
1273 .addImm(AMDGPU::sub3);
1275 // Update the instruction to use NewVaddr
1276 MI->getOperand(VAddrIdx).setReg(NewVAddr);
1277 // Update the instruction to use NewSRsrc
1278 MI->getOperand(SRsrcIdx).setReg(NewSRsrc);
1283 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1284 MachineBasicBlock *MBB = MI->getParent();
1285 switch (MI->getOpcode()) {
1286 case AMDGPU::S_LOAD_DWORD_IMM:
1287 case AMDGPU::S_LOAD_DWORD_SGPR:
1288 case AMDGPU::S_LOAD_DWORDX2_IMM:
1289 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1290 case AMDGPU::S_LOAD_DWORDX4_IMM:
1291 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1292 unsigned NewOpcode = getVALUOp(*MI);
1296 if (MI->getOperand(2).isReg()) {
1297 RegOffset = MI->getOperand(2).getReg();
1300 assert(MI->getOperand(2).isImm());
1301 // SMRD instructions take a dword offsets and MUBUF instructions
1302 // take a byte offset.
1303 ImmOffset = MI->getOperand(2).getImm() << 2;
1304 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1305 if (isUInt<12>(ImmOffset)) {
1306 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1310 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1317 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1318 unsigned DWord0 = RegOffset;
1319 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1320 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1321 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1323 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1325 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1326 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1327 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1328 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1329 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1331 .addImm(AMDGPU::sub0)
1333 .addImm(AMDGPU::sub1)
1335 .addImm(AMDGPU::sub2)
1337 .addImm(AMDGPU::sub3);
1338 MI->setDesc(get(NewOpcode));
1339 if (MI->getOperand(2).isReg()) {
1340 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1342 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1344 MI->getOperand(1).setReg(SRsrc);
1345 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1349 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1350 SmallVector<MachineInstr *, 128> Worklist;
1351 Worklist.push_back(&TopInst);
1353 while (!Worklist.empty()) {
1354 MachineInstr *Inst = Worklist.pop_back_val();
1355 MachineBasicBlock *MBB = Inst->getParent();
1356 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1358 unsigned Opcode = Inst->getOpcode();
1359 unsigned NewOpcode = getVALUOp(*Inst);
1361 // Handle some special cases
1364 if (isSMRD(Inst->getOpcode())) {
1365 moveSMRDToVALU(Inst, MRI);
1368 case AMDGPU::S_MOV_B64: {
1369 DebugLoc DL = Inst->getDebugLoc();
1371 // If the source operand is a register we can replace this with a
1373 if (Inst->getOperand(1).isReg()) {
1374 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1375 .addOperand(Inst->getOperand(0))
1376 .addOperand(Inst->getOperand(1));
1377 Worklist.push_back(Copy);
1379 // Otherwise, we need to split this into two movs, because there is
1380 // no 64-bit VALU move instruction.
1381 unsigned Reg = Inst->getOperand(0).getReg();
1382 unsigned Dst = split64BitImm(Worklist,
1385 MRI.getRegClass(Reg),
1386 Inst->getOperand(1));
1387 MRI.replaceRegWith(Reg, Dst);
1389 Inst->eraseFromParent();
1392 case AMDGPU::S_AND_B64:
1393 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1394 Inst->eraseFromParent();
1397 case AMDGPU::S_OR_B64:
1398 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1399 Inst->eraseFromParent();
1402 case AMDGPU::S_XOR_B64:
1403 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1404 Inst->eraseFromParent();
1407 case AMDGPU::S_NOT_B64:
1408 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1409 Inst->eraseFromParent();
1412 case AMDGPU::S_BCNT1_I32_B64:
1413 splitScalar64BitBCNT(Worklist, Inst);
1414 Inst->eraseFromParent();
1417 case AMDGPU::S_BFE_U64:
1418 case AMDGPU::S_BFE_I64:
1419 case AMDGPU::S_BFM_B64:
1420 llvm_unreachable("Moving this op to VALU not implemented");
1423 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1424 // We cannot move this instruction to the VALU, so we should try to
1425 // legalize its operands instead.
1426 legalizeOperands(Inst);
1430 // Use the new VALU Opcode.
1431 const MCInstrDesc &NewDesc = get(NewOpcode);
1432 Inst->setDesc(NewDesc);
1434 // Remove any references to SCC. Vector instructions can't read from it, and
1435 // We're just about to add the implicit use / defs of VCC, and we don't want
1437 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1438 MachineOperand &Op = Inst->getOperand(i);
1439 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1440 Inst->RemoveOperand(i);
1443 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1444 // We are converting these to a BFE, so we need to add the missing
1445 // operands for the size and offset.
1446 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1447 Inst->addOperand(MachineOperand::CreateImm(0));
1448 Inst->addOperand(MachineOperand::CreateImm(Size));
1450 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1451 // The VALU version adds the second operand to the result, so insert an
1453 Inst->addOperand(MachineOperand::CreateImm(0));
1456 addDescImplicitUseDef(NewDesc, Inst);
1458 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1459 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1460 // If we need to move this to VGPRs, we need to unpack the second operand
1461 // back into the 2 separate ones for bit offset and width.
1462 assert(OffsetWidthOp.isImm() &&
1463 "Scalar BFE is only implemented for constant width and offset");
1464 uint32_t Imm = OffsetWidthOp.getImm();
1466 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1467 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1468 Inst->RemoveOperand(2); // Remove old immediate.
1469 Inst->addOperand(MachineOperand::CreateImm(Offset));
1470 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1473 // Update the destination register class.
1475 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1478 // For target instructions, getOpRegClass just returns the virtual
1479 // register class associated with the operand, so we need to find an
1480 // equivalent VGPR register class in order to move the instruction to the
1484 case AMDGPU::REG_SEQUENCE:
1485 case AMDGPU::INSERT_SUBREG:
1486 if (RI.hasVGPRs(NewDstRC))
1488 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1496 unsigned DstReg = Inst->getOperand(0).getReg();
1497 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1498 MRI.replaceRegWith(DstReg, NewDstReg);
1500 // Legalize the operands
1501 legalizeOperands(Inst);
1503 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1504 E = MRI.use_end(); I != E; ++I) {
1505 MachineInstr &UseMI = *I->getParent();
1506 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1507 Worklist.push_back(&UseMI);
1513 //===----------------------------------------------------------------------===//
1514 // Indirect addressing callbacks
1515 //===----------------------------------------------------------------------===//
1517 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1518 unsigned Channel) const {
1519 assert(Channel == 0);
1523 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1524 return &AMDGPU::VReg_32RegClass;
1527 void SIInstrInfo::splitScalar64BitUnaryOp(
1528 SmallVectorImpl<MachineInstr *> &Worklist,
1530 unsigned Opcode) const {
1531 MachineBasicBlock &MBB = *Inst->getParent();
1532 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1534 MachineOperand &Dest = Inst->getOperand(0);
1535 MachineOperand &Src0 = Inst->getOperand(1);
1536 DebugLoc DL = Inst->getDebugLoc();
1538 MachineBasicBlock::iterator MII = Inst;
1540 const MCInstrDesc &InstDesc = get(Opcode);
1541 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1542 MRI.getRegClass(Src0.getReg()) :
1543 &AMDGPU::SGPR_32RegClass;
1545 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1547 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1548 AMDGPU::sub0, Src0SubRC);
1550 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1551 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1553 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1554 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1555 .addOperand(SrcReg0Sub0);
1557 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1558 AMDGPU::sub1, Src0SubRC);
1560 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1561 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1562 .addOperand(SrcReg0Sub1);
1564 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1565 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1567 .addImm(AMDGPU::sub0)
1569 .addImm(AMDGPU::sub1);
1571 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1573 // Try to legalize the operands in case we need to swap the order to keep it
1575 Worklist.push_back(LoHalf);
1576 Worklist.push_back(HiHalf);
1579 void SIInstrInfo::splitScalar64BitBinaryOp(
1580 SmallVectorImpl<MachineInstr *> &Worklist,
1582 unsigned Opcode) const {
1583 MachineBasicBlock &MBB = *Inst->getParent();
1584 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1586 MachineOperand &Dest = Inst->getOperand(0);
1587 MachineOperand &Src0 = Inst->getOperand(1);
1588 MachineOperand &Src1 = Inst->getOperand(2);
1589 DebugLoc DL = Inst->getDebugLoc();
1591 MachineBasicBlock::iterator MII = Inst;
1593 const MCInstrDesc &InstDesc = get(Opcode);
1594 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1595 MRI.getRegClass(Src0.getReg()) :
1596 &AMDGPU::SGPR_32RegClass;
1598 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1599 const TargetRegisterClass *Src1RC = Src1.isReg() ?
1600 MRI.getRegClass(Src1.getReg()) :
1601 &AMDGPU::SGPR_32RegClass;
1603 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
1605 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1606 AMDGPU::sub0, Src0SubRC);
1607 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1608 AMDGPU::sub0, Src1SubRC);
1610 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1611 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1613 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1614 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1615 .addOperand(SrcReg0Sub0)
1616 .addOperand(SrcReg1Sub0);
1618 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1619 AMDGPU::sub1, Src0SubRC);
1620 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1621 AMDGPU::sub1, Src1SubRC);
1623 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1624 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1625 .addOperand(SrcReg0Sub1)
1626 .addOperand(SrcReg1Sub1);
1628 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1629 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1631 .addImm(AMDGPU::sub0)
1633 .addImm(AMDGPU::sub1);
1635 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1637 // Try to legalize the operands in case we need to swap the order to keep it
1639 Worklist.push_back(LoHalf);
1640 Worklist.push_back(HiHalf);
1643 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
1644 MachineInstr *Inst) const {
1645 MachineBasicBlock &MBB = *Inst->getParent();
1646 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1648 MachineBasicBlock::iterator MII = Inst;
1649 DebugLoc DL = Inst->getDebugLoc();
1651 MachineOperand &Dest = Inst->getOperand(0);
1652 MachineOperand &Src = Inst->getOperand(1);
1654 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
1655 const TargetRegisterClass *SrcRC = Src.isReg() ?
1656 MRI.getRegClass(Src.getReg()) :
1657 &AMDGPU::SGPR_32RegClass;
1659 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1660 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1662 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
1664 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1665 AMDGPU::sub0, SrcSubRC);
1666 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1667 AMDGPU::sub1, SrcSubRC);
1669 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
1670 .addOperand(SrcRegSub0)
1673 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
1674 .addOperand(SrcRegSub1)
1677 MRI.replaceRegWith(Dest.getReg(), ResultReg);
1679 Worklist.push_back(First);
1680 Worklist.push_back(Second);
1683 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
1684 MachineInstr *Inst) const {
1685 // Add the implict and explicit register definitions.
1686 if (NewDesc.ImplicitUses) {
1687 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
1688 unsigned Reg = NewDesc.ImplicitUses[i];
1689 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
1693 if (NewDesc.ImplicitDefs) {
1694 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
1695 unsigned Reg = NewDesc.ImplicitDefs[i];
1696 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
1701 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1702 MachineBasicBlock *MBB,
1703 MachineBasicBlock::iterator I,
1705 unsigned Address, unsigned OffsetReg) const {
1706 const DebugLoc &DL = MBB->findDebugLoc(I);
1707 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1708 getIndirectIndexBegin(*MBB->getParent()));
1710 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
1711 .addReg(IndirectBaseReg, RegState::Define)
1712 .addOperand(I->getOperand(0))
1713 .addReg(IndirectBaseReg)
1719 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1720 MachineBasicBlock *MBB,
1721 MachineBasicBlock::iterator I,
1723 unsigned Address, unsigned OffsetReg) const {
1724 const DebugLoc &DL = MBB->findDebugLoc(I);
1725 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1726 getIndirectIndexBegin(*MBB->getParent()));
1728 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
1729 .addOperand(I->getOperand(0))
1730 .addOperand(I->getOperand(1))
1731 .addReg(IndirectBaseReg)
1737 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1738 const MachineFunction &MF) const {
1739 int End = getIndirectIndexEnd(MF);
1740 int Begin = getIndirectIndexBegin(MF);
1746 for (int Index = Begin; Index <= End; ++Index)
1747 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1749 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
1750 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1752 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
1753 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1755 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
1756 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1758 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
1759 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1761 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
1762 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
1765 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
1766 unsigned OperandName) const {
1767 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
1771 return &MI.getOperand(Idx);