1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/MC/MCInstrDesc.h"
26 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
27 : AMDGPUInstrInfo(tm),
31 const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {
35 //===----------------------------------------------------------------------===//
36 // TargetInstrInfo callbacks
37 //===----------------------------------------------------------------------===//
40 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
41 MachineBasicBlock::iterator MI, DebugLoc DL,
42 unsigned DestReg, unsigned SrcReg,
45 // If we are trying to copy to or from SCC, there is a bug somewhere else in
46 // the backend. While it may be theoretically possible to do this, it should
47 // never be necessary.
48 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
50 static const int16_t Sub0_15[] = {
51 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
52 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
53 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
54 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
57 static const int16_t Sub0_7[] = {
58 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
59 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
62 static const int16_t Sub0_3[] = {
63 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
66 static const int16_t Sub0_2[] = {
67 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
70 static const int16_t Sub0_1[] = {
71 AMDGPU::sub0, AMDGPU::sub1, 0
75 const int16_t *SubIndices;
77 if (AMDGPU::M0 == DestReg) {
78 // Check if M0 isn't already set to this value
79 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
80 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
82 if (!I->definesRegister(AMDGPU::M0))
85 unsigned Opc = I->getOpcode();
86 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
89 if (!I->readsRegister(SrcReg))
92 // The copy isn't necessary
97 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
98 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
99 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
100 .addReg(SrcReg, getKillRegState(KillSrc));
103 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
104 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
105 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
106 .addReg(SrcReg, getKillRegState(KillSrc));
109 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
110 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
111 Opcode = AMDGPU::S_MOV_B32;
114 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
115 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
116 Opcode = AMDGPU::S_MOV_B32;
119 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
120 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
121 Opcode = AMDGPU::S_MOV_B32;
122 SubIndices = Sub0_15;
124 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
125 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
126 AMDGPU::SReg_32RegClass.contains(SrcReg));
127 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
128 .addReg(SrcReg, getKillRegState(KillSrc));
131 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
132 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
133 AMDGPU::SReg_64RegClass.contains(SrcReg));
134 Opcode = AMDGPU::V_MOV_B32_e32;
137 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
138 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
139 Opcode = AMDGPU::V_MOV_B32_e32;
142 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
143 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
144 AMDGPU::SReg_128RegClass.contains(SrcReg));
145 Opcode = AMDGPU::V_MOV_B32_e32;
148 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
149 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
150 AMDGPU::SReg_256RegClass.contains(SrcReg));
151 Opcode = AMDGPU::V_MOV_B32_e32;
154 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
155 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
156 AMDGPU::SReg_512RegClass.contains(SrcReg));
157 Opcode = AMDGPU::V_MOV_B32_e32;
158 SubIndices = Sub0_15;
161 llvm_unreachable("Can't copy register!");
164 while (unsigned SubIdx = *SubIndices++) {
165 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
166 get(Opcode), RI.getSubReg(DestReg, SubIdx));
168 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
171 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
175 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
178 // Try to map original to commuted opcode
179 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
182 // Try to map commuted to original opcode
183 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
189 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
190 MachineBasicBlock::iterator MI,
191 unsigned SrcReg, bool isKill,
193 const TargetRegisterClass *RC,
194 const TargetRegisterInfo *TRI) const {
195 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
196 SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
197 DebugLoc DL = MBB.findDebugLoc(MI);
198 unsigned KillFlag = isKill ? RegState::Kill : 0;
200 if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
201 unsigned Lane = MFI->SpillTracker.getNextLane(MRI);
202 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
203 MFI->SpillTracker.LaneVGPR)
204 .addReg(SrcReg, KillFlag)
206 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
209 for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
210 unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
211 BuildMI(MBB, MI, MBB.findDebugLoc(MI), get(AMDGPU::COPY), SubReg)
212 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
213 storeRegToStackSlot(MBB, MI, SubReg, isKill, FrameIndex + i,
214 &AMDGPU::SReg_32RegClass, TRI);
219 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
220 MachineBasicBlock::iterator MI,
221 unsigned DestReg, int FrameIndex,
222 const TargetRegisterClass *RC,
223 const TargetRegisterInfo *TRI) const {
224 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
225 SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
226 DebugLoc DL = MBB.findDebugLoc(MI);
227 if (TRI->getCommonSubClass(RC, &AMDGPU::SReg_32RegClass)) {
228 SIMachineFunctionInfo::SpilledReg Spill =
229 MFI->SpillTracker.getSpilledReg(FrameIndex);
231 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), DestReg)
235 for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
236 unsigned Flags = RegState::Define;
238 Flags |= RegState::Undef;
240 unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
241 loadRegFromStackSlot(MBB, MI, SubReg, FrameIndex + i,
242 &AMDGPU::SReg_32RegClass, TRI);
243 BuildMI(MBB, MI, DL, get(AMDGPU::COPY))
244 .addReg(DestReg, Flags, RI.getSubRegFromChannel(i))
250 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
253 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
254 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
257 // Cannot commute VOP2 if src0 is SGPR.
258 if (isVOP2(MI->getOpcode()) && MI->getOperand(1).isReg() &&
259 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
262 if (!MI->getOperand(2).isReg()) {
263 // XXX: Commute instructions with FPImm operands
264 if (NewMI || MI->getOperand(2).isFPImm() ||
265 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
269 // XXX: Commute VOP3 instructions with abs and neg set.
270 if (isVOP3(MI->getOpcode()) &&
271 (MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
272 AMDGPU::OpName::abs)).getImm() ||
273 MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
274 AMDGPU::OpName::neg)).getImm()))
277 unsigned Reg = MI->getOperand(1).getReg();
278 unsigned SubReg = MI->getOperand(1).getSubReg();
279 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
280 MI->getOperand(2).ChangeToRegister(Reg, false);
281 MI->getOperand(2).setSubReg(SubReg);
283 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
287 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
292 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
293 MachineBasicBlock::iterator I,
295 unsigned SrcReg) const {
296 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
297 DstReg) .addReg(SrcReg);
300 bool SIInstrInfo::isMov(unsigned Opcode) const {
302 default: return false;
303 case AMDGPU::S_MOV_B32:
304 case AMDGPU::S_MOV_B64:
305 case AMDGPU::V_MOV_B32_e32:
306 case AMDGPU::V_MOV_B32_e64:
312 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
313 return RC != &AMDGPU::EXECRegRegClass;
316 int SIInstrInfo::isMIMG(uint16_t Opcode) const {
317 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
320 int SIInstrInfo::isSMRD(uint16_t Opcode) const {
321 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
324 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
325 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
328 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
329 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
332 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
333 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
336 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
337 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
340 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
341 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
344 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
346 return MO.getImm() >= -16 && MO.getImm() <= 64;
349 return MO.getFPImm()->isExactlyValue(0.0) ||
350 MO.getFPImm()->isExactlyValue(0.5) ||
351 MO.getFPImm()->isExactlyValue(-0.5) ||
352 MO.getFPImm()->isExactlyValue(1.0) ||
353 MO.getFPImm()->isExactlyValue(-1.0) ||
354 MO.getFPImm()->isExactlyValue(2.0) ||
355 MO.getFPImm()->isExactlyValue(-2.0) ||
356 MO.getFPImm()->isExactlyValue(4.0) ||
357 MO.getFPImm()->isExactlyValue(-4.0);
362 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
363 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
366 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
367 StringRef &ErrInfo) const {
368 uint16_t Opcode = MI->getOpcode();
369 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
370 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
371 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
374 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
375 unsigned ConstantBusCount = 0;
376 unsigned SGPRUsed = AMDGPU::NoRegister;
377 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
378 const MachineOperand &MO = MI->getOperand(i);
379 if (MO.isReg() && MO.isUse() &&
380 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
382 // EXEC register uses the constant bus.
383 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
386 // SGPRs use the constant bus
387 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
389 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
390 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
391 if (SGPRUsed != MO.getReg()) {
393 SGPRUsed = MO.getReg();
397 // Literal constants use the constant bus.
398 if (isLiteralConstant(MO))
401 if (ConstantBusCount > 1) {
402 ErrInfo = "VOP* instruction uses the constant bus more than once";
407 // Verify SRC1 for VOP2 and VOPC
408 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
409 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
410 if (Src1.isImm() || Src1.isFPImm()) {
411 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
417 if (isVOP3(Opcode)) {
418 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
419 ErrInfo = "VOP3 src0 cannot be a literal constant.";
422 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
423 ErrInfo = "VOP3 src1 cannot be a literal constant.";
426 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
427 ErrInfo = "VOP3 src2 cannot be a literal constant.";
434 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
435 switch (MI.getOpcode()) {
436 default: return AMDGPU::INSTRUCTION_LIST_END;
437 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
438 case AMDGPU::COPY: return AMDGPU::COPY;
439 case AMDGPU::PHI: return AMDGPU::PHI;
440 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
441 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
442 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
443 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
444 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
445 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
446 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
447 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
448 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
449 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
453 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
454 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
457 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
458 unsigned OpNo) const {
459 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
460 const MCInstrDesc &Desc = get(MI.getOpcode());
461 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
462 Desc.OpInfo[OpNo].RegClass == -1)
463 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
465 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
466 return RI.getRegClass(RCID);
469 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
470 switch (MI.getOpcode()) {
472 case AMDGPU::REG_SEQUENCE:
473 return RI.hasVGPRs(getOpRegClass(MI, 0));
475 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
479 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
480 MachineBasicBlock::iterator I = MI;
481 MachineOperand &MO = MI->getOperand(OpIdx);
482 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
483 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
484 const TargetRegisterClass *RC = RI.getRegClass(RCID);
485 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
487 Opcode = AMDGPU::COPY;
488 } else if (RI.isSGPRClass(RC)) {
489 Opcode = AMDGPU::S_MOV_B32;
492 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
493 unsigned Reg = MRI.createVirtualRegister(VRC);
494 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
496 MO.ChangeToRegister(Reg, false);
499 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
500 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
501 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
502 AMDGPU::OpName::src0);
503 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
504 AMDGPU::OpName::src1);
505 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
506 AMDGPU::OpName::src2);
509 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
510 MachineOperand &Src0 = MI->getOperand(Src0Idx);
511 MachineOperand &Src1 = MI->getOperand(Src1Idx);
513 // If the instruction implicitly reads VCC, we can't have any SGPR operands,
515 bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI);
516 if (ReadsVCC && Src0.isReg() &&
517 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) {
518 legalizeOpWithMove(MI, Src0Idx);
522 if (ReadsVCC && Src1.isReg() &&
523 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
524 legalizeOpWithMove(MI, Src1Idx);
528 // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
529 // be the first operand, and there can only be one.
530 if (Src1.isImm() || Src1.isFPImm() ||
531 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
532 if (MI->isCommutable()) {
533 if (commuteInstruction(MI))
536 legalizeOpWithMove(MI, Src1Idx);
540 // XXX - Do any VOP3 instructions read VCC?
542 if (isVOP3(MI->getOpcode())) {
543 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
544 unsigned SGPRReg = AMDGPU::NoRegister;
545 for (unsigned i = 0; i < 3; ++i) {
546 int Idx = VOP3Idx[i];
549 MachineOperand &MO = MI->getOperand(Idx);
552 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
553 continue; // VGPRs are legal
555 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
557 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
558 SGPRReg = MO.getReg();
559 // We can use one SGPR in each VOP3 instruction.
562 } else if (!isLiteralConstant(MO)) {
563 // If it is not a register and not a literal constant, then it must be
564 // an inline constant which is always legal.
567 // If we make it this far, then the operand is not legal and we must
569 legalizeOpWithMove(MI, Idx);
573 // Legalize REG_SEQUENCE
574 // The register class of the operands much be the same type as the register
575 // class of the output.
576 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
577 const TargetRegisterClass *RC = NULL, *SRC = NULL, *VRC = NULL;
578 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
579 if (!MI->getOperand(i).isReg() ||
580 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
582 const TargetRegisterClass *OpRC =
583 MRI.getRegClass(MI->getOperand(i).getReg());
584 if (RI.hasVGPRs(OpRC)) {
591 // If any of the operands are VGPR registers, then they all most be
592 // otherwise we will create illegal VGPR->SGPR copies when legalizing
594 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
597 VRC = RI.getEquivalentVGPRClass(SRC);
604 // Update all the operands so they have the same type.
605 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
606 if (!MI->getOperand(i).isReg() ||
607 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
609 unsigned DstReg = MRI.createVirtualRegister(RC);
610 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
611 get(AMDGPU::COPY), DstReg)
612 .addOperand(MI->getOperand(i));
613 MI->getOperand(i).setReg(DstReg);
618 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
619 SmallVector<MachineInstr *, 128> Worklist;
620 Worklist.push_back(&TopInst);
622 while (!Worklist.empty()) {
623 MachineInstr *Inst = Worklist.pop_back_val();
624 unsigned NewOpcode = getVALUOp(*Inst);
625 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)
628 MachineRegisterInfo &MRI = Inst->getParent()->getParent()->getRegInfo();
630 // Use the new VALU Opcode.
631 const MCInstrDesc &NewDesc = get(NewOpcode);
632 Inst->setDesc(NewDesc);
634 // Remove any references to SCC. Vector instructions can't read from it, and
635 // We're just about to add the implicit use / defs of VCC, and we don't want
637 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
638 MachineOperand &Op = Inst->getOperand(i);
639 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
640 Inst->RemoveOperand(i);
643 // Add the implict and explicit register definitions.
644 if (NewDesc.ImplicitUses) {
645 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
646 unsigned Reg = NewDesc.ImplicitUses[i];
647 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
651 if (NewDesc.ImplicitDefs) {
652 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
653 unsigned Reg = NewDesc.ImplicitDefs[i];
654 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
658 legalizeOperands(Inst);
660 // Update the destination register class.
661 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
663 switch (Inst->getOpcode()) {
664 // For target instructions, getOpRegClass just returns the virtual
665 // register class associated with the operand, so we need to find an
666 // equivalent VGPR register class in order to move the instruction to the
670 case AMDGPU::REG_SEQUENCE:
671 if (RI.hasVGPRs(NewDstRC))
673 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
681 unsigned DstReg = Inst->getOperand(0).getReg();
682 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
683 MRI.replaceRegWith(DstReg, NewDstReg);
685 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
686 E = MRI.use_end(); I != E; ++I) {
687 MachineInstr &UseMI = *I;
688 if (!canReadVGPR(UseMI, I.getOperandNo())) {
689 Worklist.push_back(&UseMI);
695 //===----------------------------------------------------------------------===//
696 // Indirect addressing callbacks
697 //===----------------------------------------------------------------------===//
699 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
700 unsigned Channel) const {
701 assert(Channel == 0);
705 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
706 return &AMDGPU::VReg_32RegClass;
709 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
710 MachineBasicBlock *MBB,
711 MachineBasicBlock::iterator I,
713 unsigned Address, unsigned OffsetReg) const {
714 const DebugLoc &DL = MBB->findDebugLoc(I);
715 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
716 getIndirectIndexBegin(*MBB->getParent()));
718 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
719 .addReg(IndirectBaseReg, RegState::Define)
720 .addOperand(I->getOperand(0))
721 .addReg(IndirectBaseReg)
727 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
728 MachineBasicBlock *MBB,
729 MachineBasicBlock::iterator I,
731 unsigned Address, unsigned OffsetReg) const {
732 const DebugLoc &DL = MBB->findDebugLoc(I);
733 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
734 getIndirectIndexBegin(*MBB->getParent()));
736 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
737 .addOperand(I->getOperand(0))
738 .addOperand(I->getOperand(1))
739 .addReg(IndirectBaseReg)
745 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
746 const MachineFunction &MF) const {
747 int End = getIndirectIndexEnd(MF);
748 int Begin = getIndirectIndexBegin(MF);
754 for (int Index = Begin; Index <= End; ++Index)
755 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
757 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
758 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
760 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
761 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
763 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
764 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
766 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
767 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
769 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
770 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));