1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI(st) {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
79 int64_t &Offset1) const {
80 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
83 unsigned Opc0 = Load0->getMachineOpcode();
84 unsigned Opc1 = Load1->getMachineOpcode();
86 // Make sure both are actually loads.
87 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
90 if (isDS(Opc0) && isDS(Opc1)) {
92 // FIXME: Handle this case:
93 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
97 if (Load0->getOperand(1) != Load1->getOperand(1))
101 if (findChainOperand(Load0) != findChainOperand(Load1))
104 // Skip read2 / write2 variants for simplicity.
105 // TODO: We should report true if the used offsets are adjacent (excluded
107 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
108 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
111 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
112 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
116 if (isSMRD(Opc0) && isSMRD(Opc1)) {
117 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
120 if (Load0->getOperand(0) != Load1->getOperand(0))
124 if (findChainOperand(Load0) != findChainOperand(Load1))
127 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
128 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
132 // MUBUF and MTBUF can access the same addresses.
133 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
135 // MUBUF and MTBUF have vaddr at different indices.
136 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
137 findChainOperand(Load0) != findChainOperand(Load1) ||
138 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
139 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
142 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
143 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
145 if (OffIdx0 == -1 || OffIdx1 == -1)
148 // getNamedOperandIdx returns the index for MachineInstrs. Since they
149 // inlcude the output in the operand list, but SDNodes don't, we need to
150 // subtract the index by one.
154 SDValue Off0 = Load0->getOperand(OffIdx0);
155 SDValue Off1 = Load1->getOperand(OffIdx1);
157 // The offset might be a FrameIndexSDNode.
158 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
161 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
162 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
169 static bool isStride64(unsigned Opc) {
171 case AMDGPU::DS_READ2ST64_B32:
172 case AMDGPU::DS_READ2ST64_B64:
173 case AMDGPU::DS_WRITE2ST64_B32:
174 case AMDGPU::DS_WRITE2ST64_B64:
181 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
182 unsigned &BaseReg, unsigned &Offset,
183 const TargetRegisterInfo *TRI) const {
184 unsigned Opc = LdSt->getOpcode();
186 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
187 AMDGPU::OpName::offset);
189 // Normal, single offset LDS instruction.
190 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
191 AMDGPU::OpName::addr);
193 BaseReg = AddrReg->getReg();
194 Offset = OffsetImm->getImm();
198 // The 2 offset instructions use offset0 and offset1 instead. We can treat
199 // these as a load with a single offset if the 2 offsets are consecutive. We
200 // will use this for some partially aligned loads.
201 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
202 AMDGPU::OpName::offset0);
203 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
204 AMDGPU::OpName::offset1);
206 uint8_t Offset0 = Offset0Imm->getImm();
207 uint8_t Offset1 = Offset1Imm->getImm();
208 assert(Offset1 > Offset0);
210 if (Offset1 - Offset0 == 1) {
211 // Each of these offsets is in element sized units, so we need to convert
212 // to bytes of the individual reads.
216 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
218 assert(LdSt->mayStore());
219 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
220 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
226 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
227 AMDGPU::OpName::addr);
228 BaseReg = AddrReg->getReg();
229 Offset = EltSize * Offset0;
236 if (isMUBUF(Opc) || isMTBUF(Opc)) {
237 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
240 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
241 AMDGPU::OpName::vaddr);
245 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
246 AMDGPU::OpName::offset);
247 BaseReg = AddrReg->getReg();
248 Offset = OffsetImm->getImm();
253 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
254 AMDGPU::OpName::offset);
258 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
259 AMDGPU::OpName::sbase);
260 BaseReg = SBaseReg->getReg();
261 Offset = OffsetImm->getImm();
268 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
269 MachineInstr *SecondLdSt,
270 unsigned NumLoads) const {
271 unsigned Opc0 = FirstLdSt->getOpcode();
272 unsigned Opc1 = SecondLdSt->getOpcode();
274 // TODO: This needs finer tuning
278 if (isDS(Opc0) && isDS(Opc1))
281 if (isSMRD(Opc0) && isSMRD(Opc1))
284 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
291 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
292 MachineBasicBlock::iterator MI, DebugLoc DL,
293 unsigned DestReg, unsigned SrcReg,
294 bool KillSrc) const {
296 // If we are trying to copy to or from SCC, there is a bug somewhere else in
297 // the backend. While it may be theoretically possible to do this, it should
298 // never be necessary.
299 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
301 static const int16_t Sub0_15[] = {
302 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
303 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
304 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
305 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
308 static const int16_t Sub0_7[] = {
309 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
310 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
313 static const int16_t Sub0_3[] = {
314 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
317 static const int16_t Sub0_2[] = {
318 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
321 static const int16_t Sub0_1[] = {
322 AMDGPU::sub0, AMDGPU::sub1, 0
326 const int16_t *SubIndices;
328 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
329 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
330 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
331 .addReg(SrcReg, getKillRegState(KillSrc));
334 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
335 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
336 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
337 .addReg(SrcReg, getKillRegState(KillSrc));
340 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
341 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
342 Opcode = AMDGPU::S_MOV_B32;
345 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
346 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
347 Opcode = AMDGPU::S_MOV_B32;
350 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
351 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
352 Opcode = AMDGPU::S_MOV_B32;
353 SubIndices = Sub0_15;
355 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
356 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
357 AMDGPU::SReg_32RegClass.contains(SrcReg));
358 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
359 .addReg(SrcReg, getKillRegState(KillSrc));
362 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
363 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
364 AMDGPU::SReg_64RegClass.contains(SrcReg));
365 Opcode = AMDGPU::V_MOV_B32_e32;
368 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
369 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
370 Opcode = AMDGPU::V_MOV_B32_e32;
373 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
374 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
375 AMDGPU::SReg_128RegClass.contains(SrcReg));
376 Opcode = AMDGPU::V_MOV_B32_e32;
379 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
380 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
381 AMDGPU::SReg_256RegClass.contains(SrcReg));
382 Opcode = AMDGPU::V_MOV_B32_e32;
385 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
386 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
387 AMDGPU::SReg_512RegClass.contains(SrcReg));
388 Opcode = AMDGPU::V_MOV_B32_e32;
389 SubIndices = Sub0_15;
392 llvm_unreachable("Can't copy register!");
395 while (unsigned SubIdx = *SubIndices++) {
396 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
397 get(Opcode), RI.getSubReg(DestReg, SubIdx));
399 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
402 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
406 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
409 // Try to map original to commuted opcode
410 NewOpc = AMDGPU::getCommuteRev(Opcode);
411 // Check if the commuted (REV) opcode exists on the target.
412 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
415 // Try to map commuted to original opcode
416 NewOpc = AMDGPU::getCommuteOrig(Opcode);
417 // Check if the original (non-REV) opcode exists on the target.
418 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
424 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
426 if (DstRC->getSize() == 4) {
427 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
428 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
429 return AMDGPU::S_MOV_B64;
430 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
431 return AMDGPU::V_MOV_B64_PSEUDO;
436 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
437 MachineBasicBlock::iterator MI,
438 unsigned SrcReg, bool isKill,
440 const TargetRegisterClass *RC,
441 const TargetRegisterInfo *TRI) const {
442 MachineFunction *MF = MBB.getParent();
443 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
444 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
445 DebugLoc DL = MBB.findDebugLoc(MI);
448 if (RI.isSGPRClass(RC)) {
449 // We are only allowed to create one new instruction when spilling
450 // registers, so we need to use pseudo instruction for spilling
452 switch (RC->getSize() * 8) {
453 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
454 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
455 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
456 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
457 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
459 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
460 MFI->setHasSpilledVGPRs();
462 switch(RC->getSize() * 8) {
463 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
464 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
465 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
466 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
467 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
468 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
473 FrameInfo->setObjectAlignment(FrameIndex, 4);
474 BuildMI(MBB, MI, DL, get(Opcode))
476 .addFrameIndex(FrameIndex)
477 // Place-holder registers, these will be filled in by
478 // SIPrepareScratchRegs.
479 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
480 .addReg(AMDGPU::SGPR0, RegState::Undef);
482 LLVMContext &Ctx = MF->getFunction()->getContext();
483 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
485 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
490 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
491 MachineBasicBlock::iterator MI,
492 unsigned DestReg, int FrameIndex,
493 const TargetRegisterClass *RC,
494 const TargetRegisterInfo *TRI) const {
495 MachineFunction *MF = MBB.getParent();
496 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
497 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
498 DebugLoc DL = MBB.findDebugLoc(MI);
501 if (RI.isSGPRClass(RC)){
502 switch(RC->getSize() * 8) {
503 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
504 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
505 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
506 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
507 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
509 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
510 switch(RC->getSize() * 8) {
511 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
512 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
513 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
514 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
515 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
516 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
521 FrameInfo->setObjectAlignment(FrameIndex, 4);
522 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
523 .addFrameIndex(FrameIndex)
524 // Place-holder registers, these will be filled in by
525 // SIPrepareScratchRegs.
526 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
527 .addReg(AMDGPU::SGPR0, RegState::Undef);
530 LLVMContext &Ctx = MF->getFunction()->getContext();
531 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
532 " restore register");
533 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
537 /// \param @Offset Offset in bytes of the FrameIndex being spilled
538 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
539 MachineBasicBlock::iterator MI,
540 RegScavenger *RS, unsigned TmpReg,
541 unsigned FrameOffset,
542 unsigned Size) const {
543 MachineFunction *MF = MBB.getParent();
544 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
545 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
546 const SIRegisterInfo *TRI =
547 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
548 DebugLoc DL = MBB.findDebugLoc(MI);
549 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
550 unsigned WavefrontSize = ST.getWavefrontSize();
552 unsigned TIDReg = MFI->getTIDReg();
553 if (!MFI->hasCalculatedTID()) {
554 MachineBasicBlock &Entry = MBB.getParent()->front();
555 MachineBasicBlock::iterator Insert = Entry.front();
556 DebugLoc DL = Insert->getDebugLoc();
558 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
559 if (TIDReg == AMDGPU::NoRegister)
563 if (MFI->getShaderType() == ShaderType::COMPUTE &&
564 WorkGroupSize > WavefrontSize) {
566 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
567 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
568 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
569 unsigned InputPtrReg =
570 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
571 static const unsigned TIDIGRegs[3] = {
572 TIDIGXReg, TIDIGYReg, TIDIGZReg
574 for (unsigned Reg : TIDIGRegs) {
575 if (!Entry.isLiveIn(Reg))
576 Entry.addLiveIn(Reg);
579 RS->enterBasicBlock(&Entry);
580 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
581 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
582 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
584 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
585 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
587 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
589 // NGROUPS.X * NGROUPS.Y
590 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
593 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
594 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
597 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
598 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
602 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
603 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
608 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
613 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
619 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
623 MFI->setTIDReg(TIDReg);
626 // Add FrameIndex to LDS offset
627 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
628 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
635 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
644 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
649 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
650 MachineBasicBlock &MBB = *MI->getParent();
651 DebugLoc DL = MBB.findDebugLoc(MI);
652 switch (MI->getOpcode()) {
653 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
655 case AMDGPU::SI_CONSTDATA_PTR: {
656 unsigned Reg = MI->getOperand(0).getReg();
657 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
658 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
660 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
662 // Add 32-bit offset from this instruction to the start of the constant data.
663 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
665 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
666 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
667 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
670 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
671 .addReg(AMDGPU::SCC, RegState::Implicit);
672 MI->eraseFromParent();
675 case AMDGPU::SGPR_USE:
676 // This is just a placeholder for register allocation.
677 MI->eraseFromParent();
680 case AMDGPU::V_MOV_B64_PSEUDO: {
681 unsigned Dst = MI->getOperand(0).getReg();
682 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
683 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
685 const MachineOperand &SrcOp = MI->getOperand(1);
686 // FIXME: Will this work for 64-bit floating point immediates?
687 assert(!SrcOp.isFPImm());
689 APInt Imm(64, SrcOp.getImm());
690 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
691 .addImm(Imm.getLoBits(32).getZExtValue())
692 .addReg(Dst, RegState::Implicit);
693 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
694 .addImm(Imm.getHiBits(32).getZExtValue())
695 .addReg(Dst, RegState::Implicit);
697 assert(SrcOp.isReg());
698 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
699 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
700 .addReg(Dst, RegState::Implicit);
701 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
702 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
703 .addReg(Dst, RegState::Implicit);
705 MI->eraseFromParent();
712 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
715 if (MI->getNumOperands() < 3)
718 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
719 AMDGPU::OpName::src0);
720 assert(Src0Idx != -1 && "Should always have src0 operand");
722 MachineOperand &Src0 = MI->getOperand(Src0Idx);
726 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
727 AMDGPU::OpName::src1);
731 MachineOperand &Src1 = MI->getOperand(Src1Idx);
733 // Make sure it's legal to commute operands for VOP2.
734 if (isVOP2(MI->getOpcode()) &&
735 (!isOperandLegal(MI, Src0Idx, &Src1) ||
736 !isOperandLegal(MI, Src1Idx, &Src0))) {
741 // Allow commuting instructions with Imm operands.
742 if (NewMI || !Src1.isImm() ||
743 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
747 // Be sure to copy the source modifiers to the right place.
748 if (MachineOperand *Src0Mods
749 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
750 MachineOperand *Src1Mods
751 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
753 int Src0ModsVal = Src0Mods->getImm();
754 if (!Src1Mods && Src0ModsVal != 0)
757 // XXX - This assert might be a lie. It might be useful to have a neg
758 // modifier with 0.0.
759 int Src1ModsVal = Src1Mods->getImm();
760 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
762 Src1Mods->setImm(Src0ModsVal);
763 Src0Mods->setImm(Src1ModsVal);
766 unsigned Reg = Src0.getReg();
767 unsigned SubReg = Src0.getSubReg();
769 Src0.ChangeToImmediate(Src1.getImm());
771 llvm_unreachable("Should only have immediates");
773 Src1.ChangeToRegister(Reg, false);
774 Src1.setSubReg(SubReg);
776 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
780 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
785 // This needs to be implemented because the source modifiers may be inserted
786 // between the true commutable operands, and the base
787 // TargetInstrInfo::commuteInstruction uses it.
788 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
790 unsigned &SrcOpIdx2) const {
791 const MCInstrDesc &MCID = MI->getDesc();
792 if (!MCID.isCommutable())
795 unsigned Opc = MI->getOpcode();
796 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
800 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
802 if (!MI->getOperand(Src0Idx).isReg())
805 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
809 if (!MI->getOperand(Src1Idx).isReg())
812 // If any source modifiers are set, the generic instruction commuting won't
813 // understand how to copy the source modifiers.
814 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
815 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
823 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
824 MachineBasicBlock::iterator I,
826 unsigned SrcReg) const {
827 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
828 DstReg) .addReg(SrcReg);
831 bool SIInstrInfo::isMov(unsigned Opcode) const {
833 default: return false;
834 case AMDGPU::S_MOV_B32:
835 case AMDGPU::S_MOV_B64:
836 case AMDGPU::V_MOV_B32_e32:
837 case AMDGPU::V_MOV_B32_e64:
843 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
844 return RC != &AMDGPU::EXECRegRegClass;
848 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
849 AliasAnalysis *AA) const {
850 switch(MI->getOpcode()) {
851 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
852 case AMDGPU::S_MOV_B32:
853 case AMDGPU::S_MOV_B64:
854 case AMDGPU::V_MOV_B32_e32:
855 return MI->getOperand(1).isImm();
859 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
860 int WidthB, int OffsetB) {
861 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
862 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
863 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
864 return LowOffset + LowWidth <= HighOffset;
867 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
868 MachineInstr *MIb) const {
869 unsigned BaseReg0, Offset0;
870 unsigned BaseReg1, Offset1;
872 if (getLdStBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
873 getLdStBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
874 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
875 "read2 / write2 not expected here yet");
876 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
877 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
878 if (BaseReg0 == BaseReg1 &&
879 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
887 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
889 AliasAnalysis *AA) const {
890 unsigned Opc0 = MIa->getOpcode();
891 unsigned Opc1 = MIb->getOpcode();
893 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
894 "MIa must load from or modify a memory location");
895 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
896 "MIb must load from or modify a memory location");
898 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
901 // XXX - Can we relax this between address spaces?
902 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
905 // TODO: Should we check the address space from the MachineMemOperand? That
906 // would allow us to distinguish objects we know don't alias based on the
907 // underlying addres space, even if it was lowered to a different one,
908 // e.g. private accesses lowered to use MUBUF instructions on a scratch
912 return checkInstOffsetsDoNotOverlap(MIa, MIb);
914 return !isFLAT(Opc1);
917 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
918 if (isMUBUF(Opc1) || isMTBUF(Opc1))
919 return checkInstOffsetsDoNotOverlap(MIa, MIb);
921 return !isFLAT(Opc1) && !isSMRD(Opc1);
926 return checkInstOffsetsDoNotOverlap(MIa, MIb);
928 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
933 return checkInstOffsetsDoNotOverlap(MIa, MIb);
941 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
942 int64_t SVal = Imm.getSExtValue();
943 if (SVal >= -16 && SVal <= 64)
946 if (Imm.getBitWidth() == 64) {
947 uint64_t Val = Imm.getZExtValue();
948 return (DoubleToBits(0.0) == Val) ||
949 (DoubleToBits(1.0) == Val) ||
950 (DoubleToBits(-1.0) == Val) ||
951 (DoubleToBits(0.5) == Val) ||
952 (DoubleToBits(-0.5) == Val) ||
953 (DoubleToBits(2.0) == Val) ||
954 (DoubleToBits(-2.0) == Val) ||
955 (DoubleToBits(4.0) == Val) ||
956 (DoubleToBits(-4.0) == Val);
959 // The actual type of the operand does not seem to matter as long
960 // as the bits match one of the inline immediate values. For example:
962 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
963 // so it is a legal inline immediate.
965 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
966 // floating-point, so it is a legal inline immediate.
967 uint32_t Val = Imm.getZExtValue();
969 return (FloatToBits(0.0f) == Val) ||
970 (FloatToBits(1.0f) == Val) ||
971 (FloatToBits(-1.0f) == Val) ||
972 (FloatToBits(0.5f) == Val) ||
973 (FloatToBits(-0.5f) == Val) ||
974 (FloatToBits(2.0f) == Val) ||
975 (FloatToBits(-2.0f) == Val) ||
976 (FloatToBits(4.0f) == Val) ||
977 (FloatToBits(-4.0f) == Val);
980 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
982 return isInlineConstant(APInt(32, MO.getImm(), true));
987 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
988 return MO.isImm() && !isInlineConstant(MO);
991 static bool compareMachineOp(const MachineOperand &Op0,
992 const MachineOperand &Op1) {
993 if (Op0.getType() != Op1.getType())
996 switch (Op0.getType()) {
997 case MachineOperand::MO_Register:
998 return Op0.getReg() == Op1.getReg();
999 case MachineOperand::MO_Immediate:
1000 return Op0.getImm() == Op1.getImm();
1002 llvm_unreachable("Didn't expect to be comparing these operand types");
1006 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1007 const MachineOperand &MO) const {
1008 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1010 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1012 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1015 if (OpInfo.RegClass < 0)
1018 if (isLiteralConstant(MO))
1019 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1021 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1024 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) const {
1026 case AMDGPUAS::GLOBAL_ADDRESS: {
1027 // MUBUF instructions a 12-bit offset in bytes.
1028 return isUInt<12>(OffsetSize);
1030 case AMDGPUAS::CONSTANT_ADDRESS: {
1031 // SMRD instructions have an 8-bit offset in dwords on SI and
1032 // a 20-bit offset in bytes on VI.
1033 if (RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1034 return isUInt<20>(OffsetSize);
1036 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1038 case AMDGPUAS::LOCAL_ADDRESS:
1039 case AMDGPUAS::REGION_ADDRESS: {
1040 // The single offset versions have a 16-bit offset in bytes.
1041 return isUInt<16>(OffsetSize);
1043 case AMDGPUAS::PRIVATE_ADDRESS:
1044 // Indirect register addressing does not use any offsets.
1050 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1051 int Op32 = AMDGPU::getVOPe32(Opcode);
1055 return pseudoToMCOpcode(Op32) != -1;
1058 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1059 // The src0_modifier operand is present on all instructions
1060 // that have modifiers.
1062 return AMDGPU::getNamedOperandIdx(Opcode,
1063 AMDGPU::OpName::src0_modifiers) != -1;
1066 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1067 unsigned OpName) const {
1068 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1069 return Mods && Mods->getImm();
1072 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1073 const MachineOperand &MO) const {
1074 // Literal constants use the constant bus.
1075 if (isLiteralConstant(MO))
1078 if (!MO.isReg() || !MO.isUse())
1081 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1082 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1084 // FLAT_SCR is just an SGPR pair.
1085 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1088 // EXEC register uses the constant bus.
1089 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1092 // SGPRs use the constant bus
1093 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1094 (!MO.isImplicit() &&
1095 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1096 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1103 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1104 StringRef &ErrInfo) const {
1105 uint16_t Opcode = MI->getOpcode();
1106 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1107 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1108 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1109 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1111 // Make sure the number of operands is correct.
1112 const MCInstrDesc &Desc = get(Opcode);
1113 if (!Desc.isVariadic() &&
1114 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1115 ErrInfo = "Instruction has wrong number of operands.";
1119 // Make sure the register classes are correct
1120 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1121 if (MI->getOperand(i).isFPImm()) {
1122 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1123 "all fp values to integers.";
1127 switch (Desc.OpInfo[i].OperandType) {
1128 case MCOI::OPERAND_REGISTER:
1129 if (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm()) {
1130 ErrInfo = "Illegal immediate value for operand.";
1134 case AMDGPU::OPERAND_REG_IMM32:
1136 case AMDGPU::OPERAND_REG_INLINE_C:
1137 if (MI->getOperand(i).isImm() && !isInlineConstant(MI->getOperand(i))) {
1138 ErrInfo = "Illegal immediate value for operand.";
1142 case MCOI::OPERAND_IMMEDIATE:
1143 // Check if this operand is an immediate.
1144 // FrameIndex operands will be replaced by immediates, so they are
1146 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1147 ErrInfo = "Expected immediate, but got non-immediate";
1155 if (!MI->getOperand(i).isReg())
1158 int RegClass = Desc.OpInfo[i].RegClass;
1159 if (RegClass != -1) {
1160 unsigned Reg = MI->getOperand(i).getReg();
1161 if (TargetRegisterInfo::isVirtualRegister(Reg))
1164 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1165 if (!RC->contains(Reg)) {
1166 ErrInfo = "Operand has incorrect register class.";
1174 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1175 // Only look at the true operands. Only a real operand can use the constant
1176 // bus, and we don't want to check pseudo-operands like the source modifier
1178 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1180 unsigned ConstantBusCount = 0;
1181 unsigned SGPRUsed = AMDGPU::NoRegister;
1182 for (int OpIdx : OpIndices) {
1186 const MachineOperand &MO = MI->getOperand(OpIdx);
1187 if (usesConstantBus(MRI, MO)) {
1189 if (MO.getReg() != SGPRUsed)
1191 SGPRUsed = MO.getReg();
1197 if (ConstantBusCount > 1) {
1198 ErrInfo = "VOP* instruction uses the constant bus more than once";
1203 // Verify SRC1 for VOP2 and VOPC
1204 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
1205 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1207 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
1213 if (isVOP3(Opcode)) {
1214 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
1215 ErrInfo = "VOP3 src0 cannot be a literal constant.";
1218 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
1219 ErrInfo = "VOP3 src1 cannot be a literal constant.";
1222 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
1223 ErrInfo = "VOP3 src2 cannot be a literal constant.";
1228 // Verify misc. restrictions on specific instructions.
1229 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1230 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1231 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1232 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1233 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1234 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1235 if (!compareMachineOp(Src0, Src1) &&
1236 !compareMachineOp(Src0, Src2)) {
1237 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1246 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1247 switch (MI.getOpcode()) {
1248 default: return AMDGPU::INSTRUCTION_LIST_END;
1249 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1250 case AMDGPU::COPY: return AMDGPU::COPY;
1251 case AMDGPU::PHI: return AMDGPU::PHI;
1252 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1253 case AMDGPU::S_MOV_B32:
1254 return MI.getOperand(1).isReg() ?
1255 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1256 case AMDGPU::S_ADD_I32:
1257 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1258 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1259 case AMDGPU::S_SUB_I32:
1260 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1261 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1262 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1263 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1264 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1265 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1266 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1267 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1268 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1269 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1270 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1271 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1272 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1273 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1274 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1275 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1276 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1277 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1278 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1279 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1280 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1281 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1282 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1283 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1284 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1285 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1286 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1287 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1288 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1289 case AMDGPU::S_LOAD_DWORD_IMM:
1290 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1291 case AMDGPU::S_LOAD_DWORDX2_IMM:
1292 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1293 case AMDGPU::S_LOAD_DWORDX4_IMM:
1294 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1295 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1296 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1297 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1301 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1302 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1305 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1306 unsigned OpNo) const {
1307 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1308 const MCInstrDesc &Desc = get(MI.getOpcode());
1309 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1310 Desc.OpInfo[OpNo].RegClass == -1) {
1311 unsigned Reg = MI.getOperand(OpNo).getReg();
1313 if (TargetRegisterInfo::isVirtualRegister(Reg))
1314 return MRI.getRegClass(Reg);
1315 return RI.getRegClass(Reg);
1318 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1319 return RI.getRegClass(RCID);
1322 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1323 switch (MI.getOpcode()) {
1325 case AMDGPU::REG_SEQUENCE:
1327 case AMDGPU::INSERT_SUBREG:
1328 return RI.hasVGPRs(getOpRegClass(MI, 0));
1330 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1334 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1335 MachineBasicBlock::iterator I = MI;
1336 MachineBasicBlock *MBB = MI->getParent();
1337 MachineOperand &MO = MI->getOperand(OpIdx);
1338 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1339 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1340 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1341 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1343 Opcode = AMDGPU::COPY;
1344 else if (RI.isSGPRClass(RC))
1345 Opcode = AMDGPU::S_MOV_B32;
1348 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1349 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1350 VRC = &AMDGPU::VReg_64RegClass;
1352 VRC = &AMDGPU::VGPR_32RegClass;
1354 unsigned Reg = MRI.createVirtualRegister(VRC);
1355 DebugLoc DL = MBB->findDebugLoc(I);
1356 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1358 MO.ChangeToRegister(Reg, false);
1361 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1362 MachineRegisterInfo &MRI,
1363 MachineOperand &SuperReg,
1364 const TargetRegisterClass *SuperRC,
1366 const TargetRegisterClass *SubRC)
1368 assert(SuperReg.isReg());
1370 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1371 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1373 // Just in case the super register is itself a sub-register, copy it to a new
1374 // value so we don't need to worry about merging its subreg index with the
1375 // SubIdx passed to this function. The register coalescer should be able to
1376 // eliminate this extra copy.
1377 MachineBasicBlock *MBB = MI->getParent();
1378 DebugLoc DL = MI->getDebugLoc();
1380 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1381 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1383 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1384 .addReg(NewSuperReg, 0, SubIdx);
1389 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1390 MachineBasicBlock::iterator MII,
1391 MachineRegisterInfo &MRI,
1393 const TargetRegisterClass *SuperRC,
1395 const TargetRegisterClass *SubRC) const {
1397 // XXX - Is there a better way to do this?
1398 if (SubIdx == AMDGPU::sub0)
1399 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1400 if (SubIdx == AMDGPU::sub1)
1401 return MachineOperand::CreateImm(Op.getImm() >> 32);
1403 llvm_unreachable("Unhandled register index for immediate");
1406 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1408 return MachineOperand::CreateReg(SubReg, false);
1411 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1412 MachineBasicBlock::iterator MI,
1413 MachineRegisterInfo &MRI,
1414 const TargetRegisterClass *RC,
1415 const MachineOperand &Op) const {
1416 MachineBasicBlock *MBB = MI->getParent();
1417 DebugLoc DL = MI->getDebugLoc();
1418 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1419 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1420 unsigned Dst = MRI.createVirtualRegister(RC);
1422 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1424 .addImm(Op.getImm() & 0xFFFFFFFF);
1425 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1427 .addImm(Op.getImm() >> 32);
1429 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1431 .addImm(AMDGPU::sub0)
1433 .addImm(AMDGPU::sub1);
1435 Worklist.push_back(Lo);
1436 Worklist.push_back(Hi);
1441 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1442 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1443 assert(Inst->getNumExplicitOperands() == 3);
1444 MachineOperand Op1 = Inst->getOperand(1);
1445 Inst->RemoveOperand(1);
1446 Inst->addOperand(Op1);
1449 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1450 const MachineOperand *MO) const {
1451 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1452 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1453 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1454 const TargetRegisterClass *DefinedRC =
1455 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1457 MO = &MI->getOperand(OpIdx);
1459 if (isVALU(InstDesc.Opcode) && usesConstantBus(MRI, *MO)) {
1461 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1462 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1465 if (usesConstantBus(MRI, MI->getOperand(i)) &&
1466 MI->getOperand(i).isReg() && MI->getOperand(i).getReg() != SGPRUsed) {
1474 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1476 // In order to be legal, the common sub-class must be equal to the
1477 // class of the current operand. For example:
1479 // v_mov_b32 s0 ; Operand defined as vsrc_32
1480 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1482 // s_sendmsg 0, s0 ; Operand defined as m0reg
1483 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1485 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1489 // Handle non-register types that are treated like immediates.
1490 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1493 // This operand expects an immediate.
1497 return isImmOperandLegal(MI, OpIdx, *MO);
1500 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1501 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1503 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1504 AMDGPU::OpName::src0);
1505 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1506 AMDGPU::OpName::src1);
1507 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1508 AMDGPU::OpName::src2);
1511 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1513 if (!isOperandLegal(MI, Src0Idx))
1514 legalizeOpWithMove(MI, Src0Idx);
1517 if (isOperandLegal(MI, Src1Idx))
1520 // Usually src0 of VOP2 instructions allow more types of inputs
1521 // than src1, so try to commute the instruction to decrease our
1522 // chances of having to insert a MOV instruction to legalize src1.
1523 if (MI->isCommutable()) {
1524 if (commuteInstruction(MI))
1525 // If we are successful in commuting, then we know MI is legal, so
1530 legalizeOpWithMove(MI, Src1Idx);
1534 // XXX - Do any VOP3 instructions read VCC?
1536 if (isVOP3(MI->getOpcode())) {
1537 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1539 // Find the one SGPR operand we are allowed to use.
1540 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1542 for (unsigned i = 0; i < 3; ++i) {
1543 int Idx = VOP3Idx[i];
1546 MachineOperand &MO = MI->getOperand(Idx);
1549 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1550 continue; // VGPRs are legal
1552 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1554 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1555 SGPRReg = MO.getReg();
1556 // We can use one SGPR in each VOP3 instruction.
1559 } else if (!isLiteralConstant(MO)) {
1560 // If it is not a register and not a literal constant, then it must be
1561 // an inline constant which is always legal.
1564 // If we make it this far, then the operand is not legal and we must
1566 legalizeOpWithMove(MI, Idx);
1570 // Legalize REG_SEQUENCE and PHI
1571 // The register class of the operands much be the same type as the register
1572 // class of the output.
1573 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1574 MI->getOpcode() == AMDGPU::PHI) {
1575 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1576 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1577 if (!MI->getOperand(i).isReg() ||
1578 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1580 const TargetRegisterClass *OpRC =
1581 MRI.getRegClass(MI->getOperand(i).getReg());
1582 if (RI.hasVGPRs(OpRC)) {
1589 // If any of the operands are VGPR registers, then they all most be
1590 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1592 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1595 VRC = RI.getEquivalentVGPRClass(SRC);
1602 // Update all the operands so they have the same type.
1603 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1604 if (!MI->getOperand(i).isReg() ||
1605 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1607 unsigned DstReg = MRI.createVirtualRegister(RC);
1608 MachineBasicBlock *InsertBB;
1609 MachineBasicBlock::iterator Insert;
1610 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1611 InsertBB = MI->getParent();
1614 // MI is a PHI instruction.
1615 InsertBB = MI->getOperand(i + 1).getMBB();
1616 Insert = InsertBB->getFirstTerminator();
1618 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1619 get(AMDGPU::COPY), DstReg)
1620 .addOperand(MI->getOperand(i));
1621 MI->getOperand(i).setReg(DstReg);
1625 // Legalize INSERT_SUBREG
1626 // src0 must have the same register class as dst
1627 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1628 unsigned Dst = MI->getOperand(0).getReg();
1629 unsigned Src0 = MI->getOperand(1).getReg();
1630 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1631 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1632 if (DstRC != Src0RC) {
1633 MachineBasicBlock &MBB = *MI->getParent();
1634 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1635 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1637 MI->getOperand(1).setReg(NewSrc0);
1642 // Legalize MUBUF* instructions
1643 // FIXME: If we start using the non-addr64 instructions for compute, we
1644 // may need to legalize them here.
1646 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1647 if (SRsrcIdx != -1) {
1648 // We have an MUBUF instruction
1649 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1650 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1651 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1652 RI.getRegClass(SRsrcRC))) {
1653 // The operands are legal.
1654 // FIXME: We may need to legalize operands besided srsrc.
1658 MachineBasicBlock &MBB = *MI->getParent();
1659 // Extract the the ptr from the resource descriptor.
1661 // SRsrcPtrLo = srsrc:sub0
1662 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1663 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VGPR_32RegClass);
1665 // SRsrcPtrHi = srsrc:sub1
1666 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1667 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VGPR_32RegClass);
1669 // Create an empty resource descriptor
1670 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1671 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1672 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1673 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1674 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1677 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1681 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1682 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1684 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1686 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1687 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1689 .addImm(RsrcDataFormat >> 32);
1691 // NewSRsrc = {Zero64, SRsrcFormat}
1692 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1695 .addImm(AMDGPU::sub0_sub1)
1696 .addReg(SRsrcFormatLo)
1697 .addImm(AMDGPU::sub2)
1698 .addReg(SRsrcFormatHi)
1699 .addImm(AMDGPU::sub3);
1701 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1702 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1703 unsigned NewVAddrLo;
1704 unsigned NewVAddrHi;
1706 // This is already an ADDR64 instruction so we need to add the pointer
1707 // extracted from the resource descriptor to the current value of VAddr.
1708 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1709 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1711 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1712 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1715 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1716 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1718 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1719 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1722 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1723 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1724 .addReg(AMDGPU::VCC, RegState::Implicit);
1727 // This instructions is the _OFFSET variant, so we need to convert it to
1729 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1730 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1731 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1733 // Create the new instruction.
1734 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1735 MachineInstr *Addr64 =
1736 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1739 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1740 // This will be replaced later
1741 // with the new value of vaddr.
1742 .addOperand(*SOffset)
1743 .addOperand(*Offset);
1745 MI->removeFromParent();
1748 NewVAddrLo = SRsrcPtrLo;
1749 NewVAddrHi = SRsrcPtrHi;
1750 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1751 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1754 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1755 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1758 .addImm(AMDGPU::sub0)
1760 .addImm(AMDGPU::sub1);
1763 // Update the instruction to use NewVaddr
1764 VAddr->setReg(NewVAddr);
1765 // Update the instruction to use NewSRsrc
1766 SRsrc->setReg(NewSRsrc);
1770 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1771 const TargetRegisterClass *HalfRC,
1772 unsigned HalfImmOp, unsigned HalfSGPROp,
1773 MachineInstr *&Lo, MachineInstr *&Hi) const {
1775 DebugLoc DL = MI->getDebugLoc();
1776 MachineBasicBlock *MBB = MI->getParent();
1777 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1778 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1779 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1780 unsigned HalfSize = HalfRC->getSize();
1781 const MachineOperand *OffOp =
1782 getNamedOperand(*MI, AMDGPU::OpName::offset);
1783 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1785 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1788 bool isVI = RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
1789 unsigned OffScale = isVI ? 1 : 4;
1790 // Handle the _IMM variant
1791 unsigned LoOffset = OffOp->getImm() * OffScale;
1792 unsigned HiOffset = LoOffset + HalfSize;
1793 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1795 .addImm(LoOffset / OffScale);
1797 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1798 unsigned OffsetSGPR =
1799 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1800 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1801 .addImm(HiOffset); // The offset in register is in bytes.
1802 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1804 .addReg(OffsetSGPR);
1806 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1808 .addImm(HiOffset / OffScale);
1811 // Handle the _SGPR variant
1812 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1813 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1816 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1817 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1820 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1822 .addReg(OffsetSGPR);
1825 unsigned SubLo, SubHi;
1828 SubLo = AMDGPU::sub0;
1829 SubHi = AMDGPU::sub1;
1832 SubLo = AMDGPU::sub0_sub1;
1833 SubHi = AMDGPU::sub2_sub3;
1836 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1837 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1840 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1841 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1844 llvm_unreachable("Unhandled HalfSize");
1847 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1848 .addOperand(MI->getOperand(0))
1855 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1856 MachineBasicBlock *MBB = MI->getParent();
1857 switch (MI->getOpcode()) {
1858 case AMDGPU::S_LOAD_DWORD_IMM:
1859 case AMDGPU::S_LOAD_DWORD_SGPR:
1860 case AMDGPU::S_LOAD_DWORDX2_IMM:
1861 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1862 case AMDGPU::S_LOAD_DWORDX4_IMM:
1863 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1864 unsigned NewOpcode = getVALUOp(*MI);
1868 if (MI->getOperand(2).isReg()) {
1869 RegOffset = MI->getOperand(2).getReg();
1872 assert(MI->getOperand(2).isImm());
1873 // SMRD instructions take a dword offsets on SI and byte offset on VI
1874 // and MUBUF instructions always take a byte offset.
1875 ImmOffset = MI->getOperand(2).getImm();
1876 if (RI.ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
1878 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1880 if (isUInt<12>(ImmOffset)) {
1881 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1885 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1892 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1893 unsigned DWord0 = RegOffset;
1894 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1895 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1896 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1897 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1899 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1901 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1902 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1903 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1904 .addImm(RsrcDataFormat >> 32);
1905 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1907 .addImm(AMDGPU::sub0)
1909 .addImm(AMDGPU::sub1)
1911 .addImm(AMDGPU::sub2)
1913 .addImm(AMDGPU::sub3);
1914 MI->setDesc(get(NewOpcode));
1915 if (MI->getOperand(2).isReg()) {
1916 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1918 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1920 MI->getOperand(1).setReg(SRsrc);
1921 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
1922 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1924 const TargetRegisterClass *NewDstRC =
1925 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
1927 unsigned DstReg = MI->getOperand(0).getReg();
1928 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1929 MRI.replaceRegWith(DstReg, NewDstReg);
1932 case AMDGPU::S_LOAD_DWORDX8_IMM:
1933 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
1934 MachineInstr *Lo, *Hi;
1935 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
1936 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
1937 MI->eraseFromParent();
1938 moveSMRDToVALU(Lo, MRI);
1939 moveSMRDToVALU(Hi, MRI);
1943 case AMDGPU::S_LOAD_DWORDX16_IMM:
1944 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
1945 MachineInstr *Lo, *Hi;
1946 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
1947 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
1948 MI->eraseFromParent();
1949 moveSMRDToVALU(Lo, MRI);
1950 moveSMRDToVALU(Hi, MRI);
1956 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1957 SmallVector<MachineInstr *, 128> Worklist;
1958 Worklist.push_back(&TopInst);
1960 while (!Worklist.empty()) {
1961 MachineInstr *Inst = Worklist.pop_back_val();
1962 MachineBasicBlock *MBB = Inst->getParent();
1963 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1965 unsigned Opcode = Inst->getOpcode();
1966 unsigned NewOpcode = getVALUOp(*Inst);
1968 // Handle some special cases
1971 if (isSMRD(Inst->getOpcode())) {
1972 moveSMRDToVALU(Inst, MRI);
1975 case AMDGPU::S_MOV_B64: {
1976 DebugLoc DL = Inst->getDebugLoc();
1978 // If the source operand is a register we can replace this with a
1980 if (Inst->getOperand(1).isReg()) {
1981 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1982 .addOperand(Inst->getOperand(0))
1983 .addOperand(Inst->getOperand(1));
1984 Worklist.push_back(Copy);
1986 // Otherwise, we need to split this into two movs, because there is
1987 // no 64-bit VALU move instruction.
1988 unsigned Reg = Inst->getOperand(0).getReg();
1989 unsigned Dst = split64BitImm(Worklist,
1992 MRI.getRegClass(Reg),
1993 Inst->getOperand(1));
1994 MRI.replaceRegWith(Reg, Dst);
1996 Inst->eraseFromParent();
1999 case AMDGPU::S_AND_B64:
2000 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
2001 Inst->eraseFromParent();
2004 case AMDGPU::S_OR_B64:
2005 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
2006 Inst->eraseFromParent();
2009 case AMDGPU::S_XOR_B64:
2010 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
2011 Inst->eraseFromParent();
2014 case AMDGPU::S_NOT_B64:
2015 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
2016 Inst->eraseFromParent();
2019 case AMDGPU::S_BCNT1_I32_B64:
2020 splitScalar64BitBCNT(Worklist, Inst);
2021 Inst->eraseFromParent();
2024 case AMDGPU::S_BFE_I64: {
2025 splitScalar64BitBFE(Worklist, Inst);
2026 Inst->eraseFromParent();
2030 case AMDGPU::S_LSHL_B32:
2031 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2032 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2036 case AMDGPU::S_ASHR_I32:
2037 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2038 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2042 case AMDGPU::S_LSHR_B32:
2043 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2044 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2048 case AMDGPU::S_LSHL_B64:
2049 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2050 NewOpcode = AMDGPU::V_LSHLREV_B64;
2054 case AMDGPU::S_ASHR_I64:
2055 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2056 NewOpcode = AMDGPU::V_ASHRREV_I64;
2060 case AMDGPU::S_LSHR_B64:
2061 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2062 NewOpcode = AMDGPU::V_LSHRREV_B64;
2067 case AMDGPU::S_BFE_U64:
2068 case AMDGPU::S_BFM_B64:
2069 llvm_unreachable("Moving this op to VALU not implemented");
2072 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2073 // We cannot move this instruction to the VALU, so we should try to
2074 // legalize its operands instead.
2075 legalizeOperands(Inst);
2079 // Use the new VALU Opcode.
2080 const MCInstrDesc &NewDesc = get(NewOpcode);
2081 Inst->setDesc(NewDesc);
2083 // Remove any references to SCC. Vector instructions can't read from it, and
2084 // We're just about to add the implicit use / defs of VCC, and we don't want
2086 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2087 MachineOperand &Op = Inst->getOperand(i);
2088 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2089 Inst->RemoveOperand(i);
2092 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2093 // We are converting these to a BFE, so we need to add the missing
2094 // operands for the size and offset.
2095 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2096 Inst->addOperand(MachineOperand::CreateImm(0));
2097 Inst->addOperand(MachineOperand::CreateImm(Size));
2099 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2100 // The VALU version adds the second operand to the result, so insert an
2102 Inst->addOperand(MachineOperand::CreateImm(0));
2105 addDescImplicitUseDef(NewDesc, Inst);
2107 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2108 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2109 // If we need to move this to VGPRs, we need to unpack the second operand
2110 // back into the 2 separate ones for bit offset and width.
2111 assert(OffsetWidthOp.isImm() &&
2112 "Scalar BFE is only implemented for constant width and offset");
2113 uint32_t Imm = OffsetWidthOp.getImm();
2115 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2116 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2117 Inst->RemoveOperand(2); // Remove old immediate.
2118 Inst->addOperand(MachineOperand::CreateImm(Offset));
2119 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2122 // Update the destination register class.
2124 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2127 // For target instructions, getOpRegClass just returns the virtual
2128 // register class associated with the operand, so we need to find an
2129 // equivalent VGPR register class in order to move the instruction to the
2133 case AMDGPU::REG_SEQUENCE:
2134 case AMDGPU::INSERT_SUBREG:
2135 if (RI.hasVGPRs(NewDstRC))
2137 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2145 unsigned DstReg = Inst->getOperand(0).getReg();
2146 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2147 MRI.replaceRegWith(DstReg, NewDstReg);
2149 // Legalize the operands
2150 legalizeOperands(Inst);
2152 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
2153 E = MRI.use_end(); I != E; ++I) {
2154 MachineInstr &UseMI = *I->getParent();
2155 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2156 Worklist.push_back(&UseMI);
2162 //===----------------------------------------------------------------------===//
2163 // Indirect addressing callbacks
2164 //===----------------------------------------------------------------------===//
2166 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2167 unsigned Channel) const {
2168 assert(Channel == 0);
2172 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2173 return &AMDGPU::VGPR_32RegClass;
2176 void SIInstrInfo::splitScalar64BitUnaryOp(
2177 SmallVectorImpl<MachineInstr *> &Worklist,
2179 unsigned Opcode) const {
2180 MachineBasicBlock &MBB = *Inst->getParent();
2181 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2183 MachineOperand &Dest = Inst->getOperand(0);
2184 MachineOperand &Src0 = Inst->getOperand(1);
2185 DebugLoc DL = Inst->getDebugLoc();
2187 MachineBasicBlock::iterator MII = Inst;
2189 const MCInstrDesc &InstDesc = get(Opcode);
2190 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2191 MRI.getRegClass(Src0.getReg()) :
2192 &AMDGPU::SGPR_32RegClass;
2194 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2196 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2197 AMDGPU::sub0, Src0SubRC);
2199 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2200 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2202 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2203 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2204 .addOperand(SrcReg0Sub0);
2206 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2207 AMDGPU::sub1, Src0SubRC);
2209 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2210 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2211 .addOperand(SrcReg0Sub1);
2213 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2214 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2216 .addImm(AMDGPU::sub0)
2218 .addImm(AMDGPU::sub1);
2220 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2222 // Try to legalize the operands in case we need to swap the order to keep it
2224 Worklist.push_back(LoHalf);
2225 Worklist.push_back(HiHalf);
2228 void SIInstrInfo::splitScalar64BitBinaryOp(
2229 SmallVectorImpl<MachineInstr *> &Worklist,
2231 unsigned Opcode) const {
2232 MachineBasicBlock &MBB = *Inst->getParent();
2233 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2235 MachineOperand &Dest = Inst->getOperand(0);
2236 MachineOperand &Src0 = Inst->getOperand(1);
2237 MachineOperand &Src1 = Inst->getOperand(2);
2238 DebugLoc DL = Inst->getDebugLoc();
2240 MachineBasicBlock::iterator MII = Inst;
2242 const MCInstrDesc &InstDesc = get(Opcode);
2243 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2244 MRI.getRegClass(Src0.getReg()) :
2245 &AMDGPU::SGPR_32RegClass;
2247 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2248 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2249 MRI.getRegClass(Src1.getReg()) :
2250 &AMDGPU::SGPR_32RegClass;
2252 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2254 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2255 AMDGPU::sub0, Src0SubRC);
2256 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2257 AMDGPU::sub0, Src1SubRC);
2259 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2260 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2262 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2263 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2264 .addOperand(SrcReg0Sub0)
2265 .addOperand(SrcReg1Sub0);
2267 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2268 AMDGPU::sub1, Src0SubRC);
2269 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2270 AMDGPU::sub1, Src1SubRC);
2272 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2273 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2274 .addOperand(SrcReg0Sub1)
2275 .addOperand(SrcReg1Sub1);
2277 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2278 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2280 .addImm(AMDGPU::sub0)
2282 .addImm(AMDGPU::sub1);
2284 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2286 // Try to legalize the operands in case we need to swap the order to keep it
2288 Worklist.push_back(LoHalf);
2289 Worklist.push_back(HiHalf);
2292 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2293 MachineInstr *Inst) const {
2294 MachineBasicBlock &MBB = *Inst->getParent();
2295 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2297 MachineBasicBlock::iterator MII = Inst;
2298 DebugLoc DL = Inst->getDebugLoc();
2300 MachineOperand &Dest = Inst->getOperand(0);
2301 MachineOperand &Src = Inst->getOperand(1);
2303 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2304 const TargetRegisterClass *SrcRC = Src.isReg() ?
2305 MRI.getRegClass(Src.getReg()) :
2306 &AMDGPU::SGPR_32RegClass;
2308 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2309 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2311 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2313 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2314 AMDGPU::sub0, SrcSubRC);
2315 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2316 AMDGPU::sub1, SrcSubRC);
2318 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2319 .addOperand(SrcRegSub0)
2322 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2323 .addOperand(SrcRegSub1)
2326 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2328 Worklist.push_back(First);
2329 Worklist.push_back(Second);
2332 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2333 MachineInstr *Inst) const {
2334 MachineBasicBlock &MBB = *Inst->getParent();
2335 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2336 MachineBasicBlock::iterator MII = Inst;
2337 DebugLoc DL = Inst->getDebugLoc();
2339 MachineOperand &Dest = Inst->getOperand(0);
2340 uint32_t Imm = Inst->getOperand(2).getImm();
2341 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2342 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2346 // Only sext_inreg cases handled.
2347 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2352 if (BitWidth < 32) {
2353 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2354 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2355 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2357 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2358 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2362 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2366 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2368 .addImm(AMDGPU::sub0)
2370 .addImm(AMDGPU::sub1);
2372 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2376 MachineOperand &Src = Inst->getOperand(1);
2377 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2378 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2380 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2382 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2384 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2385 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2386 .addImm(AMDGPU::sub0)
2388 .addImm(AMDGPU::sub1);
2390 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2393 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2394 MachineInstr *Inst) const {
2395 // Add the implict and explicit register definitions.
2396 if (NewDesc.ImplicitUses) {
2397 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2398 unsigned Reg = NewDesc.ImplicitUses[i];
2399 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2403 if (NewDesc.ImplicitDefs) {
2404 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2405 unsigned Reg = NewDesc.ImplicitDefs[i];
2406 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2411 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2412 int OpIndices[3]) const {
2413 const MCInstrDesc &Desc = get(MI->getOpcode());
2415 // Find the one SGPR operand we are allowed to use.
2416 unsigned SGPRReg = AMDGPU::NoRegister;
2418 // First we need to consider the instruction's operand requirements before
2419 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2420 // of VCC, but we are still bound by the constant bus requirement to only use
2423 // If the operand's class is an SGPR, we can never move it.
2425 for (const MachineOperand &MO : MI->implicit_operands()) {
2426 // We only care about reads.
2430 if (MO.getReg() == AMDGPU::VCC)
2433 if (MO.getReg() == AMDGPU::FLAT_SCR)
2434 return AMDGPU::FLAT_SCR;
2437 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2438 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2440 for (unsigned i = 0; i < 3; ++i) {
2441 int Idx = OpIndices[i];
2445 const MachineOperand &MO = MI->getOperand(Idx);
2446 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2447 SGPRReg = MO.getReg();
2449 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2450 UsedSGPRs[i] = MO.getReg();
2453 if (SGPRReg != AMDGPU::NoRegister)
2456 // We don't have a required SGPR operand, so we have a bit more freedom in
2457 // selecting operands to move.
2459 // Try to select the most used SGPR. If an SGPR is equal to one of the
2460 // others, we choose that.
2463 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2464 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2466 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2467 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2468 SGPRReg = UsedSGPRs[0];
2471 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2472 if (UsedSGPRs[1] == UsedSGPRs[2])
2473 SGPRReg = UsedSGPRs[1];
2479 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2480 MachineBasicBlock *MBB,
2481 MachineBasicBlock::iterator I,
2483 unsigned Address, unsigned OffsetReg) const {
2484 const DebugLoc &DL = MBB->findDebugLoc(I);
2485 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2486 getIndirectIndexBegin(*MBB->getParent()));
2488 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2489 .addReg(IndirectBaseReg, RegState::Define)
2490 .addOperand(I->getOperand(0))
2491 .addReg(IndirectBaseReg)
2497 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2498 MachineBasicBlock *MBB,
2499 MachineBasicBlock::iterator I,
2501 unsigned Address, unsigned OffsetReg) const {
2502 const DebugLoc &DL = MBB->findDebugLoc(I);
2503 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2504 getIndirectIndexBegin(*MBB->getParent()));
2506 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2507 .addOperand(I->getOperand(0))
2508 .addOperand(I->getOperand(1))
2509 .addReg(IndirectBaseReg)
2515 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2516 const MachineFunction &MF) const {
2517 int End = getIndirectIndexEnd(MF);
2518 int Begin = getIndirectIndexBegin(MF);
2524 for (int Index = Begin; Index <= End; ++Index)
2525 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2527 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2528 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2530 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2531 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2533 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2534 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2536 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2537 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2539 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2540 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2543 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2544 unsigned OperandName) const {
2545 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2549 return &MI.getOperand(Idx);
2552 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2553 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2554 if (ST.isAmdHsaOS())
2555 RsrcDataFormat |= (1ULL << 56);
2557 return RsrcDataFormat;