1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/MC/MCInstrDesc.h"
26 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
27 : AMDGPUInstrInfo(tm),
30 //===----------------------------------------------------------------------===//
31 // TargetInstrInfo callbacks
32 //===----------------------------------------------------------------------===//
35 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator MI, DebugLoc DL,
37 unsigned DestReg, unsigned SrcReg,
40 // If we are trying to copy to or from SCC, there is a bug somewhere else in
41 // the backend. While it may be theoretically possible to do this, it should
42 // never be necessary.
43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
45 static const int16_t Sub0_15[] = {
46 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
47 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
48 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
49 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
52 static const int16_t Sub0_7[] = {
53 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
54 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
57 static const int16_t Sub0_3[] = {
58 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
61 static const int16_t Sub0_2[] = {
62 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
65 static const int16_t Sub0_1[] = {
66 AMDGPU::sub0, AMDGPU::sub1, 0
70 const int16_t *SubIndices;
72 if (AMDGPU::M0 == DestReg) {
73 // Check if M0 isn't already set to this value
74 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
75 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
77 if (!I->definesRegister(AMDGPU::M0))
80 unsigned Opc = I->getOpcode();
81 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
84 if (!I->readsRegister(SrcReg))
87 // The copy isn't necessary
92 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
93 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
94 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
95 .addReg(SrcReg, getKillRegState(KillSrc));
98 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
99 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
100 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
101 .addReg(SrcReg, getKillRegState(KillSrc));
104 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
105 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
106 Opcode = AMDGPU::S_MOV_B32;
109 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
110 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
111 Opcode = AMDGPU::S_MOV_B32;
114 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
115 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
116 Opcode = AMDGPU::S_MOV_B32;
117 SubIndices = Sub0_15;
119 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
120 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
121 AMDGPU::SReg_32RegClass.contains(SrcReg));
122 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
123 .addReg(SrcReg, getKillRegState(KillSrc));
126 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
127 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
128 AMDGPU::SReg_64RegClass.contains(SrcReg));
129 Opcode = AMDGPU::V_MOV_B32_e32;
132 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
133 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
134 Opcode = AMDGPU::V_MOV_B32_e32;
137 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
138 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
139 AMDGPU::SReg_128RegClass.contains(SrcReg));
140 Opcode = AMDGPU::V_MOV_B32_e32;
143 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
144 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
145 AMDGPU::SReg_256RegClass.contains(SrcReg));
146 Opcode = AMDGPU::V_MOV_B32_e32;
149 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
150 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
151 AMDGPU::SReg_512RegClass.contains(SrcReg));
152 Opcode = AMDGPU::V_MOV_B32_e32;
153 SubIndices = Sub0_15;
156 llvm_unreachable("Can't copy register!");
159 while (unsigned SubIdx = *SubIndices++) {
160 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
161 get(Opcode), RI.getSubReg(DestReg, SubIdx));
163 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
166 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
170 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
173 // Try to map original to commuted opcode
174 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
177 // Try to map commuted to original opcode
178 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
184 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
185 MachineBasicBlock::iterator MI,
186 unsigned SrcReg, bool isKill,
188 const TargetRegisterClass *RC,
189 const TargetRegisterInfo *TRI) const {
190 SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
191 DebugLoc DL = MBB.findDebugLoc(MI);
192 unsigned KillFlag = isKill ? RegState::Kill : 0;
193 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
195 if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
196 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MBB.getParent());
198 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), MFI->SpillTracker.LaneVGPR)
199 .addReg(SrcReg, KillFlag)
201 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR, Lane);
202 } else if (RI.isSGPRClass(RC)) {
203 // We are only allowed to create one new instruction when spilling
204 // registers, so we need to use pseudo instruction for vector
207 // Reserve a spot in the spill tracker for each sub-register of
208 // the vector register.
209 unsigned NumSubRegs = RC->getSize() / 4;
210 unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MBB.getParent(),
212 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
216 switch (RC->getSize() * 8) {
217 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
218 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
219 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
220 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
221 default: llvm_unreachable("Cannot spill register class");
224 BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
228 llvm_unreachable("VGPR spilling not supported");
232 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
233 MachineBasicBlock::iterator MI,
234 unsigned DestReg, int FrameIndex,
235 const TargetRegisterClass *RC,
236 const TargetRegisterInfo *TRI) const {
237 SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
238 DebugLoc DL = MBB.findDebugLoc(MI);
239 if (RI.isSGPRClass(RC)){
241 switch(RC->getSize() * 8) {
242 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
243 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
244 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
245 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
246 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
247 default: llvm_unreachable("Cannot spill register class");
250 SIMachineFunctionInfo::SpilledReg Spill =
251 MFI->SpillTracker.getSpilledReg(FrameIndex);
253 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
257 llvm_unreachable("VGPR spilling not supported");
261 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
264 case AMDGPU::SI_SPILL_S512_SAVE:
265 case AMDGPU::SI_SPILL_S512_RESTORE:
267 case AMDGPU::SI_SPILL_S256_SAVE:
268 case AMDGPU::SI_SPILL_S256_RESTORE:
270 case AMDGPU::SI_SPILL_S128_SAVE:
271 case AMDGPU::SI_SPILL_S128_RESTORE:
273 case AMDGPU::SI_SPILL_S64_SAVE:
274 case AMDGPU::SI_SPILL_S64_RESTORE:
276 case AMDGPU::SI_SPILL_S32_RESTORE:
278 default: llvm_unreachable("Invalid spill opcode");
282 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
291 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
296 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
297 SIMachineFunctionInfo *MFI =
298 MI->getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
299 MachineBasicBlock &MBB = *MI->getParent();
300 DebugLoc DL = MBB.findDebugLoc(MI);
301 switch (MI->getOpcode()) {
302 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
304 // SGPR register spill
305 case AMDGPU::SI_SPILL_S512_SAVE:
306 case AMDGPU::SI_SPILL_S256_SAVE:
307 case AMDGPU::SI_SPILL_S128_SAVE:
308 case AMDGPU::SI_SPILL_S64_SAVE: {
309 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
310 unsigned FrameIndex = MI->getOperand(2).getImm();
312 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
313 SIMachineFunctionInfo::SpilledReg Spill;
314 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
315 &AMDGPU::SGPR_32RegClass, i);
316 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
318 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
319 MI->getOperand(0).getReg())
321 .addImm(Spill.Lane + i);
323 MI->eraseFromParent();
327 // SGPR register restore
328 case AMDGPU::SI_SPILL_S512_RESTORE:
329 case AMDGPU::SI_SPILL_S256_RESTORE:
330 case AMDGPU::SI_SPILL_S128_RESTORE:
331 case AMDGPU::SI_SPILL_S64_RESTORE:
332 case AMDGPU::SI_SPILL_S32_RESTORE: {
333 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
335 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
336 SIMachineFunctionInfo::SpilledReg Spill;
337 unsigned FrameIndex = MI->getOperand(2).getImm();
338 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
339 &AMDGPU::SGPR_32RegClass, i);
340 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
342 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
343 .addReg(MI->getOperand(1).getReg())
344 .addImm(Spill.Lane + i);
347 MI->eraseFromParent();
354 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
357 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
358 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
361 // Cannot commute VOP2 if src0 is SGPR.
362 if (isVOP2(MI->getOpcode()) && MI->getOperand(1).isReg() &&
363 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
366 if (!MI->getOperand(2).isReg()) {
367 // XXX: Commute instructions with FPImm operands
368 if (NewMI || MI->getOperand(2).isFPImm() ||
369 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
373 // XXX: Commute VOP3 instructions with abs and neg set.
374 if (isVOP3(MI->getOpcode()) &&
375 (MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
376 AMDGPU::OpName::abs)).getImm() ||
377 MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
378 AMDGPU::OpName::neg)).getImm()))
381 unsigned Reg = MI->getOperand(1).getReg();
382 unsigned SubReg = MI->getOperand(1).getSubReg();
383 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
384 MI->getOperand(2).ChangeToRegister(Reg, false);
385 MI->getOperand(2).setSubReg(SubReg);
387 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
391 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
396 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
397 MachineBasicBlock::iterator I,
399 unsigned SrcReg) const {
400 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
401 DstReg) .addReg(SrcReg);
404 bool SIInstrInfo::isMov(unsigned Opcode) const {
406 default: return false;
407 case AMDGPU::S_MOV_B32:
408 case AMDGPU::S_MOV_B64:
409 case AMDGPU::V_MOV_B32_e32:
410 case AMDGPU::V_MOV_B32_e64:
416 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
417 return RC != &AMDGPU::EXECRegRegClass;
421 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
422 AliasAnalysis *AA) const {
423 switch(MI->getOpcode()) {
424 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
425 case AMDGPU::S_MOV_B32:
426 case AMDGPU::S_MOV_B64:
427 case AMDGPU::V_MOV_B32_e32:
428 return MI->getOperand(1).isImm();
434 // Helper function generated by tablegen. We are wrapping this with
435 // an SIInstrInfo function that reutrns bool rather than int.
436 int isDS(uint16_t Opcode);
440 bool SIInstrInfo::isDS(uint16_t Opcode) const {
441 return ::AMDGPU::isDS(Opcode) != -1;
444 int SIInstrInfo::isMIMG(uint16_t Opcode) const {
445 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
448 int SIInstrInfo::isSMRD(uint16_t Opcode) const {
449 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
452 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
453 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
456 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
457 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
460 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
461 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
464 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
465 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
468 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
469 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
472 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
473 int32_t Val = Imm.getSExtValue();
474 if (Val >= -16 && Val <= 64)
477 // The actual type of the operand does not seem to matter as long
478 // as the bits match one of the inline immediate values. For example:
480 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
481 // so it is a legal inline immediate.
483 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
484 // floating-point, so it is a legal inline immediate.
486 return (APInt::floatToBits(0.0f) == Imm) ||
487 (APInt::floatToBits(1.0f) == Imm) ||
488 (APInt::floatToBits(-1.0f) == Imm) ||
489 (APInt::floatToBits(0.5f) == Imm) ||
490 (APInt::floatToBits(-0.5f) == Imm) ||
491 (APInt::floatToBits(2.0f) == Imm) ||
492 (APInt::floatToBits(-2.0f) == Imm) ||
493 (APInt::floatToBits(4.0f) == Imm) ||
494 (APInt::floatToBits(-4.0f) == Imm);
497 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
499 return isInlineConstant(APInt(32, MO.getImm(), true));
502 APFloat FpImm = MO.getFPImm()->getValueAPF();
503 return isInlineConstant(FpImm.bitcastToAPInt());
509 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
510 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
513 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
514 StringRef &ErrInfo) const {
515 uint16_t Opcode = MI->getOpcode();
516 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
517 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
518 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
520 // Make sure the number of operands is correct.
521 const MCInstrDesc &Desc = get(Opcode);
522 if (!Desc.isVariadic() &&
523 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
524 ErrInfo = "Instruction has wrong number of operands.";
528 // Make sure the register classes are correct
529 for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
530 switch (Desc.OpInfo[i].OperandType) {
531 case MCOI::OPERAND_REGISTER:
533 case MCOI::OPERAND_IMMEDIATE:
534 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm()) {
535 ErrInfo = "Expected immediate, but got non-immediate";
543 if (!MI->getOperand(i).isReg())
546 int RegClass = Desc.OpInfo[i].RegClass;
547 if (RegClass != -1) {
548 unsigned Reg = MI->getOperand(i).getReg();
549 if (TargetRegisterInfo::isVirtualRegister(Reg))
552 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
553 if (!RC->contains(Reg)) {
554 ErrInfo = "Operand has incorrect register class.";
562 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
563 unsigned ConstantBusCount = 0;
564 unsigned SGPRUsed = AMDGPU::NoRegister;
565 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
566 const MachineOperand &MO = MI->getOperand(i);
567 if (MO.isReg() && MO.isUse() &&
568 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
570 // EXEC register uses the constant bus.
571 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
574 // SGPRs use the constant bus
575 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
577 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
578 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
579 if (SGPRUsed != MO.getReg()) {
581 SGPRUsed = MO.getReg();
585 // Literal constants use the constant bus.
586 if (isLiteralConstant(MO))
589 if (ConstantBusCount > 1) {
590 ErrInfo = "VOP* instruction uses the constant bus more than once";
595 // Verify SRC1 for VOP2 and VOPC
596 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
597 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
598 if (Src1.isImm() || Src1.isFPImm()) {
599 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
605 if (isVOP3(Opcode)) {
606 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
607 ErrInfo = "VOP3 src0 cannot be a literal constant.";
610 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
611 ErrInfo = "VOP3 src1 cannot be a literal constant.";
614 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
615 ErrInfo = "VOP3 src2 cannot be a literal constant.";
622 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
623 switch (MI.getOpcode()) {
624 default: return AMDGPU::INSTRUCTION_LIST_END;
625 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
626 case AMDGPU::COPY: return AMDGPU::COPY;
627 case AMDGPU::PHI: return AMDGPU::PHI;
628 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
629 case AMDGPU::S_MOV_B32:
630 return MI.getOperand(1).isReg() ?
631 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
632 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
633 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
634 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
635 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
636 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
637 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
638 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
639 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
640 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
641 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
642 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
643 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
644 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
645 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
646 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
647 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
648 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
649 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
650 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
651 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
652 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
653 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
654 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
655 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
656 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
657 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
658 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
659 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
660 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
661 case AMDGPU::S_LOAD_DWORD_IMM:
662 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
663 case AMDGPU::S_LOAD_DWORDX2_IMM:
664 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
665 case AMDGPU::S_LOAD_DWORDX4_IMM:
666 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
667 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
671 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
672 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
675 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
676 unsigned OpNo) const {
677 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
678 const MCInstrDesc &Desc = get(MI.getOpcode());
679 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
680 Desc.OpInfo[OpNo].RegClass == -1)
681 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
683 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
684 return RI.getRegClass(RCID);
687 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
688 switch (MI.getOpcode()) {
690 case AMDGPU::REG_SEQUENCE:
692 case AMDGPU::INSERT_SUBREG:
693 return RI.hasVGPRs(getOpRegClass(MI, 0));
695 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
699 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
700 MachineBasicBlock::iterator I = MI;
701 MachineOperand &MO = MI->getOperand(OpIdx);
702 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
703 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
704 const TargetRegisterClass *RC = RI.getRegClass(RCID);
705 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
707 Opcode = AMDGPU::COPY;
708 } else if (RI.isSGPRClass(RC)) {
709 Opcode = AMDGPU::S_MOV_B32;
712 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
713 unsigned Reg = MRI.createVirtualRegister(VRC);
714 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
716 MO.ChangeToRegister(Reg, false);
719 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
720 MachineRegisterInfo &MRI,
721 MachineOperand &SuperReg,
722 const TargetRegisterClass *SuperRC,
724 const TargetRegisterClass *SubRC)
726 assert(SuperReg.isReg());
728 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
729 unsigned SubReg = MRI.createVirtualRegister(SubRC);
731 // Just in case the super register is itself a sub-register, copy it to a new
732 // value so we don't need to worry about merging its subreg index with the
733 // SubIdx passed to this function. The register coalescer should be able to
734 // eliminate this extra copy.
735 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
737 .addOperand(SuperReg);
739 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
741 .addReg(NewSuperReg, 0, SubIdx);
745 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
746 MachineBasicBlock::iterator MII,
747 MachineRegisterInfo &MRI,
749 const TargetRegisterClass *SuperRC,
751 const TargetRegisterClass *SubRC) const {
753 // XXX - Is there a better way to do this?
754 if (SubIdx == AMDGPU::sub0)
755 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
756 if (SubIdx == AMDGPU::sub1)
757 return MachineOperand::CreateImm(Op.getImm() >> 32);
759 llvm_unreachable("Unhandled register index for immediate");
762 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
764 return MachineOperand::CreateReg(SubReg, false);
767 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
768 MachineBasicBlock::iterator MI,
769 MachineRegisterInfo &MRI,
770 const TargetRegisterClass *RC,
771 const MachineOperand &Op) const {
772 MachineBasicBlock *MBB = MI->getParent();
773 DebugLoc DL = MI->getDebugLoc();
774 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
775 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
776 unsigned Dst = MRI.createVirtualRegister(RC);
778 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
780 .addImm(Op.getImm() & 0xFFFFFFFF);
781 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
783 .addImm(Op.getImm() >> 32);
785 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
787 .addImm(AMDGPU::sub0)
789 .addImm(AMDGPU::sub1);
791 Worklist.push_back(Lo);
792 Worklist.push_back(Hi);
797 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
798 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
799 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
800 AMDGPU::OpName::src0);
801 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
802 AMDGPU::OpName::src1);
803 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
804 AMDGPU::OpName::src2);
807 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
808 MachineOperand &Src0 = MI->getOperand(Src0Idx);
809 MachineOperand &Src1 = MI->getOperand(Src1Idx);
811 // If the instruction implicitly reads VCC, we can't have any SGPR operands,
813 bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI);
814 if (ReadsVCC && Src0.isReg() &&
815 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) {
816 legalizeOpWithMove(MI, Src0Idx);
820 if (ReadsVCC && Src1.isReg() &&
821 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
822 legalizeOpWithMove(MI, Src1Idx);
826 // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
827 // be the first operand, and there can only be one.
828 if (Src1.isImm() || Src1.isFPImm() ||
829 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
830 if (MI->isCommutable()) {
831 if (commuteInstruction(MI))
834 legalizeOpWithMove(MI, Src1Idx);
838 // XXX - Do any VOP3 instructions read VCC?
840 if (isVOP3(MI->getOpcode())) {
841 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
842 unsigned SGPRReg = AMDGPU::NoRegister;
843 for (unsigned i = 0; i < 3; ++i) {
844 int Idx = VOP3Idx[i];
847 MachineOperand &MO = MI->getOperand(Idx);
850 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
851 continue; // VGPRs are legal
853 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
855 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
856 SGPRReg = MO.getReg();
857 // We can use one SGPR in each VOP3 instruction.
860 } else if (!isLiteralConstant(MO)) {
861 // If it is not a register and not a literal constant, then it must be
862 // an inline constant which is always legal.
865 // If we make it this far, then the operand is not legal and we must
867 legalizeOpWithMove(MI, Idx);
871 // Legalize REG_SEQUENCE and PHI
872 // The register class of the operands much be the same type as the register
873 // class of the output.
874 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
875 MI->getOpcode() == AMDGPU::PHI) {
876 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
877 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
878 if (!MI->getOperand(i).isReg() ||
879 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
881 const TargetRegisterClass *OpRC =
882 MRI.getRegClass(MI->getOperand(i).getReg());
883 if (RI.hasVGPRs(OpRC)) {
890 // If any of the operands are VGPR registers, then they all most be
891 // otherwise we will create illegal VGPR->SGPR copies when legalizing
893 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
896 VRC = RI.getEquivalentVGPRClass(SRC);
903 // Update all the operands so they have the same type.
904 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
905 if (!MI->getOperand(i).isReg() ||
906 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
908 unsigned DstReg = MRI.createVirtualRegister(RC);
909 MachineBasicBlock *InsertBB;
910 MachineBasicBlock::iterator Insert;
911 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
912 InsertBB = MI->getParent();
915 // MI is a PHI instruction.
916 InsertBB = MI->getOperand(i + 1).getMBB();
917 Insert = InsertBB->getFirstTerminator();
919 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
920 get(AMDGPU::COPY), DstReg)
921 .addOperand(MI->getOperand(i));
922 MI->getOperand(i).setReg(DstReg);
926 // Legalize INSERT_SUBREG
927 // src0 must have the same register class as dst
928 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
929 unsigned Dst = MI->getOperand(0).getReg();
930 unsigned Src0 = MI->getOperand(1).getReg();
931 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
932 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
933 if (DstRC != Src0RC) {
934 MachineBasicBlock &MBB = *MI->getParent();
935 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
936 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
938 MI->getOperand(1).setReg(NewSrc0);
943 // Legalize MUBUF* instructions
944 // FIXME: If we start using the non-addr64 instructions for compute, we
945 // may need to legalize them here.
947 int SRsrcIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
948 AMDGPU::OpName::srsrc);
949 int VAddrIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
950 AMDGPU::OpName::vaddr);
951 if (SRsrcIdx != -1 && VAddrIdx != -1) {
952 const TargetRegisterClass *VAddrRC =
953 RI.getRegClass(get(MI->getOpcode()).OpInfo[VAddrIdx].RegClass);
955 if(VAddrRC->getSize() == 8 &&
956 MRI.getRegClass(MI->getOperand(SRsrcIdx).getReg()) != VAddrRC) {
957 // We have a MUBUF instruction that uses a 64-bit vaddr register and
958 // srsrc has the incorrect register class. In order to fix this, we
959 // need to extract the pointer from the resource descriptor (srsrc),
960 // add it to the value of vadd, then store the result in the vaddr
961 // operand. Then, we need to set the pointer field of the resource
962 // descriptor to zero.
964 MachineBasicBlock &MBB = *MI->getParent();
965 MachineOperand &SRsrcOp = MI->getOperand(SRsrcIdx);
966 MachineOperand &VAddrOp = MI->getOperand(VAddrIdx);
967 unsigned SRsrcPtrLo, SRsrcPtrHi, VAddrLo, VAddrHi;
968 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
969 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
970 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
971 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
972 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
973 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
974 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
976 // SRsrcPtrLo = srsrc:sub0
977 SRsrcPtrLo = buildExtractSubReg(MI, MRI, SRsrcOp,
978 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
980 // SRsrcPtrHi = srsrc:sub1
981 SRsrcPtrHi = buildExtractSubReg(MI, MRI, SRsrcOp,
982 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
984 // VAddrLo = vaddr:sub0
985 VAddrLo = buildExtractSubReg(MI, MRI, VAddrOp,
986 &AMDGPU::VReg_64RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
988 // VAddrHi = vaddr:sub1
989 VAddrHi = buildExtractSubReg(MI, MRI, VAddrOp,
990 &AMDGPU::VReg_64RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
992 // NewVaddrLo = SRsrcPtrLo + VAddrLo
993 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
997 .addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
999 // NewVaddrHi = SRsrcPtrHi + VAddrHi
1000 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1004 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1005 .addReg(AMDGPU::VCC, RegState::Implicit);
1007 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1008 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1011 .addImm(AMDGPU::sub0)
1013 .addImm(AMDGPU::sub1);
1016 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1020 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1021 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1023 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1025 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1026 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1028 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1030 // NewSRsrc = {Zero64, SRsrcFormat}
1031 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1034 .addImm(AMDGPU::sub0_sub1)
1035 .addReg(SRsrcFormatLo)
1036 .addImm(AMDGPU::sub2)
1037 .addReg(SRsrcFormatHi)
1038 .addImm(AMDGPU::sub3);
1040 // Update the instruction to use NewVaddr
1041 MI->getOperand(VAddrIdx).setReg(NewVAddr);
1042 // Update the instruction to use NewSRsrc
1043 MI->getOperand(SRsrcIdx).setReg(NewSRsrc);
1048 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1049 MachineBasicBlock *MBB = MI->getParent();
1050 switch (MI->getOpcode()) {
1051 case AMDGPU::S_LOAD_DWORD_IMM:
1052 case AMDGPU::S_LOAD_DWORD_SGPR:
1053 case AMDGPU::S_LOAD_DWORDX2_IMM:
1054 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1055 case AMDGPU::S_LOAD_DWORDX4_IMM:
1056 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1057 unsigned NewOpcode = getVALUOp(*MI);
1061 if (MI->getOperand(2).isReg()) {
1062 RegOffset = MI->getOperand(2).getReg();
1065 assert(MI->getOperand(2).isImm());
1066 // SMRD instructions take a dword offsets and MUBUF instructions
1067 // take a byte offset.
1068 ImmOffset = MI->getOperand(2).getImm() << 2;
1069 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1070 if (isUInt<12>(ImmOffset)) {
1071 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1075 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1082 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1083 unsigned DWord0 = RegOffset;
1084 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1085 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1086 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1088 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1090 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1091 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1092 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1093 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1094 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1096 .addImm(AMDGPU::sub0)
1098 .addImm(AMDGPU::sub1)
1100 .addImm(AMDGPU::sub2)
1102 .addImm(AMDGPU::sub3);
1103 MI->setDesc(get(NewOpcode));
1104 if (MI->getOperand(2).isReg()) {
1105 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1107 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1109 MI->getOperand(1).setReg(SRsrc);
1110 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1114 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1115 SmallVector<MachineInstr *, 128> Worklist;
1116 Worklist.push_back(&TopInst);
1118 while (!Worklist.empty()) {
1119 MachineInstr *Inst = Worklist.pop_back_val();
1120 MachineBasicBlock *MBB = Inst->getParent();
1121 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1123 unsigned Opcode = Inst->getOpcode();
1124 unsigned NewOpcode = getVALUOp(*Inst);
1126 // Handle some special cases
1129 if (isSMRD(Inst->getOpcode())) {
1130 moveSMRDToVALU(Inst, MRI);
1133 case AMDGPU::S_MOV_B64: {
1134 DebugLoc DL = Inst->getDebugLoc();
1136 // If the source operand is a register we can replace this with a
1138 if (Inst->getOperand(1).isReg()) {
1139 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1140 .addOperand(Inst->getOperand(0))
1141 .addOperand(Inst->getOperand(1));
1142 Worklist.push_back(Copy);
1144 // Otherwise, we need to split this into two movs, because there is
1145 // no 64-bit VALU move instruction.
1146 unsigned Reg = Inst->getOperand(0).getReg();
1147 unsigned Dst = split64BitImm(Worklist,
1150 MRI.getRegClass(Reg),
1151 Inst->getOperand(1));
1152 MRI.replaceRegWith(Reg, Dst);
1154 Inst->eraseFromParent();
1157 case AMDGPU::S_AND_B64:
1158 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1159 Inst->eraseFromParent();
1162 case AMDGPU::S_OR_B64:
1163 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1164 Inst->eraseFromParent();
1167 case AMDGPU::S_XOR_B64:
1168 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1169 Inst->eraseFromParent();
1172 case AMDGPU::S_NOT_B64:
1173 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1174 Inst->eraseFromParent();
1177 case AMDGPU::S_BCNT1_I32_B64:
1178 splitScalar64BitBCNT(Worklist, Inst);
1179 Inst->eraseFromParent();
1182 case AMDGPU::S_BFE_U64:
1183 case AMDGPU::S_BFE_I64:
1184 case AMDGPU::S_BFM_B64:
1185 llvm_unreachable("Moving this op to VALU not implemented");
1188 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1189 // We cannot move this instruction to the VALU, so we should try to
1190 // legalize its operands instead.
1191 legalizeOperands(Inst);
1195 // Use the new VALU Opcode.
1196 const MCInstrDesc &NewDesc = get(NewOpcode);
1197 Inst->setDesc(NewDesc);
1199 // Remove any references to SCC. Vector instructions can't read from it, and
1200 // We're just about to add the implicit use / defs of VCC, and we don't want
1202 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1203 MachineOperand &Op = Inst->getOperand(i);
1204 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1205 Inst->RemoveOperand(i);
1208 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1209 // We are converting these to a BFE, so we need to add the missing
1210 // operands for the size and offset.
1211 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1212 Inst->addOperand(Inst->getOperand(1));
1213 Inst->getOperand(1).ChangeToImmediate(0);
1214 Inst->addOperand(MachineOperand::CreateImm(0));
1215 Inst->addOperand(MachineOperand::CreateImm(0));
1216 Inst->addOperand(MachineOperand::CreateImm(0));
1217 Inst->addOperand(MachineOperand::CreateImm(Size));
1219 // XXX - Other pointless operands. There are 4, but it seems you only need
1220 // 3 to not hit an assertion later in MCInstLower.
1221 Inst->addOperand(MachineOperand::CreateImm(0));
1222 Inst->addOperand(MachineOperand::CreateImm(0));
1223 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1224 // The VALU version adds the second operand to the result, so insert an
1226 Inst->addOperand(MachineOperand::CreateImm(0));
1229 addDescImplicitUseDef(NewDesc, Inst);
1231 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1232 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1233 // If we need to move this to VGPRs, we need to unpack the second operand
1234 // back into the 2 separate ones for bit offset and width.
1235 assert(OffsetWidthOp.isImm() &&
1236 "Scalar BFE is only implemented for constant width and offset");
1237 uint32_t Imm = OffsetWidthOp.getImm();
1239 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1240 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1242 Inst->RemoveOperand(2); // Remove old immediate.
1243 Inst->addOperand(Inst->getOperand(1));
1244 Inst->getOperand(1).ChangeToImmediate(0);
1245 Inst->addOperand(MachineOperand::CreateImm(0));
1246 Inst->addOperand(MachineOperand::CreateImm(Offset));
1247 Inst->addOperand(MachineOperand::CreateImm(0));
1248 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1249 Inst->addOperand(MachineOperand::CreateImm(0));
1250 Inst->addOperand(MachineOperand::CreateImm(0));
1253 // Update the destination register class.
1255 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1258 // For target instructions, getOpRegClass just returns the virtual
1259 // register class associated with the operand, so we need to find an
1260 // equivalent VGPR register class in order to move the instruction to the
1264 case AMDGPU::REG_SEQUENCE:
1265 case AMDGPU::INSERT_SUBREG:
1266 if (RI.hasVGPRs(NewDstRC))
1268 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1276 unsigned DstReg = Inst->getOperand(0).getReg();
1277 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1278 MRI.replaceRegWith(DstReg, NewDstReg);
1280 // Legalize the operands
1281 legalizeOperands(Inst);
1283 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1284 E = MRI.use_end(); I != E; ++I) {
1285 MachineInstr &UseMI = *I->getParent();
1286 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1287 Worklist.push_back(&UseMI);
1293 //===----------------------------------------------------------------------===//
1294 // Indirect addressing callbacks
1295 //===----------------------------------------------------------------------===//
1297 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1298 unsigned Channel) const {
1299 assert(Channel == 0);
1303 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1304 return &AMDGPU::VReg_32RegClass;
1307 void SIInstrInfo::splitScalar64BitUnaryOp(
1308 SmallVectorImpl<MachineInstr *> &Worklist,
1310 unsigned Opcode) const {
1311 MachineBasicBlock &MBB = *Inst->getParent();
1312 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1314 MachineOperand &Dest = Inst->getOperand(0);
1315 MachineOperand &Src0 = Inst->getOperand(1);
1316 DebugLoc DL = Inst->getDebugLoc();
1318 MachineBasicBlock::iterator MII = Inst;
1320 const MCInstrDesc &InstDesc = get(Opcode);
1321 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1322 MRI.getRegClass(Src0.getReg()) :
1323 &AMDGPU::SGPR_32RegClass;
1325 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1327 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1328 AMDGPU::sub0, Src0SubRC);
1330 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1331 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1333 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1334 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1335 .addOperand(SrcReg0Sub0);
1337 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1338 AMDGPU::sub1, Src0SubRC);
1340 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1341 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1342 .addOperand(SrcReg0Sub1);
1344 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1345 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1347 .addImm(AMDGPU::sub0)
1349 .addImm(AMDGPU::sub1);
1351 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1353 // Try to legalize the operands in case we need to swap the order to keep it
1355 Worklist.push_back(LoHalf);
1356 Worklist.push_back(HiHalf);
1359 void SIInstrInfo::splitScalar64BitBinaryOp(
1360 SmallVectorImpl<MachineInstr *> &Worklist,
1362 unsigned Opcode) const {
1363 MachineBasicBlock &MBB = *Inst->getParent();
1364 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1366 MachineOperand &Dest = Inst->getOperand(0);
1367 MachineOperand &Src0 = Inst->getOperand(1);
1368 MachineOperand &Src1 = Inst->getOperand(2);
1369 DebugLoc DL = Inst->getDebugLoc();
1371 MachineBasicBlock::iterator MII = Inst;
1373 const MCInstrDesc &InstDesc = get(Opcode);
1374 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1375 MRI.getRegClass(Src0.getReg()) :
1376 &AMDGPU::SGPR_32RegClass;
1378 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1379 const TargetRegisterClass *Src1RC = Src1.isReg() ?
1380 MRI.getRegClass(Src1.getReg()) :
1381 &AMDGPU::SGPR_32RegClass;
1383 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
1385 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1386 AMDGPU::sub0, Src0SubRC);
1387 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1388 AMDGPU::sub0, Src1SubRC);
1390 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1391 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1393 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1394 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1395 .addOperand(SrcReg0Sub0)
1396 .addOperand(SrcReg1Sub0);
1398 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1399 AMDGPU::sub1, Src0SubRC);
1400 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1401 AMDGPU::sub1, Src1SubRC);
1403 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1404 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1405 .addOperand(SrcReg0Sub1)
1406 .addOperand(SrcReg1Sub1);
1408 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1409 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1411 .addImm(AMDGPU::sub0)
1413 .addImm(AMDGPU::sub1);
1415 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1417 // Try to legalize the operands in case we need to swap the order to keep it
1419 Worklist.push_back(LoHalf);
1420 Worklist.push_back(HiHalf);
1423 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
1424 MachineInstr *Inst) const {
1425 MachineBasicBlock &MBB = *Inst->getParent();
1426 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1428 MachineBasicBlock::iterator MII = Inst;
1429 DebugLoc DL = Inst->getDebugLoc();
1431 MachineOperand &Dest = Inst->getOperand(0);
1432 MachineOperand &Src = Inst->getOperand(1);
1434 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
1435 const TargetRegisterClass *SrcRC = Src.isReg() ?
1436 MRI.getRegClass(Src.getReg()) :
1437 &AMDGPU::SGPR_32RegClass;
1439 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1440 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1442 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
1444 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1445 AMDGPU::sub0, SrcSubRC);
1446 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1447 AMDGPU::sub1, SrcSubRC);
1449 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
1450 .addOperand(SrcRegSub0)
1453 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
1454 .addOperand(SrcRegSub1)
1457 MRI.replaceRegWith(Dest.getReg(), ResultReg);
1459 Worklist.push_back(First);
1460 Worklist.push_back(Second);
1463 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
1464 MachineInstr *Inst) const {
1465 // Add the implict and explicit register definitions.
1466 if (NewDesc.ImplicitUses) {
1467 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
1468 unsigned Reg = NewDesc.ImplicitUses[i];
1469 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
1473 if (NewDesc.ImplicitDefs) {
1474 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
1475 unsigned Reg = NewDesc.ImplicitDefs[i];
1476 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
1481 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1482 MachineBasicBlock *MBB,
1483 MachineBasicBlock::iterator I,
1485 unsigned Address, unsigned OffsetReg) const {
1486 const DebugLoc &DL = MBB->findDebugLoc(I);
1487 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1488 getIndirectIndexBegin(*MBB->getParent()));
1490 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
1491 .addReg(IndirectBaseReg, RegState::Define)
1492 .addOperand(I->getOperand(0))
1493 .addReg(IndirectBaseReg)
1499 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1500 MachineBasicBlock *MBB,
1501 MachineBasicBlock::iterator I,
1503 unsigned Address, unsigned OffsetReg) const {
1504 const DebugLoc &DL = MBB->findDebugLoc(I);
1505 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1506 getIndirectIndexBegin(*MBB->getParent()));
1508 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
1509 .addOperand(I->getOperand(0))
1510 .addOperand(I->getOperand(1))
1511 .addReg(IndirectBaseReg)
1517 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1518 const MachineFunction &MF) const {
1519 int End = getIndirectIndexEnd(MF);
1520 int Begin = getIndirectIndexBegin(MF);
1526 for (int Index = Begin; Index <= End; ++Index)
1527 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1529 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
1530 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1532 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
1533 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1535 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
1536 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1538 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
1539 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1541 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
1542 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));