1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI(st) {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
79 int64_t &Offset1) const {
80 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
83 unsigned Opc0 = Load0->getMachineOpcode();
84 unsigned Opc1 = Load1->getMachineOpcode();
86 // Make sure both are actually loads.
87 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
90 if (isDS(Opc0) && isDS(Opc1)) {
92 // FIXME: Handle this case:
93 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
97 if (Load0->getOperand(1) != Load1->getOperand(1))
101 if (findChainOperand(Load0) != findChainOperand(Load1))
104 // Skip read2 / write2 variants for simplicity.
105 // TODO: We should report true if the used offsets are adjacent (excluded
107 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
108 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
111 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
112 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
116 if (isSMRD(Opc0) && isSMRD(Opc1)) {
117 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
120 if (Load0->getOperand(0) != Load1->getOperand(0))
124 if (findChainOperand(Load0) != findChainOperand(Load1))
127 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
128 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
132 // MUBUF and MTBUF can access the same addresses.
133 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
135 // MUBUF and MTBUF have vaddr at different indices.
136 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
137 findChainOperand(Load0) != findChainOperand(Load1) ||
138 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
139 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
142 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
143 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
145 if (OffIdx0 == -1 || OffIdx1 == -1)
148 // getNamedOperandIdx returns the index for MachineInstrs. Since they
149 // inlcude the output in the operand list, but SDNodes don't, we need to
150 // subtract the index by one.
154 SDValue Off0 = Load0->getOperand(OffIdx0);
155 SDValue Off1 = Load1->getOperand(OffIdx1);
157 // The offset might be a FrameIndexSDNode.
158 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
161 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
162 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
169 static bool isStride64(unsigned Opc) {
171 case AMDGPU::DS_READ2ST64_B32:
172 case AMDGPU::DS_READ2ST64_B64:
173 case AMDGPU::DS_WRITE2ST64_B32:
174 case AMDGPU::DS_WRITE2ST64_B64:
181 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
182 unsigned &BaseReg, unsigned &Offset,
183 const TargetRegisterInfo *TRI) const {
184 unsigned Opc = LdSt->getOpcode();
186 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
187 AMDGPU::OpName::offset);
189 // Normal, single offset LDS instruction.
190 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
191 AMDGPU::OpName::addr);
193 BaseReg = AddrReg->getReg();
194 Offset = OffsetImm->getImm();
198 // The 2 offset instructions use offset0 and offset1 instead. We can treat
199 // these as a load with a single offset if the 2 offsets are consecutive. We
200 // will use this for some partially aligned loads.
201 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
202 AMDGPU::OpName::offset0);
203 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
204 AMDGPU::OpName::offset1);
206 uint8_t Offset0 = Offset0Imm->getImm();
207 uint8_t Offset1 = Offset1Imm->getImm();
208 assert(Offset1 > Offset0);
210 if (Offset1 - Offset0 == 1) {
211 // Each of these offsets is in element sized units, so we need to convert
212 // to bytes of the individual reads.
216 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
218 assert(LdSt->mayStore());
219 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
220 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
226 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
227 AMDGPU::OpName::addr);
228 BaseReg = AddrReg->getReg();
229 Offset = EltSize * Offset0;
236 if (isMUBUF(Opc) || isMTBUF(Opc)) {
237 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
240 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
241 AMDGPU::OpName::vaddr);
245 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
246 AMDGPU::OpName::offset);
247 BaseReg = AddrReg->getReg();
248 Offset = OffsetImm->getImm();
253 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
254 AMDGPU::OpName::offset);
258 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
259 AMDGPU::OpName::sbase);
260 BaseReg = SBaseReg->getReg();
261 Offset = OffsetImm->getImm();
268 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
269 MachineInstr *SecondLdSt,
270 unsigned NumLoads) const {
271 unsigned Opc0 = FirstLdSt->getOpcode();
272 unsigned Opc1 = SecondLdSt->getOpcode();
274 // TODO: This needs finer tuning
278 if (isDS(Opc0) && isDS(Opc1))
281 if (isSMRD(Opc0) && isSMRD(Opc1))
284 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
291 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
292 MachineBasicBlock::iterator MI, DebugLoc DL,
293 unsigned DestReg, unsigned SrcReg,
294 bool KillSrc) const {
296 // If we are trying to copy to or from SCC, there is a bug somewhere else in
297 // the backend. While it may be theoretically possible to do this, it should
298 // never be necessary.
299 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
301 static const int16_t Sub0_15[] = {
302 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
303 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
304 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
305 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
308 static const int16_t Sub0_7[] = {
309 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
310 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
313 static const int16_t Sub0_3[] = {
314 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
317 static const int16_t Sub0_2[] = {
318 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
321 static const int16_t Sub0_1[] = {
322 AMDGPU::sub0, AMDGPU::sub1, 0
326 const int16_t *SubIndices;
328 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
329 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
330 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
331 .addReg(SrcReg, getKillRegState(KillSrc));
334 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
335 if (DestReg == AMDGPU::VCC) {
336 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
337 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
338 .addReg(SrcReg, getKillRegState(KillSrc));
340 // FIXME: Hack until VReg_1 removed.
341 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
342 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
344 .addReg(SrcReg, getKillRegState(KillSrc));
350 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
356 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
357 Opcode = AMDGPU::S_MOV_B32;
360 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
361 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
362 Opcode = AMDGPU::S_MOV_B32;
365 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
366 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
367 Opcode = AMDGPU::S_MOV_B32;
368 SubIndices = Sub0_15;
370 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
371 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
372 AMDGPU::SReg_32RegClass.contains(SrcReg));
373 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
374 .addReg(SrcReg, getKillRegState(KillSrc));
377 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
378 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
379 AMDGPU::SReg_64RegClass.contains(SrcReg));
380 Opcode = AMDGPU::V_MOV_B32_e32;
383 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
384 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
385 Opcode = AMDGPU::V_MOV_B32_e32;
388 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
389 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
390 AMDGPU::SReg_128RegClass.contains(SrcReg));
391 Opcode = AMDGPU::V_MOV_B32_e32;
394 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
395 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
396 AMDGPU::SReg_256RegClass.contains(SrcReg));
397 Opcode = AMDGPU::V_MOV_B32_e32;
400 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
401 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
402 AMDGPU::SReg_512RegClass.contains(SrcReg));
403 Opcode = AMDGPU::V_MOV_B32_e32;
404 SubIndices = Sub0_15;
407 llvm_unreachable("Can't copy register!");
410 while (unsigned SubIdx = *SubIndices++) {
411 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
412 get(Opcode), RI.getSubReg(DestReg, SubIdx));
414 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
417 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
421 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
424 // Try to map original to commuted opcode
425 NewOpc = AMDGPU::getCommuteRev(Opcode);
426 // Check if the commuted (REV) opcode exists on the target.
427 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
430 // Try to map commuted to original opcode
431 NewOpc = AMDGPU::getCommuteOrig(Opcode);
432 // Check if the original (non-REV) opcode exists on the target.
433 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
439 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
441 if (DstRC->getSize() == 4) {
442 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
443 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
444 return AMDGPU::S_MOV_B64;
445 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
446 return AMDGPU::V_MOV_B64_PSEUDO;
451 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
452 MachineBasicBlock::iterator MI,
453 unsigned SrcReg, bool isKill,
455 const TargetRegisterClass *RC,
456 const TargetRegisterInfo *TRI) const {
457 MachineFunction *MF = MBB.getParent();
458 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
459 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
460 DebugLoc DL = MBB.findDebugLoc(MI);
463 if (RI.isSGPRClass(RC)) {
464 // We are only allowed to create one new instruction when spilling
465 // registers, so we need to use pseudo instruction for spilling
467 switch (RC->getSize() * 8) {
468 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
469 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
470 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
471 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
472 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
474 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
475 MFI->setHasSpilledVGPRs();
477 switch(RC->getSize() * 8) {
478 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
479 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
480 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
481 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
482 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
483 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
488 FrameInfo->setObjectAlignment(FrameIndex, 4);
489 BuildMI(MBB, MI, DL, get(Opcode))
491 .addFrameIndex(FrameIndex)
492 // Place-holder registers, these will be filled in by
493 // SIPrepareScratchRegs.
494 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
495 .addReg(AMDGPU::SGPR0, RegState::Undef);
497 LLVMContext &Ctx = MF->getFunction()->getContext();
498 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
500 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
505 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
506 MachineBasicBlock::iterator MI,
507 unsigned DestReg, int FrameIndex,
508 const TargetRegisterClass *RC,
509 const TargetRegisterInfo *TRI) const {
510 MachineFunction *MF = MBB.getParent();
511 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
512 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
513 DebugLoc DL = MBB.findDebugLoc(MI);
516 if (RI.isSGPRClass(RC)){
517 switch(RC->getSize() * 8) {
518 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
519 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
520 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
521 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
522 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
524 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
525 switch(RC->getSize() * 8) {
526 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
527 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
528 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
529 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
530 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
531 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
536 FrameInfo->setObjectAlignment(FrameIndex, 4);
537 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
538 .addFrameIndex(FrameIndex)
539 // Place-holder registers, these will be filled in by
540 // SIPrepareScratchRegs.
541 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
542 .addReg(AMDGPU::SGPR0, RegState::Undef);
545 LLVMContext &Ctx = MF->getFunction()->getContext();
546 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
547 " restore register");
548 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
552 /// \param @Offset Offset in bytes of the FrameIndex being spilled
553 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
554 MachineBasicBlock::iterator MI,
555 RegScavenger *RS, unsigned TmpReg,
556 unsigned FrameOffset,
557 unsigned Size) const {
558 MachineFunction *MF = MBB.getParent();
559 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
560 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
561 const SIRegisterInfo *TRI =
562 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
563 DebugLoc DL = MBB.findDebugLoc(MI);
564 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
565 unsigned WavefrontSize = ST.getWavefrontSize();
567 unsigned TIDReg = MFI->getTIDReg();
568 if (!MFI->hasCalculatedTID()) {
569 MachineBasicBlock &Entry = MBB.getParent()->front();
570 MachineBasicBlock::iterator Insert = Entry.front();
571 DebugLoc DL = Insert->getDebugLoc();
573 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
574 if (TIDReg == AMDGPU::NoRegister)
578 if (MFI->getShaderType() == ShaderType::COMPUTE &&
579 WorkGroupSize > WavefrontSize) {
581 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
582 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
583 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
584 unsigned InputPtrReg =
585 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
586 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
587 if (!Entry.isLiveIn(Reg))
588 Entry.addLiveIn(Reg);
591 RS->enterBasicBlock(&Entry);
592 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
593 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
594 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
596 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
597 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
599 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
601 // NGROUPS.X * NGROUPS.Y
602 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
605 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
606 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
609 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
610 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
614 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
615 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
620 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
625 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
631 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
635 MFI->setTIDReg(TIDReg);
638 // Add FrameIndex to LDS offset
639 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
640 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
647 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
656 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
661 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
662 MachineBasicBlock &MBB = *MI->getParent();
663 DebugLoc DL = MBB.findDebugLoc(MI);
664 switch (MI->getOpcode()) {
665 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
667 case AMDGPU::SI_CONSTDATA_PTR: {
668 unsigned Reg = MI->getOperand(0).getReg();
669 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
670 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
672 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
674 // Add 32-bit offset from this instruction to the start of the constant data.
675 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
677 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
678 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
679 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
682 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
683 .addReg(AMDGPU::SCC, RegState::Implicit);
684 MI->eraseFromParent();
687 case AMDGPU::SGPR_USE:
688 // This is just a placeholder for register allocation.
689 MI->eraseFromParent();
692 case AMDGPU::V_MOV_B64_PSEUDO: {
693 unsigned Dst = MI->getOperand(0).getReg();
694 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
695 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
697 const MachineOperand &SrcOp = MI->getOperand(1);
698 // FIXME: Will this work for 64-bit floating point immediates?
699 assert(!SrcOp.isFPImm());
701 APInt Imm(64, SrcOp.getImm());
702 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
703 .addImm(Imm.getLoBits(32).getZExtValue())
704 .addReg(Dst, RegState::Implicit);
705 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
706 .addImm(Imm.getHiBits(32).getZExtValue())
707 .addReg(Dst, RegState::Implicit);
709 assert(SrcOp.isReg());
710 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
711 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
712 .addReg(Dst, RegState::Implicit);
713 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
714 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
715 .addReg(Dst, RegState::Implicit);
717 MI->eraseFromParent();
724 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
727 if (MI->getNumOperands() < 3)
730 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
731 AMDGPU::OpName::src0);
732 assert(Src0Idx != -1 && "Should always have src0 operand");
734 MachineOperand &Src0 = MI->getOperand(Src0Idx);
738 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
739 AMDGPU::OpName::src1);
743 MachineOperand &Src1 = MI->getOperand(Src1Idx);
745 // Make sure it's legal to commute operands for VOP2.
746 if (isVOP2(MI->getOpcode()) &&
747 (!isOperandLegal(MI, Src0Idx, &Src1) ||
748 !isOperandLegal(MI, Src1Idx, &Src0))) {
753 // Allow commuting instructions with Imm operands.
754 if (NewMI || !Src1.isImm() ||
755 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
759 // Be sure to copy the source modifiers to the right place.
760 if (MachineOperand *Src0Mods
761 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
762 MachineOperand *Src1Mods
763 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
765 int Src0ModsVal = Src0Mods->getImm();
766 if (!Src1Mods && Src0ModsVal != 0)
769 // XXX - This assert might be a lie. It might be useful to have a neg
770 // modifier with 0.0.
771 int Src1ModsVal = Src1Mods->getImm();
772 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
774 Src1Mods->setImm(Src0ModsVal);
775 Src0Mods->setImm(Src1ModsVal);
778 unsigned Reg = Src0.getReg();
779 unsigned SubReg = Src0.getSubReg();
781 Src0.ChangeToImmediate(Src1.getImm());
783 llvm_unreachable("Should only have immediates");
785 Src1.ChangeToRegister(Reg, false);
786 Src1.setSubReg(SubReg);
788 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
792 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
797 // This needs to be implemented because the source modifiers may be inserted
798 // between the true commutable operands, and the base
799 // TargetInstrInfo::commuteInstruction uses it.
800 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
802 unsigned &SrcOpIdx2) const {
803 const MCInstrDesc &MCID = MI->getDesc();
804 if (!MCID.isCommutable())
807 unsigned Opc = MI->getOpcode();
808 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
812 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
814 if (!MI->getOperand(Src0Idx).isReg())
817 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
821 if (!MI->getOperand(Src1Idx).isReg())
824 // If any source modifiers are set, the generic instruction commuting won't
825 // understand how to copy the source modifiers.
826 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
827 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
835 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
836 MachineBasicBlock::iterator I,
838 unsigned SrcReg) const {
839 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
840 DstReg) .addReg(SrcReg);
843 bool SIInstrInfo::isMov(unsigned Opcode) const {
845 default: return false;
846 case AMDGPU::S_MOV_B32:
847 case AMDGPU::S_MOV_B64:
848 case AMDGPU::V_MOV_B32_e32:
849 case AMDGPU::V_MOV_B32_e64:
855 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
856 return RC != &AMDGPU::EXECRegRegClass;
859 static void removeModOperands(MachineInstr &MI) {
860 unsigned Opc = MI.getOpcode();
861 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
862 AMDGPU::OpName::src0_modifiers);
863 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
864 AMDGPU::OpName::src1_modifiers);
865 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
866 AMDGPU::OpName::src2_modifiers);
868 MI.RemoveOperand(Src2ModIdx);
869 MI.RemoveOperand(Src1ModIdx);
870 MI.RemoveOperand(Src0ModIdx);
873 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
874 unsigned Reg, MachineRegisterInfo *MRI) const {
875 if (!MRI->hasOneNonDBGUse(Reg))
878 unsigned Opc = UseMI->getOpcode();
879 if (Opc == AMDGPU::V_MAD_F32) {
880 // Don't fold if we are using source modifiers. The new VOP2 instructions
882 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
883 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
884 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
888 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
889 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
890 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
892 // Multiplied part is the constant: Use v_madmk_f32
893 // We should only expect these to be on src0 due to canonicalizations.
894 if (Src0->isReg() && Src0->getReg() == Reg) {
895 if (!Src1->isReg() ||
896 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
899 if (!Src2->isReg() ||
900 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
903 // We need to do some weird looking operand shuffling since the madmk
904 // operands are out of the normal expected order with the multiplied
905 // constant as the last operand.
907 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
912 const int64_t Imm = DefMI->getOperand(1).getImm();
914 // FIXME: This would be a lot easier if we could return a new instruction
915 // instead of having to modify in place.
917 // Remove these first since they are at the end.
918 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(AMDGPU::V_MAD_F32,
919 AMDGPU::OpName::omod));
920 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(AMDGPU::V_MAD_F32,
921 AMDGPU::OpName::clamp));
923 unsigned Src1Reg = Src1->getReg();
924 unsigned Src1SubReg = Src1->getSubReg();
925 unsigned Src2Reg = Src2->getReg();
926 unsigned Src2SubReg = Src2->getSubReg();
927 Src0->setReg(Src1Reg);
928 Src0->setSubReg(Src1SubReg);
929 Src1->setReg(Src2Reg);
930 Src1->setSubReg(Src2SubReg);
932 Src2->ChangeToImmediate(Imm);
934 removeModOperands(*UseMI);
935 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
937 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
939 DefMI->eraseFromParent();
944 // Added part is the constant: Use v_madak_f32
945 if (Src2->isReg() && Src2->getReg() == Reg) {
946 // Not allowed to use constant bus for another operand.
947 // We can however allow an inline immediate as src0.
948 if (!Src0->isImm() &&
949 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
952 if (!Src1->isReg() ||
953 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
956 const int64_t Imm = DefMI->getOperand(1).getImm();
958 // FIXME: This would be a lot easier if we could return a new instruction
959 // instead of having to modify in place.
961 // Remove these first since they are at the end.
962 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(AMDGPU::V_MAD_F32,
963 AMDGPU::OpName::omod));
964 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(AMDGPU::V_MAD_F32,
965 AMDGPU::OpName::clamp));
967 Src2->ChangeToImmediate(Imm);
969 // These come before src2.
970 removeModOperands(*UseMI);
971 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
973 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
975 DefMI->eraseFromParent();
985 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
986 AliasAnalysis *AA) const {
987 switch(MI->getOpcode()) {
988 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
989 case AMDGPU::S_MOV_B32:
990 case AMDGPU::S_MOV_B64:
991 case AMDGPU::V_MOV_B32_e32:
992 return MI->getOperand(1).isImm();
996 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
997 int WidthB, int OffsetB) {
998 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
999 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1000 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1001 return LowOffset + LowWidth <= HighOffset;
1004 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1005 MachineInstr *MIb) const {
1006 unsigned BaseReg0, Offset0;
1007 unsigned BaseReg1, Offset1;
1009 if (getLdStBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1010 getLdStBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1011 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1012 "read2 / write2 not expected here yet");
1013 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1014 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1015 if (BaseReg0 == BaseReg1 &&
1016 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1024 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1026 AliasAnalysis *AA) const {
1027 unsigned Opc0 = MIa->getOpcode();
1028 unsigned Opc1 = MIb->getOpcode();
1030 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1031 "MIa must load from or modify a memory location");
1032 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1033 "MIb must load from or modify a memory location");
1035 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1038 // XXX - Can we relax this between address spaces?
1039 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1042 // TODO: Should we check the address space from the MachineMemOperand? That
1043 // would allow us to distinguish objects we know don't alias based on the
1044 // underlying addres space, even if it was lowered to a different one,
1045 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1049 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1051 return !isFLAT(Opc1);
1054 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
1055 if (isMUBUF(Opc1) || isMTBUF(Opc1))
1056 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1058 return !isFLAT(Opc1) && !isSMRD(Opc1);
1063 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1065 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
1070 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1078 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1079 int64_t SVal = Imm.getSExtValue();
1080 if (SVal >= -16 && SVal <= 64)
1083 if (Imm.getBitWidth() == 64) {
1084 uint64_t Val = Imm.getZExtValue();
1085 return (DoubleToBits(0.0) == Val) ||
1086 (DoubleToBits(1.0) == Val) ||
1087 (DoubleToBits(-1.0) == Val) ||
1088 (DoubleToBits(0.5) == Val) ||
1089 (DoubleToBits(-0.5) == Val) ||
1090 (DoubleToBits(2.0) == Val) ||
1091 (DoubleToBits(-2.0) == Val) ||
1092 (DoubleToBits(4.0) == Val) ||
1093 (DoubleToBits(-4.0) == Val);
1096 // The actual type of the operand does not seem to matter as long
1097 // as the bits match one of the inline immediate values. For example:
1099 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1100 // so it is a legal inline immediate.
1102 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1103 // floating-point, so it is a legal inline immediate.
1104 uint32_t Val = Imm.getZExtValue();
1106 return (FloatToBits(0.0f) == Val) ||
1107 (FloatToBits(1.0f) == Val) ||
1108 (FloatToBits(-1.0f) == Val) ||
1109 (FloatToBits(0.5f) == Val) ||
1110 (FloatToBits(-0.5f) == Val) ||
1111 (FloatToBits(2.0f) == Val) ||
1112 (FloatToBits(-2.0f) == Val) ||
1113 (FloatToBits(4.0f) == Val) ||
1114 (FloatToBits(-4.0f) == Val);
1117 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1118 unsigned OpSize) const {
1120 // MachineOperand provides no way to tell the true operand size, since it
1121 // only records a 64-bit value. We need to know the size to determine if a
1122 // 32-bit floating point immediate bit pattern is legal for an integer
1123 // immediate. It would be for any 32-bit integer operand, but would not be
1124 // for a 64-bit one.
1126 unsigned BitSize = 8 * OpSize;
1127 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1133 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1134 unsigned OpSize) const {
1135 return MO.isImm() && !isInlineConstant(MO, OpSize);
1138 static bool compareMachineOp(const MachineOperand &Op0,
1139 const MachineOperand &Op1) {
1140 if (Op0.getType() != Op1.getType())
1143 switch (Op0.getType()) {
1144 case MachineOperand::MO_Register:
1145 return Op0.getReg() == Op1.getReg();
1146 case MachineOperand::MO_Immediate:
1147 return Op0.getImm() == Op1.getImm();
1149 llvm_unreachable("Didn't expect to be comparing these operand types");
1153 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1154 const MachineOperand &MO) const {
1155 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1157 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1159 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1162 if (OpInfo.RegClass < 0)
1165 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1166 if (isLiteralConstant(MO, OpSize))
1167 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1169 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1172 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) const {
1174 case AMDGPUAS::GLOBAL_ADDRESS: {
1175 // MUBUF instructions a 12-bit offset in bytes.
1176 return isUInt<12>(OffsetSize);
1178 case AMDGPUAS::CONSTANT_ADDRESS: {
1179 // SMRD instructions have an 8-bit offset in dwords on SI and
1180 // a 20-bit offset in bytes on VI.
1181 if (RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1182 return isUInt<20>(OffsetSize);
1184 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1186 case AMDGPUAS::LOCAL_ADDRESS:
1187 case AMDGPUAS::REGION_ADDRESS: {
1188 // The single offset versions have a 16-bit offset in bytes.
1189 return isUInt<16>(OffsetSize);
1191 case AMDGPUAS::PRIVATE_ADDRESS:
1192 // Indirect register addressing does not use any offsets.
1198 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1199 int Op32 = AMDGPU::getVOPe32(Opcode);
1203 return pseudoToMCOpcode(Op32) != -1;
1206 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1207 // The src0_modifier operand is present on all instructions
1208 // that have modifiers.
1210 return AMDGPU::getNamedOperandIdx(Opcode,
1211 AMDGPU::OpName::src0_modifiers) != -1;
1214 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1215 unsigned OpName) const {
1216 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1217 return Mods && Mods->getImm();
1220 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1221 const MachineOperand &MO,
1222 unsigned OpSize) const {
1223 // Literal constants use the constant bus.
1224 if (isLiteralConstant(MO, OpSize))
1227 if (!MO.isReg() || !MO.isUse())
1230 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1231 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1233 // FLAT_SCR is just an SGPR pair.
1234 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1237 // EXEC register uses the constant bus.
1238 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1241 // SGPRs use the constant bus
1242 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1243 (!MO.isImplicit() &&
1244 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1245 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1252 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1253 StringRef &ErrInfo) const {
1254 uint16_t Opcode = MI->getOpcode();
1255 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1256 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1257 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1258 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1260 // Make sure the number of operands is correct.
1261 const MCInstrDesc &Desc = get(Opcode);
1262 if (!Desc.isVariadic() &&
1263 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1264 ErrInfo = "Instruction has wrong number of operands.";
1268 // Make sure the register classes are correct
1269 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1270 if (MI->getOperand(i).isFPImm()) {
1271 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1272 "all fp values to integers.";
1276 int RegClass = Desc.OpInfo[i].RegClass;
1278 switch (Desc.OpInfo[i].OperandType) {
1279 case MCOI::OPERAND_REGISTER:
1280 if (MI->getOperand(i).isImm()) {
1281 ErrInfo = "Illegal immediate value for operand.";
1285 case AMDGPU::OPERAND_REG_IMM32:
1287 case AMDGPU::OPERAND_REG_INLINE_C:
1288 if (isLiteralConstant(MI->getOperand(i),
1289 RI.getRegClass(RegClass)->getSize())) {
1290 ErrInfo = "Illegal immediate value for operand.";
1294 case MCOI::OPERAND_IMMEDIATE:
1295 // Check if this operand is an immediate.
1296 // FrameIndex operands will be replaced by immediates, so they are
1298 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1299 ErrInfo = "Expected immediate, but got non-immediate";
1307 if (!MI->getOperand(i).isReg())
1310 if (RegClass != -1) {
1311 unsigned Reg = MI->getOperand(i).getReg();
1312 if (TargetRegisterInfo::isVirtualRegister(Reg))
1315 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1316 if (!RC->contains(Reg)) {
1317 ErrInfo = "Operand has incorrect register class.";
1325 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1326 // Only look at the true operands. Only a real operand can use the constant
1327 // bus, and we don't want to check pseudo-operands like the source modifier
1329 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1331 unsigned ConstantBusCount = 0;
1332 unsigned SGPRUsed = AMDGPU::NoRegister;
1333 for (int OpIdx : OpIndices) {
1336 const MachineOperand &MO = MI->getOperand(OpIdx);
1337 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1339 if (MO.getReg() != SGPRUsed)
1341 SGPRUsed = MO.getReg();
1347 if (ConstantBusCount > 1) {
1348 ErrInfo = "VOP* instruction uses the constant bus more than once";
1353 // Verify misc. restrictions on specific instructions.
1354 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1355 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1356 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1357 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1358 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1359 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1360 if (!compareMachineOp(Src0, Src1) &&
1361 !compareMachineOp(Src0, Src2)) {
1362 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1371 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1372 switch (MI.getOpcode()) {
1373 default: return AMDGPU::INSTRUCTION_LIST_END;
1374 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1375 case AMDGPU::COPY: return AMDGPU::COPY;
1376 case AMDGPU::PHI: return AMDGPU::PHI;
1377 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1378 case AMDGPU::S_MOV_B32:
1379 return MI.getOperand(1).isReg() ?
1380 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1381 case AMDGPU::S_ADD_I32:
1382 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1383 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1384 case AMDGPU::S_SUB_I32:
1385 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1386 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1387 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1388 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1389 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1390 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1391 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1392 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1393 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1394 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1395 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1396 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1397 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1398 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1399 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1400 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1401 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1402 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1403 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1404 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1405 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1406 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1407 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1408 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1409 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1410 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1411 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1412 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1413 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1414 case AMDGPU::S_LOAD_DWORD_IMM:
1415 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1416 case AMDGPU::S_LOAD_DWORDX2_IMM:
1417 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1418 case AMDGPU::S_LOAD_DWORDX4_IMM:
1419 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1420 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1421 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1422 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1426 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1427 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1430 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1431 unsigned OpNo) const {
1432 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1433 const MCInstrDesc &Desc = get(MI.getOpcode());
1434 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1435 Desc.OpInfo[OpNo].RegClass == -1) {
1436 unsigned Reg = MI.getOperand(OpNo).getReg();
1438 if (TargetRegisterInfo::isVirtualRegister(Reg))
1439 return MRI.getRegClass(Reg);
1440 return RI.getPhysRegClass(Reg);
1443 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1444 return RI.getRegClass(RCID);
1447 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1448 switch (MI.getOpcode()) {
1450 case AMDGPU::REG_SEQUENCE:
1452 case AMDGPU::INSERT_SUBREG:
1453 return RI.hasVGPRs(getOpRegClass(MI, 0));
1455 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1459 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1460 MachineBasicBlock::iterator I = MI;
1461 MachineBasicBlock *MBB = MI->getParent();
1462 MachineOperand &MO = MI->getOperand(OpIdx);
1463 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1464 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1465 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1466 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1468 Opcode = AMDGPU::COPY;
1469 else if (RI.isSGPRClass(RC))
1470 Opcode = AMDGPU::S_MOV_B32;
1473 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1474 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1475 VRC = &AMDGPU::VReg_64RegClass;
1477 VRC = &AMDGPU::VGPR_32RegClass;
1479 unsigned Reg = MRI.createVirtualRegister(VRC);
1480 DebugLoc DL = MBB->findDebugLoc(I);
1481 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1483 MO.ChangeToRegister(Reg, false);
1486 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1487 MachineRegisterInfo &MRI,
1488 MachineOperand &SuperReg,
1489 const TargetRegisterClass *SuperRC,
1491 const TargetRegisterClass *SubRC)
1493 assert(SuperReg.isReg());
1495 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1496 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1498 // Just in case the super register is itself a sub-register, copy it to a new
1499 // value so we don't need to worry about merging its subreg index with the
1500 // SubIdx passed to this function. The register coalescer should be able to
1501 // eliminate this extra copy.
1502 MachineBasicBlock *MBB = MI->getParent();
1503 DebugLoc DL = MI->getDebugLoc();
1505 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1506 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1508 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1509 .addReg(NewSuperReg, 0, SubIdx);
1514 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1515 MachineBasicBlock::iterator MII,
1516 MachineRegisterInfo &MRI,
1518 const TargetRegisterClass *SuperRC,
1520 const TargetRegisterClass *SubRC) const {
1522 // XXX - Is there a better way to do this?
1523 if (SubIdx == AMDGPU::sub0)
1524 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1525 if (SubIdx == AMDGPU::sub1)
1526 return MachineOperand::CreateImm(Op.getImm() >> 32);
1528 llvm_unreachable("Unhandled register index for immediate");
1531 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1533 return MachineOperand::CreateReg(SubReg, false);
1536 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1537 MachineBasicBlock::iterator MI,
1538 MachineRegisterInfo &MRI,
1539 const TargetRegisterClass *RC,
1540 const MachineOperand &Op) const {
1541 MachineBasicBlock *MBB = MI->getParent();
1542 DebugLoc DL = MI->getDebugLoc();
1543 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1544 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1545 unsigned Dst = MRI.createVirtualRegister(RC);
1547 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1549 .addImm(Op.getImm() & 0xFFFFFFFF);
1550 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1552 .addImm(Op.getImm() >> 32);
1554 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1556 .addImm(AMDGPU::sub0)
1558 .addImm(AMDGPU::sub1);
1560 Worklist.push_back(Lo);
1561 Worklist.push_back(Hi);
1566 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1567 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1568 assert(Inst->getNumExplicitOperands() == 3);
1569 MachineOperand Op1 = Inst->getOperand(1);
1570 Inst->RemoveOperand(1);
1571 Inst->addOperand(Op1);
1574 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1575 const MachineOperand *MO) const {
1576 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1577 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1578 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1579 const TargetRegisterClass *DefinedRC =
1580 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1582 MO = &MI->getOperand(OpIdx);
1584 if (isVALU(InstDesc.Opcode) &&
1585 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1587 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1588 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1591 const MachineOperand &Op = MI->getOperand(i);
1592 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1593 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1601 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1603 // In order to be legal, the common sub-class must be equal to the
1604 // class of the current operand. For example:
1606 // v_mov_b32 s0 ; Operand defined as vsrc_32
1607 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1609 // s_sendmsg 0, s0 ; Operand defined as m0reg
1610 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1612 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1616 // Handle non-register types that are treated like immediates.
1617 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1620 // This operand expects an immediate.
1624 return isImmOperandLegal(MI, OpIdx, *MO);
1627 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1628 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1630 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1631 AMDGPU::OpName::src0);
1632 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1633 AMDGPU::OpName::src1);
1634 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1635 AMDGPU::OpName::src2);
1638 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1640 if (!isOperandLegal(MI, Src0Idx))
1641 legalizeOpWithMove(MI, Src0Idx);
1644 if (isOperandLegal(MI, Src1Idx))
1647 // Usually src0 of VOP2 instructions allow more types of inputs
1648 // than src1, so try to commute the instruction to decrease our
1649 // chances of having to insert a MOV instruction to legalize src1.
1650 if (MI->isCommutable()) {
1651 if (commuteInstruction(MI))
1652 // If we are successful in commuting, then we know MI is legal, so
1657 legalizeOpWithMove(MI, Src1Idx);
1661 // XXX - Do any VOP3 instructions read VCC?
1663 if (isVOP3(MI->getOpcode())) {
1664 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1666 // Find the one SGPR operand we are allowed to use.
1667 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1669 for (unsigned i = 0; i < 3; ++i) {
1670 int Idx = VOP3Idx[i];
1673 MachineOperand &MO = MI->getOperand(Idx);
1676 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1677 continue; // VGPRs are legal
1679 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1681 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1682 SGPRReg = MO.getReg();
1683 // We can use one SGPR in each VOP3 instruction.
1686 } else if (!isLiteralConstant(MO, getOpSize(MI->getOpcode(), Idx))) {
1687 // If it is not a register and not a literal constant, then it must be
1688 // an inline constant which is always legal.
1691 // If we make it this far, then the operand is not legal and we must
1693 legalizeOpWithMove(MI, Idx);
1697 // Legalize REG_SEQUENCE and PHI
1698 // The register class of the operands much be the same type as the register
1699 // class of the output.
1700 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1701 MI->getOpcode() == AMDGPU::PHI) {
1702 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1703 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1704 if (!MI->getOperand(i).isReg() ||
1705 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1707 const TargetRegisterClass *OpRC =
1708 MRI.getRegClass(MI->getOperand(i).getReg());
1709 if (RI.hasVGPRs(OpRC)) {
1716 // If any of the operands are VGPR registers, then they all most be
1717 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1719 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1722 VRC = RI.getEquivalentVGPRClass(SRC);
1729 // Update all the operands so they have the same type.
1730 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1731 if (!MI->getOperand(i).isReg() ||
1732 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1734 unsigned DstReg = MRI.createVirtualRegister(RC);
1735 MachineBasicBlock *InsertBB;
1736 MachineBasicBlock::iterator Insert;
1737 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1738 InsertBB = MI->getParent();
1741 // MI is a PHI instruction.
1742 InsertBB = MI->getOperand(i + 1).getMBB();
1743 Insert = InsertBB->getFirstTerminator();
1745 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1746 get(AMDGPU::COPY), DstReg)
1747 .addOperand(MI->getOperand(i));
1748 MI->getOperand(i).setReg(DstReg);
1752 // Legalize INSERT_SUBREG
1753 // src0 must have the same register class as dst
1754 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1755 unsigned Dst = MI->getOperand(0).getReg();
1756 unsigned Src0 = MI->getOperand(1).getReg();
1757 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1758 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1759 if (DstRC != Src0RC) {
1760 MachineBasicBlock &MBB = *MI->getParent();
1761 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1762 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1764 MI->getOperand(1).setReg(NewSrc0);
1769 // Legalize MUBUF* instructions
1770 // FIXME: If we start using the non-addr64 instructions for compute, we
1771 // may need to legalize them here.
1773 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1774 if (SRsrcIdx != -1) {
1775 // We have an MUBUF instruction
1776 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1777 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1778 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1779 RI.getRegClass(SRsrcRC))) {
1780 // The operands are legal.
1781 // FIXME: We may need to legalize operands besided srsrc.
1785 MachineBasicBlock &MBB = *MI->getParent();
1786 // Extract the the ptr from the resource descriptor.
1788 // SRsrcPtrLo = srsrc:sub0
1789 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1790 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VGPR_32RegClass);
1792 // SRsrcPtrHi = srsrc:sub1
1793 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1794 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VGPR_32RegClass);
1796 // Create an empty resource descriptor
1797 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1798 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1799 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1800 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1801 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1804 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1808 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1809 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1811 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1813 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1814 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1816 .addImm(RsrcDataFormat >> 32);
1818 // NewSRsrc = {Zero64, SRsrcFormat}
1819 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1822 .addImm(AMDGPU::sub0_sub1)
1823 .addReg(SRsrcFormatLo)
1824 .addImm(AMDGPU::sub2)
1825 .addReg(SRsrcFormatHi)
1826 .addImm(AMDGPU::sub3);
1828 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1829 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1830 unsigned NewVAddrLo;
1831 unsigned NewVAddrHi;
1833 // This is already an ADDR64 instruction so we need to add the pointer
1834 // extracted from the resource descriptor to the current value of VAddr.
1835 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1836 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1838 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1839 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1842 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1843 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1845 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1846 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1849 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1850 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1851 .addReg(AMDGPU::VCC, RegState::Implicit);
1854 // This instructions is the _OFFSET variant, so we need to convert it to
1856 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1857 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1858 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1860 // Create the new instruction.
1861 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1862 MachineInstr *Addr64 =
1863 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1866 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1867 // This will be replaced later
1868 // with the new value of vaddr.
1869 .addOperand(*SOffset)
1870 .addOperand(*Offset)
1875 MI->removeFromParent();
1878 NewVAddrLo = SRsrcPtrLo;
1879 NewVAddrHi = SRsrcPtrHi;
1880 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1881 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1884 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1885 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1888 .addImm(AMDGPU::sub0)
1890 .addImm(AMDGPU::sub1);
1893 // Update the instruction to use NewVaddr
1894 VAddr->setReg(NewVAddr);
1895 // Update the instruction to use NewSRsrc
1896 SRsrc->setReg(NewSRsrc);
1900 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1901 const TargetRegisterClass *HalfRC,
1902 unsigned HalfImmOp, unsigned HalfSGPROp,
1903 MachineInstr *&Lo, MachineInstr *&Hi) const {
1905 DebugLoc DL = MI->getDebugLoc();
1906 MachineBasicBlock *MBB = MI->getParent();
1907 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1908 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1909 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1910 unsigned HalfSize = HalfRC->getSize();
1911 const MachineOperand *OffOp =
1912 getNamedOperand(*MI, AMDGPU::OpName::offset);
1913 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1915 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1918 bool isVI = RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
1919 unsigned OffScale = isVI ? 1 : 4;
1920 // Handle the _IMM variant
1921 unsigned LoOffset = OffOp->getImm() * OffScale;
1922 unsigned HiOffset = LoOffset + HalfSize;
1923 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1925 .addImm(LoOffset / OffScale);
1927 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1928 unsigned OffsetSGPR =
1929 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1930 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1931 .addImm(HiOffset); // The offset in register is in bytes.
1932 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1934 .addReg(OffsetSGPR);
1936 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1938 .addImm(HiOffset / OffScale);
1941 // Handle the _SGPR variant
1942 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1943 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1946 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1947 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1950 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1952 .addReg(OffsetSGPR);
1955 unsigned SubLo, SubHi;
1958 SubLo = AMDGPU::sub0;
1959 SubHi = AMDGPU::sub1;
1962 SubLo = AMDGPU::sub0_sub1;
1963 SubHi = AMDGPU::sub2_sub3;
1966 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1967 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1970 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1971 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1974 llvm_unreachable("Unhandled HalfSize");
1977 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1978 .addOperand(MI->getOperand(0))
1985 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1986 MachineBasicBlock *MBB = MI->getParent();
1987 switch (MI->getOpcode()) {
1988 case AMDGPU::S_LOAD_DWORD_IMM:
1989 case AMDGPU::S_LOAD_DWORD_SGPR:
1990 case AMDGPU::S_LOAD_DWORDX2_IMM:
1991 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1992 case AMDGPU::S_LOAD_DWORDX4_IMM:
1993 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1994 unsigned NewOpcode = getVALUOp(*MI);
1998 if (MI->getOperand(2).isReg()) {
1999 RegOffset = MI->getOperand(2).getReg();
2002 assert(MI->getOperand(2).isImm());
2003 // SMRD instructions take a dword offsets on SI and byte offset on VI
2004 // and MUBUF instructions always take a byte offset.
2005 ImmOffset = MI->getOperand(2).getImm();
2006 if (RI.ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
2008 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2010 if (isUInt<12>(ImmOffset)) {
2011 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2015 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2022 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2023 unsigned DWord0 = RegOffset;
2024 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2025 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2026 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2027 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2029 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2031 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2032 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2033 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2034 .addImm(RsrcDataFormat >> 32);
2035 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2037 .addImm(AMDGPU::sub0)
2039 .addImm(AMDGPU::sub1)
2041 .addImm(AMDGPU::sub2)
2043 .addImm(AMDGPU::sub3);
2044 MI->setDesc(get(NewOpcode));
2045 if (MI->getOperand(2).isReg()) {
2046 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
2048 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
2050 MI->getOperand(1).setReg(SRsrc);
2051 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
2052 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
2053 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // glc
2054 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // slc
2055 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // tfe
2057 const TargetRegisterClass *NewDstRC =
2058 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
2060 unsigned DstReg = MI->getOperand(0).getReg();
2061 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2062 MRI.replaceRegWith(DstReg, NewDstReg);
2065 case AMDGPU::S_LOAD_DWORDX8_IMM:
2066 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
2067 MachineInstr *Lo, *Hi;
2068 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2069 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2070 MI->eraseFromParent();
2071 moveSMRDToVALU(Lo, MRI);
2072 moveSMRDToVALU(Hi, MRI);
2076 case AMDGPU::S_LOAD_DWORDX16_IMM:
2077 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
2078 MachineInstr *Lo, *Hi;
2079 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2080 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2081 MI->eraseFromParent();
2082 moveSMRDToVALU(Lo, MRI);
2083 moveSMRDToVALU(Hi, MRI);
2089 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2090 SmallVector<MachineInstr *, 128> Worklist;
2091 Worklist.push_back(&TopInst);
2093 while (!Worklist.empty()) {
2094 MachineInstr *Inst = Worklist.pop_back_val();
2095 MachineBasicBlock *MBB = Inst->getParent();
2096 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2098 unsigned Opcode = Inst->getOpcode();
2099 unsigned NewOpcode = getVALUOp(*Inst);
2101 // Handle some special cases
2104 if (isSMRD(Inst->getOpcode())) {
2105 moveSMRDToVALU(Inst, MRI);
2108 case AMDGPU::S_MOV_B64: {
2109 DebugLoc DL = Inst->getDebugLoc();
2111 // If the source operand is a register we can replace this with a
2113 if (Inst->getOperand(1).isReg()) {
2114 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
2115 .addOperand(Inst->getOperand(0))
2116 .addOperand(Inst->getOperand(1));
2117 Worklist.push_back(Copy);
2119 // Otherwise, we need to split this into two movs, because there is
2120 // no 64-bit VALU move instruction.
2121 unsigned Reg = Inst->getOperand(0).getReg();
2122 unsigned Dst = split64BitImm(Worklist,
2125 MRI.getRegClass(Reg),
2126 Inst->getOperand(1));
2127 MRI.replaceRegWith(Reg, Dst);
2129 Inst->eraseFromParent();
2132 case AMDGPU::S_AND_B64:
2133 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
2134 Inst->eraseFromParent();
2137 case AMDGPU::S_OR_B64:
2138 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
2139 Inst->eraseFromParent();
2142 case AMDGPU::S_XOR_B64:
2143 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
2144 Inst->eraseFromParent();
2147 case AMDGPU::S_NOT_B64:
2148 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
2149 Inst->eraseFromParent();
2152 case AMDGPU::S_BCNT1_I32_B64:
2153 splitScalar64BitBCNT(Worklist, Inst);
2154 Inst->eraseFromParent();
2157 case AMDGPU::S_BFE_I64: {
2158 splitScalar64BitBFE(Worklist, Inst);
2159 Inst->eraseFromParent();
2163 case AMDGPU::S_LSHL_B32:
2164 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2165 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2169 case AMDGPU::S_ASHR_I32:
2170 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2171 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2175 case AMDGPU::S_LSHR_B32:
2176 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2177 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2181 case AMDGPU::S_LSHL_B64:
2182 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2183 NewOpcode = AMDGPU::V_LSHLREV_B64;
2187 case AMDGPU::S_ASHR_I64:
2188 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2189 NewOpcode = AMDGPU::V_ASHRREV_I64;
2193 case AMDGPU::S_LSHR_B64:
2194 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2195 NewOpcode = AMDGPU::V_LSHRREV_B64;
2200 case AMDGPU::S_BFE_U64:
2201 case AMDGPU::S_BFM_B64:
2202 llvm_unreachable("Moving this op to VALU not implemented");
2205 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2206 // We cannot move this instruction to the VALU, so we should try to
2207 // legalize its operands instead.
2208 legalizeOperands(Inst);
2212 // Use the new VALU Opcode.
2213 const MCInstrDesc &NewDesc = get(NewOpcode);
2214 Inst->setDesc(NewDesc);
2216 // Remove any references to SCC. Vector instructions can't read from it, and
2217 // We're just about to add the implicit use / defs of VCC, and we don't want
2219 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2220 MachineOperand &Op = Inst->getOperand(i);
2221 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2222 Inst->RemoveOperand(i);
2225 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2226 // We are converting these to a BFE, so we need to add the missing
2227 // operands for the size and offset.
2228 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2229 Inst->addOperand(MachineOperand::CreateImm(0));
2230 Inst->addOperand(MachineOperand::CreateImm(Size));
2232 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2233 // The VALU version adds the second operand to the result, so insert an
2235 Inst->addOperand(MachineOperand::CreateImm(0));
2238 addDescImplicitUseDef(NewDesc, Inst);
2240 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2241 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2242 // If we need to move this to VGPRs, we need to unpack the second operand
2243 // back into the 2 separate ones for bit offset and width.
2244 assert(OffsetWidthOp.isImm() &&
2245 "Scalar BFE is only implemented for constant width and offset");
2246 uint32_t Imm = OffsetWidthOp.getImm();
2248 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2249 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2250 Inst->RemoveOperand(2); // Remove old immediate.
2251 Inst->addOperand(MachineOperand::CreateImm(Offset));
2252 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2255 // Update the destination register class.
2257 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2260 // For target instructions, getOpRegClass just returns the virtual
2261 // register class associated with the operand, so we need to find an
2262 // equivalent VGPR register class in order to move the instruction to the
2266 case AMDGPU::REG_SEQUENCE:
2267 case AMDGPU::INSERT_SUBREG:
2268 if (RI.hasVGPRs(NewDstRC))
2270 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2278 unsigned DstReg = Inst->getOperand(0).getReg();
2279 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2280 MRI.replaceRegWith(DstReg, NewDstReg);
2282 // Legalize the operands
2283 legalizeOperands(Inst);
2285 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
2286 E = MRI.use_end(); I != E; ++I) {
2287 MachineInstr &UseMI = *I->getParent();
2288 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2289 Worklist.push_back(&UseMI);
2295 //===----------------------------------------------------------------------===//
2296 // Indirect addressing callbacks
2297 //===----------------------------------------------------------------------===//
2299 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2300 unsigned Channel) const {
2301 assert(Channel == 0);
2305 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2306 return &AMDGPU::VGPR_32RegClass;
2309 void SIInstrInfo::splitScalar64BitUnaryOp(
2310 SmallVectorImpl<MachineInstr *> &Worklist,
2312 unsigned Opcode) const {
2313 MachineBasicBlock &MBB = *Inst->getParent();
2314 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2316 MachineOperand &Dest = Inst->getOperand(0);
2317 MachineOperand &Src0 = Inst->getOperand(1);
2318 DebugLoc DL = Inst->getDebugLoc();
2320 MachineBasicBlock::iterator MII = Inst;
2322 const MCInstrDesc &InstDesc = get(Opcode);
2323 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2324 MRI.getRegClass(Src0.getReg()) :
2325 &AMDGPU::SGPR_32RegClass;
2327 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2329 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2330 AMDGPU::sub0, Src0SubRC);
2332 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2333 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2335 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2336 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2337 .addOperand(SrcReg0Sub0);
2339 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2340 AMDGPU::sub1, Src0SubRC);
2342 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2343 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2344 .addOperand(SrcReg0Sub1);
2346 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2347 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2349 .addImm(AMDGPU::sub0)
2351 .addImm(AMDGPU::sub1);
2353 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2355 // Try to legalize the operands in case we need to swap the order to keep it
2357 Worklist.push_back(LoHalf);
2358 Worklist.push_back(HiHalf);
2361 void SIInstrInfo::splitScalar64BitBinaryOp(
2362 SmallVectorImpl<MachineInstr *> &Worklist,
2364 unsigned Opcode) const {
2365 MachineBasicBlock &MBB = *Inst->getParent();
2366 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2368 MachineOperand &Dest = Inst->getOperand(0);
2369 MachineOperand &Src0 = Inst->getOperand(1);
2370 MachineOperand &Src1 = Inst->getOperand(2);
2371 DebugLoc DL = Inst->getDebugLoc();
2373 MachineBasicBlock::iterator MII = Inst;
2375 const MCInstrDesc &InstDesc = get(Opcode);
2376 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2377 MRI.getRegClass(Src0.getReg()) :
2378 &AMDGPU::SGPR_32RegClass;
2380 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2381 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2382 MRI.getRegClass(Src1.getReg()) :
2383 &AMDGPU::SGPR_32RegClass;
2385 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2387 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2388 AMDGPU::sub0, Src0SubRC);
2389 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2390 AMDGPU::sub0, Src1SubRC);
2392 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2393 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2395 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2396 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2397 .addOperand(SrcReg0Sub0)
2398 .addOperand(SrcReg1Sub0);
2400 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2401 AMDGPU::sub1, Src0SubRC);
2402 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2403 AMDGPU::sub1, Src1SubRC);
2405 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2406 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2407 .addOperand(SrcReg0Sub1)
2408 .addOperand(SrcReg1Sub1);
2410 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2411 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2413 .addImm(AMDGPU::sub0)
2415 .addImm(AMDGPU::sub1);
2417 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2419 // Try to legalize the operands in case we need to swap the order to keep it
2421 Worklist.push_back(LoHalf);
2422 Worklist.push_back(HiHalf);
2425 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2426 MachineInstr *Inst) const {
2427 MachineBasicBlock &MBB = *Inst->getParent();
2428 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2430 MachineBasicBlock::iterator MII = Inst;
2431 DebugLoc DL = Inst->getDebugLoc();
2433 MachineOperand &Dest = Inst->getOperand(0);
2434 MachineOperand &Src = Inst->getOperand(1);
2436 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2437 const TargetRegisterClass *SrcRC = Src.isReg() ?
2438 MRI.getRegClass(Src.getReg()) :
2439 &AMDGPU::SGPR_32RegClass;
2441 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2442 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2444 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2446 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2447 AMDGPU::sub0, SrcSubRC);
2448 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2449 AMDGPU::sub1, SrcSubRC);
2451 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2452 .addOperand(SrcRegSub0)
2455 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2456 .addOperand(SrcRegSub1)
2459 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2461 Worklist.push_back(First);
2462 Worklist.push_back(Second);
2465 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2466 MachineInstr *Inst) const {
2467 MachineBasicBlock &MBB = *Inst->getParent();
2468 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2469 MachineBasicBlock::iterator MII = Inst;
2470 DebugLoc DL = Inst->getDebugLoc();
2472 MachineOperand &Dest = Inst->getOperand(0);
2473 uint32_t Imm = Inst->getOperand(2).getImm();
2474 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2475 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2479 // Only sext_inreg cases handled.
2480 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2485 if (BitWidth < 32) {
2486 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2487 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2488 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2490 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2491 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2495 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2499 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2501 .addImm(AMDGPU::sub0)
2503 .addImm(AMDGPU::sub1);
2505 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2509 MachineOperand &Src = Inst->getOperand(1);
2510 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2511 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2513 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2515 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2517 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2518 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2519 .addImm(AMDGPU::sub0)
2521 .addImm(AMDGPU::sub1);
2523 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2526 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2527 MachineInstr *Inst) const {
2528 // Add the implict and explicit register definitions.
2529 if (NewDesc.ImplicitUses) {
2530 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2531 unsigned Reg = NewDesc.ImplicitUses[i];
2532 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2536 if (NewDesc.ImplicitDefs) {
2537 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2538 unsigned Reg = NewDesc.ImplicitDefs[i];
2539 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2544 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2545 int OpIndices[3]) const {
2546 const MCInstrDesc &Desc = get(MI->getOpcode());
2548 // Find the one SGPR operand we are allowed to use.
2549 unsigned SGPRReg = AMDGPU::NoRegister;
2551 // First we need to consider the instruction's operand requirements before
2552 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2553 // of VCC, but we are still bound by the constant bus requirement to only use
2556 // If the operand's class is an SGPR, we can never move it.
2558 for (const MachineOperand &MO : MI->implicit_operands()) {
2559 // We only care about reads.
2563 if (MO.getReg() == AMDGPU::VCC)
2566 if (MO.getReg() == AMDGPU::FLAT_SCR)
2567 return AMDGPU::FLAT_SCR;
2570 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2571 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2573 for (unsigned i = 0; i < 3; ++i) {
2574 int Idx = OpIndices[i];
2578 const MachineOperand &MO = MI->getOperand(Idx);
2579 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2580 SGPRReg = MO.getReg();
2582 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2583 UsedSGPRs[i] = MO.getReg();
2586 if (SGPRReg != AMDGPU::NoRegister)
2589 // We don't have a required SGPR operand, so we have a bit more freedom in
2590 // selecting operands to move.
2592 // Try to select the most used SGPR. If an SGPR is equal to one of the
2593 // others, we choose that.
2596 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2597 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2599 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2600 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2601 SGPRReg = UsedSGPRs[0];
2604 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2605 if (UsedSGPRs[1] == UsedSGPRs[2])
2606 SGPRReg = UsedSGPRs[1];
2612 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2613 MachineBasicBlock *MBB,
2614 MachineBasicBlock::iterator I,
2616 unsigned Address, unsigned OffsetReg) const {
2617 const DebugLoc &DL = MBB->findDebugLoc(I);
2618 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2619 getIndirectIndexBegin(*MBB->getParent()));
2621 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2622 .addReg(IndirectBaseReg, RegState::Define)
2623 .addOperand(I->getOperand(0))
2624 .addReg(IndirectBaseReg)
2630 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2631 MachineBasicBlock *MBB,
2632 MachineBasicBlock::iterator I,
2634 unsigned Address, unsigned OffsetReg) const {
2635 const DebugLoc &DL = MBB->findDebugLoc(I);
2636 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2637 getIndirectIndexBegin(*MBB->getParent()));
2639 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2640 .addOperand(I->getOperand(0))
2641 .addOperand(I->getOperand(1))
2642 .addReg(IndirectBaseReg)
2648 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2649 const MachineFunction &MF) const {
2650 int End = getIndirectIndexEnd(MF);
2651 int Begin = getIndirectIndexBegin(MF);
2657 for (int Index = Begin; Index <= End; ++Index)
2658 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2660 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2661 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2663 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2664 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2666 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2667 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2669 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2670 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2672 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2673 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2676 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2677 unsigned OperandName) const {
2678 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2682 return &MI.getOperand(Idx);
2685 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2686 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2687 if (ST.isAmdHsaOS())
2688 RsrcDataFormat |= (1ULL << 56);
2690 return RsrcDataFormat;